Searched refs:clk (Results 126 - 150 of 4102) sorted by last modified time

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/linux-master/drivers/media/platform/st/stm32/stm32-dcmipp/
H A Ddcmipp-core.c11 #include <linux/clk.h>
43 struct clk *kclk;
414 struct clk *kclk;
/linux-master/drivers/media/platform/st/sti/hva/
H A Dhva-hw.c8 #include <linux/clk.h>
326 hva->clk = devm_clk_get(dev, "clk_hva");
327 if (IS_ERR(hva->clk)) {
329 return PTR_ERR(hva->clk);
332 ret = clk_prepare(hva->clk);
335 hva->clk = ERR_PTR(-EINVAL);
409 clk_unprepare(hva->clk);
429 clk_disable_unprepare(hva->clk);
438 if (clk_prepare_enable(hva->clk)) {
439 dev_err(hva->dev, "%s failed to prepare hva clk\
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/linux-master/drivers/media/platform/st/sti/c8sectpfe/
H A Dc8sectpfe-core.c12 #include <linux/clk.h>
777 "invert-ts-clk");
831 "channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss.c10 #include <linux/clk.h>
1264 ret = clk_prepare_enable(clock[i].clk);
1275 clk_disable_unprepare(clock[i].clk);
1290 clk_disable_unprepare(clock[i].clk);
1415 lncfg->clk.pos = mipi_csi2->clock_lane;
1416 lncfg->clk.pol = mipi_csi2->lane_polarities[0];
H A Dcamss.h130 struct clk *clk; member in struct:camss_clock
H A Dcamss-vfe.c10 #include <linux/clk.h>
590 rate = clk_round_rate(clock->clk, clock->freq[j]);
592 dev_err(dev, "clk round rate failed: %ld\n",
597 ret = clk_set_rate(clock->clk, rate);
599 dev_err(dev, "clk set rate failed: %d\n", ret);
656 rate = clk_get_rate(clock->clk);
1453 clock->clk = devm_clk_get(dev, res->clock[i]);
1454 if (IS_ERR(clock->clk))
1455 return PTR_ERR(clock->clk);
H A Dcamss-csiphy.c10 #include <linux/clk.h>
166 round_rate = clk_round_rate(clock->clk, clock->freq[j]);
168 dev_err(dev, "clk round rate failed: %ld\n",
175 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate);
177 dev_err(dev, "clk set rate failed: %d\n", ret);
271 /* Enforce reg write ordering between clk mux & lane enabling */
643 clock->clk = devm_clk_get(dev, res->clock[i]);
644 if (IS_ERR(clock->clk))
645 return PTR_ERR(clock->clk);
/linux-master/drivers/media/platform/nxp/
H A Dimx-mipi-csis.c15 #include <linux/clk.h>
721 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk,
/linux-master/drivers/media/platform/mediatek/vcodec/encoder/
H A Dmtk_vcodec_enc_pm.c7 #include <linux/clk.h>
46 dev_err(pm->dev, "[MTK VCODEC] venc failed to get clk name %d", i);
/linux-master/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-core.c7 #include <linux/clk.h>
/linux-master/drivers/media/platform/chips-media/wave5/
H A Dwave5-vpu.c10 #include <linux/clk.h>
/linux-master/drivers/media/platform/cadence/
H A Dcdns-csi2rx.c8 #include <linux/clk.h>
85 struct clk *sys_clk;
86 struct clk *p_clk;
87 struct clk *pixel_clk[CSI2RX_STREAMS_MAX];
242 /* Enable DPHY clk and data lanes. */
/linux-master/drivers/media/platform/broadcom/
H A Dbcm2835-unicam.c34 #include <linux/clk.h>
190 struct clk *clock;
192 struct clk *vpu_clock;
/linux-master/drivers/media/pci/mgb4/
H A Dmgb4_core.c24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
/linux-master/drivers/media/pci/cobalt/
H A Dcobalt-v4l2.c150 u64 clk = bt->pixelclock; local
153 clk = div_u64(clk * 1000ULL, 1001);
154 if (!cobalt_cpld_set_freq(cobalt, clk)) {
/linux-master/drivers/media/i2c/
H A Dtc358746.c12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
150 struct clk *refclk;
1251 /* MCLK clk provider support is optional */
1659 * Enable the PLL here since it can be called by the clk-framework or by
H A Dtc358743.c19 #include <linux/clk.h>
1898 struct clk *refclk;
H A Dst-mipid02.c12 #include <linux/clk.h>
95 struct clk *xclk;
343 dev_err(&client->dev, "clk lane must be map to lane 0\n");
H A Dov4689.c9 #include <linux/clk.h>
126 struct clk *xvclk;
H A Dov2740.c6 #include <linux/clk.h>
528 struct clk *clk; member in struct:ov2740
1297 clk_disable_unprepare(ov2740->clk);
1307 ret = clk_prepare_enable(ov2740->clk);
1347 ov2740->clk = devm_clk_get_optional(dev, "clk");
1348 if (IS_ERR(ov2740->clk))
1349 return dev_err_probe(dev, PTR_ERR(ov2740->clk),
H A Dov2680.c13 #include <linux/clk.h>
155 struct clk *xvclk;
H A Dimx335.c9 #include <linux/clk.h>
204 struct clk *inclk;
H A Dimx219.c17 #include <linux/clk.h>
320 struct clk *xclk; /* system clock to IMX219 */
H A Dimx214.c9 #include <linux/clk.h>
57 struct clk *xclk;
467 dev_err(imx214->dev, "clk prepare enable failed\n");
H A Dhi556.c6 #include <linux/clk.h>
641 struct clk *clk; member in struct:hi556
1302 clk_disable_unprepare(hi556->clk);
1312 ret = clk_prepare_enable(hi556->clk);
1319 clk_disable_unprepare(hi556->clk);
1353 hi556->clk = devm_clk_get_optional(&client->dev, "clk");
1354 if (IS_ERR(hi556->clk))
1355 return dev_err_probe(&client->dev, PTR_ERR(hi556->clk),
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