1// SPDX-License-Identifier: GPL-2.0 2/* 3 * camss-csiphy.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/interrupt.h> 13#include <linux/io.h> 14#include <linux/kernel.h> 15#include <linux/of.h> 16#include <linux/platform_device.h> 17#include <linux/pm_runtime.h> 18#include <media/media-entity.h> 19#include <media/v4l2-device.h> 20#include <media/v4l2-subdev.h> 21 22#include "camss-csiphy.h" 23#include "camss.h" 24 25#define MSM_CSIPHY_NAME "msm_csiphy" 26 27struct csiphy_format { 28 u32 code; 29 u8 bpp; 30}; 31 32static const struct csiphy_format csiphy_formats_8x16[] = { 33 { MEDIA_BUS_FMT_UYVY8_1X16, 8 }, 34 { MEDIA_BUS_FMT_VYUY8_1X16, 8 }, 35 { MEDIA_BUS_FMT_YUYV8_1X16, 8 }, 36 { MEDIA_BUS_FMT_YVYU8_1X16, 8 }, 37 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 38 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 39 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 40 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 41 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 42 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 43 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 44 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 45 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 46 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 47 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 48 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 49 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 50}; 51 52static const struct csiphy_format csiphy_formats_8x96[] = { 53 { MEDIA_BUS_FMT_UYVY8_1X16, 8 }, 54 { MEDIA_BUS_FMT_VYUY8_1X16, 8 }, 55 { MEDIA_BUS_FMT_YUYV8_1X16, 8 }, 56 { MEDIA_BUS_FMT_YVYU8_1X16, 8 }, 57 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 58 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 59 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 60 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 61 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 62 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 63 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 64 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 65 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 66 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 67 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 68 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 69 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 70 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 71 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 72 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 73 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 74}; 75 76static const struct csiphy_format csiphy_formats_sdm845[] = { 77 { MEDIA_BUS_FMT_UYVY8_1X16, 8 }, 78 { MEDIA_BUS_FMT_VYUY8_1X16, 8 }, 79 { MEDIA_BUS_FMT_YUYV8_1X16, 8 }, 80 { MEDIA_BUS_FMT_YVYU8_1X16, 8 }, 81 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 82 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 83 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 84 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 85 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 86 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 87 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 88 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 89 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 90 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 91 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 92 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 93 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 94 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 95 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 96 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 97 { MEDIA_BUS_FMT_Y8_1X8, 8 }, 98 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 99}; 100 101/* 102 * csiphy_get_bpp - map media bus format to bits per pixel 103 * @formats: supported media bus formats array 104 * @nformats: size of @formats array 105 * @code: media bus format code 106 * 107 * Return number of bits per pixel 108 */ 109static u8 csiphy_get_bpp(const struct csiphy_format *formats, 110 unsigned int nformats, u32 code) 111{ 112 unsigned int i; 113 114 for (i = 0; i < nformats; i++) 115 if (code == formats[i].code) 116 return formats[i].bpp; 117 118 WARN(1, "Unknown format\n"); 119 120 return formats[0].bpp; 121} 122 123/* 124 * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module 125 * @csiphy: CSIPHY device 126 */ 127static int csiphy_set_clock_rates(struct csiphy_device *csiphy) 128{ 129 struct device *dev = csiphy->camss->dev; 130 s64 link_freq; 131 int i, j; 132 int ret; 133 134 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 135 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 136 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 137 138 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 139 if (link_freq < 0) 140 link_freq = 0; 141 142 for (i = 0; i < csiphy->nclocks; i++) { 143 struct camss_clock *clock = &csiphy->clock[i]; 144 145 if (csiphy->rate_set[i]) { 146 u64 min_rate = link_freq / 4; 147 long round_rate; 148 149 camss_add_clock_margin(&min_rate); 150 151 for (j = 0; j < clock->nfreqs; j++) 152 if (min_rate < clock->freq[j]) 153 break; 154 155 if (j == clock->nfreqs) { 156 dev_err(dev, 157 "Pixel clock is too high for CSIPHY\n"); 158 return -EINVAL; 159 } 160 161 /* if sensor pixel clock is not available */ 162 /* set highest possible CSIPHY clock rate */ 163 if (min_rate == 0) 164 j = clock->nfreqs - 1; 165 166 round_rate = clk_round_rate(clock->clk, clock->freq[j]); 167 if (round_rate < 0) { 168 dev_err(dev, "clk round rate failed: %ld\n", 169 round_rate); 170 return -EINVAL; 171 } 172 173 csiphy->timer_clk_rate = round_rate; 174 175 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); 176 if (ret < 0) { 177 dev_err(dev, "clk set rate failed: %d\n", ret); 178 return ret; 179 } 180 } 181 } 182 183 return 0; 184} 185 186/* 187 * csiphy_set_power - Power on/off CSIPHY module 188 * @sd: CSIPHY V4L2 subdevice 189 * @on: Requested power state 190 * 191 * Return 0 on success or a negative error code otherwise 192 */ 193static int csiphy_set_power(struct v4l2_subdev *sd, int on) 194{ 195 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 196 struct device *dev = csiphy->camss->dev; 197 198 if (on) { 199 int ret; 200 201 ret = pm_runtime_resume_and_get(dev); 202 if (ret < 0) 203 return ret; 204 205 ret = csiphy_set_clock_rates(csiphy); 206 if (ret < 0) { 207 pm_runtime_put_sync(dev); 208 return ret; 209 } 210 211 ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev); 212 if (ret < 0) { 213 pm_runtime_put_sync(dev); 214 return ret; 215 } 216 217 enable_irq(csiphy->irq); 218 219 csiphy->ops->reset(csiphy); 220 221 csiphy->ops->hw_version_read(csiphy, dev); 222 } else { 223 disable_irq(csiphy->irq); 224 225 camss_disable_clocks(csiphy->nclocks, csiphy->clock); 226 227 pm_runtime_put_sync(dev); 228 } 229 230 return 0; 231} 232 233/* 234 * csiphy_stream_on - Enable streaming on CSIPHY module 235 * @csiphy: CSIPHY device 236 * 237 * Helper function to enable streaming on CSIPHY module. 238 * Main configuration of CSIPHY module is also done here. 239 * 240 * Return 0 on success or a negative error code otherwise 241 */ 242static int csiphy_stream_on(struct csiphy_device *csiphy) 243{ 244 struct csiphy_config *cfg = &csiphy->cfg; 245 s64 link_freq; 246 u8 lane_mask = csiphy->ops->get_lane_mask(&cfg->csi2->lane_cfg); 247 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 248 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 249 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 250 u8 val; 251 252 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 253 254 if (link_freq < 0) { 255 dev_err(csiphy->camss->dev, 256 "Cannot get CSI2 transmitter's link frequency\n"); 257 return -EINVAL; 258 } 259 260 if (csiphy->base_clk_mux) { 261 val = readl_relaxed(csiphy->base_clk_mux); 262 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { 263 val &= ~0xf0; 264 val |= cfg->csid_id << 4; 265 } else { 266 val &= ~0xf; 267 val |= cfg->csid_id; 268 } 269 writel_relaxed(val, csiphy->base_clk_mux); 270 271 /* Enforce reg write ordering between clk mux & lane enabling */ 272 wmb(); 273 } 274 275 csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); 276 277 return 0; 278} 279 280/* 281 * csiphy_stream_off - Disable streaming on CSIPHY module 282 * @csiphy: CSIPHY device 283 * 284 * Helper function to disable streaming on CSIPHY module 285 */ 286static void csiphy_stream_off(struct csiphy_device *csiphy) 287{ 288 csiphy->ops->lanes_disable(csiphy, &csiphy->cfg); 289} 290 291 292/* 293 * csiphy_set_stream - Enable/disable streaming on CSIPHY module 294 * @sd: CSIPHY V4L2 subdevice 295 * @enable: Requested streaming state 296 * 297 * Return 0 on success or a negative error code otherwise 298 */ 299static int csiphy_set_stream(struct v4l2_subdev *sd, int enable) 300{ 301 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 302 int ret = 0; 303 304 if (enable) 305 ret = csiphy_stream_on(csiphy); 306 else 307 csiphy_stream_off(csiphy); 308 309 return ret; 310} 311 312/* 313 * __csiphy_get_format - Get pointer to format structure 314 * @csiphy: CSIPHY device 315 * @sd_state: V4L2 subdev state 316 * @pad: pad from which format is requested 317 * @which: TRY or ACTIVE format 318 * 319 * Return pointer to TRY or ACTIVE format structure 320 */ 321static struct v4l2_mbus_framefmt * 322__csiphy_get_format(struct csiphy_device *csiphy, 323 struct v4l2_subdev_state *sd_state, 324 unsigned int pad, 325 enum v4l2_subdev_format_whence which) 326{ 327 if (which == V4L2_SUBDEV_FORMAT_TRY) 328 return v4l2_subdev_state_get_format(sd_state, pad); 329 330 return &csiphy->fmt[pad]; 331} 332 333/* 334 * csiphy_try_format - Handle try format by pad subdev method 335 * @csiphy: CSIPHY device 336 * @sd_state: V4L2 subdev state 337 * @pad: pad on which format is requested 338 * @fmt: pointer to v4l2 format structure 339 * @which: wanted subdev format 340 */ 341static void csiphy_try_format(struct csiphy_device *csiphy, 342 struct v4l2_subdev_state *sd_state, 343 unsigned int pad, 344 struct v4l2_mbus_framefmt *fmt, 345 enum v4l2_subdev_format_whence which) 346{ 347 unsigned int i; 348 349 switch (pad) { 350 case MSM_CSIPHY_PAD_SINK: 351 /* Set format on sink pad */ 352 353 for (i = 0; i < csiphy->nformats; i++) 354 if (fmt->code == csiphy->formats[i].code) 355 break; 356 357 /* If not found, use UYVY as default */ 358 if (i >= csiphy->nformats) 359 fmt->code = MEDIA_BUS_FMT_UYVY8_1X16; 360 361 fmt->width = clamp_t(u32, fmt->width, 1, 8191); 362 fmt->height = clamp_t(u32, fmt->height, 1, 8191); 363 364 fmt->field = V4L2_FIELD_NONE; 365 fmt->colorspace = V4L2_COLORSPACE_SRGB; 366 367 break; 368 369 case MSM_CSIPHY_PAD_SRC: 370 /* Set and return a format same as sink pad */ 371 372 *fmt = *__csiphy_get_format(csiphy, sd_state, 373 MSM_CSID_PAD_SINK, 374 which); 375 376 break; 377 } 378} 379 380/* 381 * csiphy_enum_mbus_code - Handle pixel format enumeration 382 * @sd: CSIPHY V4L2 subdevice 383 * @sd_state: V4L2 subdev state 384 * @code: pointer to v4l2_subdev_mbus_code_enum structure 385 * return -EINVAL or zero on success 386 */ 387static int csiphy_enum_mbus_code(struct v4l2_subdev *sd, 388 struct v4l2_subdev_state *sd_state, 389 struct v4l2_subdev_mbus_code_enum *code) 390{ 391 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 392 struct v4l2_mbus_framefmt *format; 393 394 if (code->pad == MSM_CSIPHY_PAD_SINK) { 395 if (code->index >= csiphy->nformats) 396 return -EINVAL; 397 398 code->code = csiphy->formats[code->index].code; 399 } else { 400 if (code->index > 0) 401 return -EINVAL; 402 403 format = __csiphy_get_format(csiphy, sd_state, 404 MSM_CSIPHY_PAD_SINK, 405 code->which); 406 407 code->code = format->code; 408 } 409 410 return 0; 411} 412 413/* 414 * csiphy_enum_frame_size - Handle frame size enumeration 415 * @sd: CSIPHY V4L2 subdevice 416 * @sd_state: V4L2 subdev state 417 * @fse: pointer to v4l2_subdev_frame_size_enum structure 418 * return -EINVAL or zero on success 419 */ 420static int csiphy_enum_frame_size(struct v4l2_subdev *sd, 421 struct v4l2_subdev_state *sd_state, 422 struct v4l2_subdev_frame_size_enum *fse) 423{ 424 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 425 struct v4l2_mbus_framefmt format; 426 427 if (fse->index != 0) 428 return -EINVAL; 429 430 format.code = fse->code; 431 format.width = 1; 432 format.height = 1; 433 csiphy_try_format(csiphy, sd_state, fse->pad, &format, fse->which); 434 fse->min_width = format.width; 435 fse->min_height = format.height; 436 437 if (format.code != fse->code) 438 return -EINVAL; 439 440 format.code = fse->code; 441 format.width = -1; 442 format.height = -1; 443 csiphy_try_format(csiphy, sd_state, fse->pad, &format, fse->which); 444 fse->max_width = format.width; 445 fse->max_height = format.height; 446 447 return 0; 448} 449 450/* 451 * csiphy_get_format - Handle get format by pads subdev method 452 * @sd: CSIPHY V4L2 subdevice 453 * @sd_state: V4L2 subdev state 454 * @fmt: pointer to v4l2 subdev format structure 455 * 456 * Return -EINVAL or zero on success 457 */ 458static int csiphy_get_format(struct v4l2_subdev *sd, 459 struct v4l2_subdev_state *sd_state, 460 struct v4l2_subdev_format *fmt) 461{ 462 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 463 struct v4l2_mbus_framefmt *format; 464 465 format = __csiphy_get_format(csiphy, sd_state, fmt->pad, fmt->which); 466 if (format == NULL) 467 return -EINVAL; 468 469 fmt->format = *format; 470 471 return 0; 472} 473 474/* 475 * csiphy_set_format - Handle set format by pads subdev method 476 * @sd: CSIPHY V4L2 subdevice 477 * @sd_state: V4L2 subdev state 478 * @fmt: pointer to v4l2 subdev format structure 479 * 480 * Return -EINVAL or zero on success 481 */ 482static int csiphy_set_format(struct v4l2_subdev *sd, 483 struct v4l2_subdev_state *sd_state, 484 struct v4l2_subdev_format *fmt) 485{ 486 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 487 struct v4l2_mbus_framefmt *format; 488 489 format = __csiphy_get_format(csiphy, sd_state, fmt->pad, fmt->which); 490 if (format == NULL) 491 return -EINVAL; 492 493 csiphy_try_format(csiphy, sd_state, fmt->pad, &fmt->format, 494 fmt->which); 495 *format = fmt->format; 496 497 /* Propagate the format from sink to source */ 498 if (fmt->pad == MSM_CSIPHY_PAD_SINK) { 499 format = __csiphy_get_format(csiphy, sd_state, 500 MSM_CSIPHY_PAD_SRC, 501 fmt->which); 502 503 *format = fmt->format; 504 csiphy_try_format(csiphy, sd_state, MSM_CSIPHY_PAD_SRC, 505 format, 506 fmt->which); 507 } 508 509 return 0; 510} 511 512/* 513 * csiphy_init_formats - Initialize formats on all pads 514 * @sd: CSIPHY V4L2 subdevice 515 * @fh: V4L2 subdev file handle 516 * 517 * Initialize all pad formats with default values. 518 * 519 * Return 0 on success or a negative error code otherwise 520 */ 521static int csiphy_init_formats(struct v4l2_subdev *sd, 522 struct v4l2_subdev_fh *fh) 523{ 524 struct v4l2_subdev_format format = { 525 .pad = MSM_CSIPHY_PAD_SINK, 526 .which = fh ? V4L2_SUBDEV_FORMAT_TRY : 527 V4L2_SUBDEV_FORMAT_ACTIVE, 528 .format = { 529 .code = MEDIA_BUS_FMT_UYVY8_1X16, 530 .width = 1920, 531 .height = 1080 532 } 533 }; 534 535 return csiphy_set_format(sd, fh ? fh->state : NULL, &format); 536} 537 538static bool csiphy_match_clock_name(const char *clock_name, const char *format, 539 int index) 540{ 541 char name[16]; /* csiphyXXX_timer\0 */ 542 543 snprintf(name, sizeof(name), format, index); 544 return !strcmp(clock_name, name); 545} 546 547/* 548 * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources 549 * @csiphy: CSIPHY device 550 * @res: CSIPHY module resources table 551 * @id: CSIPHY module id 552 * 553 * Return 0 on success or a negative error code otherwise 554 */ 555int msm_csiphy_subdev_init(struct camss *camss, 556 struct csiphy_device *csiphy, 557 const struct camss_subdev_resources *res, u8 id) 558{ 559 struct device *dev = camss->dev; 560 struct platform_device *pdev = to_platform_device(dev); 561 int i, j, k; 562 int ret; 563 564 csiphy->camss = camss; 565 csiphy->id = id; 566 csiphy->cfg.combo_mode = 0; 567 csiphy->ops = res->ops; 568 569 switch (camss->res->version) { 570 case CAMSS_8x16: 571 csiphy->formats = csiphy_formats_8x16; 572 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x16); 573 break; 574 case CAMSS_8x96: 575 case CAMSS_660: 576 csiphy->formats = csiphy_formats_8x96; 577 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96); 578 break; 579 case CAMSS_845: 580 case CAMSS_8250: 581 csiphy->formats = csiphy_formats_sdm845; 582 csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845); 583 break; 584 } 585 586 /* Memory */ 587 588 csiphy->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]); 589 if (IS_ERR(csiphy->base)) 590 return PTR_ERR(csiphy->base); 591 592 if (camss->res->version == CAMSS_8x16 || 593 camss->res->version == CAMSS_8x96) { 594 csiphy->base_clk_mux = 595 devm_platform_ioremap_resource_byname(pdev, res->reg[1]); 596 if (IS_ERR(csiphy->base_clk_mux)) 597 return PTR_ERR(csiphy->base_clk_mux); 598 } else { 599 csiphy->base_clk_mux = NULL; 600 } 601 602 /* Interrupt */ 603 604 ret = platform_get_irq_byname(pdev, res->interrupt[0]); 605 if (ret < 0) 606 return ret; 607 608 csiphy->irq = ret; 609 snprintf(csiphy->irq_name, sizeof(csiphy->irq_name), "%s_%s%d", 610 dev_name(dev), MSM_CSIPHY_NAME, csiphy->id); 611 612 ret = devm_request_irq(dev, csiphy->irq, csiphy->ops->isr, 613 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, 614 csiphy->irq_name, csiphy); 615 if (ret < 0) { 616 dev_err(dev, "request_irq failed: %d\n", ret); 617 return ret; 618 } 619 620 /* Clocks */ 621 622 csiphy->nclocks = 0; 623 while (res->clock[csiphy->nclocks]) 624 csiphy->nclocks++; 625 626 csiphy->clock = devm_kcalloc(dev, 627 csiphy->nclocks, sizeof(*csiphy->clock), 628 GFP_KERNEL); 629 if (!csiphy->clock) 630 return -ENOMEM; 631 632 csiphy->rate_set = devm_kcalloc(dev, 633 csiphy->nclocks, 634 sizeof(*csiphy->rate_set), 635 GFP_KERNEL); 636 if (!csiphy->rate_set) 637 return -ENOMEM; 638 639 for (i = 0; i < csiphy->nclocks; i++) { 640 struct camss_clock *clock = &csiphy->clock[i]; 641 642 clock->clk = devm_clk_get(dev, res->clock[i]); 643 if (IS_ERR(clock->clk)) 644 return PTR_ERR(clock->clk); 645 646 clock->name = res->clock[i]; 647 648 clock->nfreqs = 0; 649 while (res->clock_rate[i][clock->nfreqs]) 650 clock->nfreqs++; 651 652 if (!clock->nfreqs) { 653 clock->freq = NULL; 654 continue; 655 } 656 657 clock->freq = devm_kcalloc(dev, 658 clock->nfreqs, 659 sizeof(*clock->freq), 660 GFP_KERNEL); 661 if (!clock->freq) 662 return -ENOMEM; 663 664 for (j = 0; j < clock->nfreqs; j++) 665 clock->freq[j] = res->clock_rate[i][j]; 666 667 for (k = 0; k < camss->res->csiphy_num; k++) { 668 csiphy->rate_set[i] = csiphy_match_clock_name(clock->name, 669 "csiphy%d_timer", k); 670 if (csiphy->rate_set[i]) 671 break; 672 673 if (camss->res->version == CAMSS_660) { 674 csiphy->rate_set[i] = csiphy_match_clock_name(clock->name, 675 "csi%d_phy", k); 676 if (csiphy->rate_set[i]) 677 break; 678 } 679 680 csiphy->rate_set[i] = csiphy_match_clock_name(clock->name, "csiphy%d", k); 681 if (csiphy->rate_set[i]) 682 break; 683 } 684 } 685 686 return 0; 687} 688 689/* 690 * csiphy_link_setup - Setup CSIPHY connections 691 * @entity: Pointer to media entity structure 692 * @local: Pointer to local pad 693 * @remote: Pointer to remote pad 694 * @flags: Link flags 695 * 696 * Rreturn 0 on success 697 */ 698static int csiphy_link_setup(struct media_entity *entity, 699 const struct media_pad *local, 700 const struct media_pad *remote, u32 flags) 701{ 702 if ((local->flags & MEDIA_PAD_FL_SOURCE) && 703 (flags & MEDIA_LNK_FL_ENABLED)) { 704 struct v4l2_subdev *sd; 705 struct csiphy_device *csiphy; 706 struct csid_device *csid; 707 708 if (media_pad_remote_pad_first(local)) 709 return -EBUSY; 710 711 sd = media_entity_to_v4l2_subdev(entity); 712 csiphy = v4l2_get_subdevdata(sd); 713 714 sd = media_entity_to_v4l2_subdev(remote->entity); 715 csid = v4l2_get_subdevdata(sd); 716 717 csiphy->cfg.csid_id = csid->id; 718 } 719 720 return 0; 721} 722 723static const struct v4l2_subdev_core_ops csiphy_core_ops = { 724 .s_power = csiphy_set_power, 725}; 726 727static const struct v4l2_subdev_video_ops csiphy_video_ops = { 728 .s_stream = csiphy_set_stream, 729}; 730 731static const struct v4l2_subdev_pad_ops csiphy_pad_ops = { 732 .enum_mbus_code = csiphy_enum_mbus_code, 733 .enum_frame_size = csiphy_enum_frame_size, 734 .get_fmt = csiphy_get_format, 735 .set_fmt = csiphy_set_format, 736}; 737 738static const struct v4l2_subdev_ops csiphy_v4l2_ops = { 739 .core = &csiphy_core_ops, 740 .video = &csiphy_video_ops, 741 .pad = &csiphy_pad_ops, 742}; 743 744static const struct v4l2_subdev_internal_ops csiphy_v4l2_internal_ops = { 745 .open = csiphy_init_formats, 746}; 747 748static const struct media_entity_operations csiphy_media_ops = { 749 .link_setup = csiphy_link_setup, 750 .link_validate = v4l2_subdev_link_validate, 751}; 752 753/* 754 * msm_csiphy_register_entity - Register subdev node for CSIPHY module 755 * @csiphy: CSIPHY device 756 * @v4l2_dev: V4L2 device 757 * 758 * Return 0 on success or a negative error code otherwise 759 */ 760int msm_csiphy_register_entity(struct csiphy_device *csiphy, 761 struct v4l2_device *v4l2_dev) 762{ 763 struct v4l2_subdev *sd = &csiphy->subdev; 764 struct media_pad *pads = csiphy->pads; 765 struct device *dev = csiphy->camss->dev; 766 int ret; 767 768 v4l2_subdev_init(sd, &csiphy_v4l2_ops); 769 sd->internal_ops = &csiphy_v4l2_internal_ops; 770 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 771 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", 772 MSM_CSIPHY_NAME, csiphy->id); 773 v4l2_set_subdevdata(sd, csiphy); 774 775 ret = csiphy_init_formats(sd, NULL); 776 if (ret < 0) { 777 dev_err(dev, "Failed to init format: %d\n", ret); 778 return ret; 779 } 780 781 pads[MSM_CSIPHY_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 782 pads[MSM_CSIPHY_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 783 784 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 785 sd->entity.ops = &csiphy_media_ops; 786 ret = media_entity_pads_init(&sd->entity, MSM_CSIPHY_PADS_NUM, pads); 787 if (ret < 0) { 788 dev_err(dev, "Failed to init media entity: %d\n", ret); 789 return ret; 790 } 791 792 ret = v4l2_device_register_subdev(v4l2_dev, sd); 793 if (ret < 0) { 794 dev_err(dev, "Failed to register subdev: %d\n", ret); 795 media_entity_cleanup(&sd->entity); 796 } 797 798 return ret; 799} 800 801/* 802 * msm_csiphy_unregister_entity - Unregister CSIPHY module subdev node 803 * @csiphy: CSIPHY device 804 */ 805void msm_csiphy_unregister_entity(struct csiphy_device *csiphy) 806{ 807 v4l2_device_unregister_subdev(&csiphy->subdev); 808 media_entity_cleanup(&csiphy->subdev.entity); 809} 810