1// SPDX-License-Identifier: GPL-2.0 2/* 3 * camss.c 4 * 5 * Qualcomm MSM Camera Subsystem - Core 6 * 7 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10#include <linux/clk.h> 11#include <linux/interconnect.h> 12#include <linux/media-bus-format.h> 13#include <linux/media.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/of.h> 17#include <linux/of_device.h> 18#include <linux/of_graph.h> 19#include <linux/pm_runtime.h> 20#include <linux/pm_domain.h> 21#include <linux/slab.h> 22#include <linux/videodev2.h> 23 24#include <media/media-device.h> 25#include <media/v4l2-async.h> 26#include <media/v4l2-device.h> 27#include <media/v4l2-mc.h> 28#include <media/v4l2-fwnode.h> 29 30#include "camss.h" 31 32#define CAMSS_CLOCK_MARGIN_NUMERATOR 105 33#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 34 35static const struct camss_subdev_resources csiphy_res_8x16[] = { 36 /* CSIPHY0 */ 37 { 38 .regulators = {}, 39 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 40 .clock_rate = { { 0 }, 41 { 0 }, 42 { 0 }, 43 { 100000000, 200000000 } }, 44 .reg = { "csiphy0", "csiphy0_clk_mux" }, 45 .interrupt = { "csiphy0" }, 46 .ops = &csiphy_ops_2ph_1_0 47 }, 48 49 /* CSIPHY1 */ 50 { 51 .regulators = {}, 52 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 53 .clock_rate = { { 0 }, 54 { 0 }, 55 { 0 }, 56 { 100000000, 200000000 } }, 57 .reg = { "csiphy1", "csiphy1_clk_mux" }, 58 .interrupt = { "csiphy1" }, 59 .ops = &csiphy_ops_2ph_1_0 60 } 61}; 62 63static const struct camss_subdev_resources csid_res_8x16[] = { 64 /* CSID0 */ 65 { 66 .regulators = { "vdda" }, 67 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 68 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 69 .clock_rate = { { 0 }, 70 { 0 }, 71 { 0 }, 72 { 0 }, 73 { 100000000, 200000000 }, 74 { 0 }, 75 { 0 }, 76 { 0 } }, 77 .reg = { "csid0" }, 78 .interrupt = { "csid0" }, 79 .ops = &csid_ops_4_1, 80 }, 81 82 /* CSID1 */ 83 { 84 .regulators = { "vdda" }, 85 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 86 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 87 .clock_rate = { { 0 }, 88 { 0 }, 89 { 0 }, 90 { 0 }, 91 { 100000000, 200000000 }, 92 { 0 }, 93 { 0 }, 94 { 0 } }, 95 .reg = { "csid1" }, 96 .interrupt = { "csid1" }, 97 .ops = &csid_ops_4_1, 98 }, 99}; 100 101static const struct camss_subdev_resources ispif_res_8x16 = { 102 /* ISPIF */ 103 .clock = { "top_ahb", "ahb", "ispif_ahb", 104 "csi0", "csi0_pix", "csi0_rdi", 105 "csi1", "csi1_pix", "csi1_rdi" }, 106 .clock_for_reset = { "vfe0", "csi_vfe0" }, 107 .reg = { "ispif", "csi_clk_mux" }, 108 .interrupt = { "ispif" } 109 110}; 111 112static const struct camss_subdev_resources vfe_res_8x16[] = { 113 /* VFE0 */ 114 { 115 .regulators = {}, 116 .clock = { "top_ahb", "vfe0", "csi_vfe0", 117 "vfe_ahb", "vfe_axi", "ahb" }, 118 .clock_rate = { { 0 }, 119 { 50000000, 80000000, 100000000, 160000000, 120 177780000, 200000000, 266670000, 320000000, 121 400000000, 465000000 }, 122 { 0 }, 123 { 0 }, 124 { 0 }, 125 { 0 }, 126 { 0 }, 127 { 0 }, 128 { 0 } }, 129 .reg = { "vfe0" }, 130 .interrupt = { "vfe0" }, 131 .line_num = 3, 132 .ops = &vfe_ops_4_1 133 } 134}; 135 136static const struct camss_subdev_resources csiphy_res_8x96[] = { 137 /* CSIPHY0 */ 138 { 139 .regulators = {}, 140 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 141 .clock_rate = { { 0 }, 142 { 0 }, 143 { 0 }, 144 { 100000000, 200000000, 266666667 } }, 145 .reg = { "csiphy0", "csiphy0_clk_mux" }, 146 .interrupt = { "csiphy0" }, 147 .ops = &csiphy_ops_3ph_1_0 148 }, 149 150 /* CSIPHY1 */ 151 { 152 .regulators = {}, 153 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 154 .clock_rate = { { 0 }, 155 { 0 }, 156 { 0 }, 157 { 100000000, 200000000, 266666667 } }, 158 .reg = { "csiphy1", "csiphy1_clk_mux" }, 159 .interrupt = { "csiphy1" }, 160 .ops = &csiphy_ops_3ph_1_0 161 }, 162 163 /* CSIPHY2 */ 164 { 165 .regulators = {}, 166 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" }, 167 .clock_rate = { { 0 }, 168 { 0 }, 169 { 0 }, 170 { 100000000, 200000000, 266666667 } }, 171 .reg = { "csiphy2", "csiphy2_clk_mux" }, 172 .interrupt = { "csiphy2" }, 173 .ops = &csiphy_ops_3ph_1_0 174 } 175}; 176 177static const struct camss_subdev_resources csid_res_8x96[] = { 178 /* CSID0 */ 179 { 180 .regulators = { "vdda" }, 181 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 182 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 183 .clock_rate = { { 0 }, 184 { 0 }, 185 { 0 }, 186 { 0 }, 187 { 100000000, 200000000, 266666667 }, 188 { 0 }, 189 { 0 }, 190 { 0 } }, 191 .reg = { "csid0" }, 192 .interrupt = { "csid0" }, 193 .ops = &csid_ops_4_7, 194 }, 195 196 /* CSID1 */ 197 { 198 .regulators = { "vdda" }, 199 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 200 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 201 .clock_rate = { { 0 }, 202 { 0 }, 203 { 0 }, 204 { 0 }, 205 { 100000000, 200000000, 266666667 }, 206 { 0 }, 207 { 0 }, 208 { 0 } }, 209 .reg = { "csid1" }, 210 .interrupt = { "csid1" }, 211 .ops = &csid_ops_4_7, 212 }, 213 214 /* CSID2 */ 215 { 216 .regulators = { "vdda" }, 217 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 218 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, 219 .clock_rate = { { 0 }, 220 { 0 }, 221 { 0 }, 222 { 0 }, 223 { 100000000, 200000000, 266666667 }, 224 { 0 }, 225 { 0 }, 226 { 0 } }, 227 .reg = { "csid2" }, 228 .interrupt = { "csid2" }, 229 .ops = &csid_ops_4_7, 230 }, 231 232 /* CSID3 */ 233 { 234 .regulators = { "vdda" }, 235 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 236 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" }, 237 .clock_rate = { { 0 }, 238 { 0 }, 239 { 0 }, 240 { 0 }, 241 { 100000000, 200000000, 266666667 }, 242 { 0 }, 243 { 0 }, 244 { 0 } }, 245 .reg = { "csid3" }, 246 .interrupt = { "csid3" }, 247 .ops = &csid_ops_4_7, 248 } 249}; 250 251static const struct camss_subdev_resources ispif_res_8x96 = { 252 /* ISPIF */ 253 .clock = { "top_ahb", "ahb", "ispif_ahb", 254 "csi0", "csi0_pix", "csi0_rdi", 255 "csi1", "csi1_pix", "csi1_rdi", 256 "csi2", "csi2_pix", "csi2_rdi", 257 "csi3", "csi3_pix", "csi3_rdi" }, 258 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" }, 259 .reg = { "ispif", "csi_clk_mux" }, 260 .interrupt = { "ispif" } 261}; 262 263static const struct camss_subdev_resources vfe_res_8x96[] = { 264 /* VFE0 */ 265 { 266 .regulators = {}, 267 .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb", 268 "vfe0_ahb", "vfe_axi", "vfe0_stream"}, 269 .clock_rate = { { 0 }, 270 { 0 }, 271 { 75000000, 100000000, 300000000, 272 320000000, 480000000, 600000000 }, 273 { 0 }, 274 { 0 }, 275 { 0 }, 276 { 0 }, 277 { 0 } }, 278 .reg = { "vfe0" }, 279 .interrupt = { "vfe0" }, 280 .line_num = 3, 281 .has_pd = true, 282 .ops = &vfe_ops_4_7 283 }, 284 285 /* VFE1 */ 286 { 287 .regulators = {}, 288 .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb", 289 "vfe1_ahb", "vfe_axi", "vfe1_stream"}, 290 .clock_rate = { { 0 }, 291 { 0 }, 292 { 75000000, 100000000, 300000000, 293 320000000, 480000000, 600000000 }, 294 { 0 }, 295 { 0 }, 296 { 0 }, 297 { 0 }, 298 { 0 } }, 299 .reg = { "vfe1" }, 300 .interrupt = { "vfe1" }, 301 .line_num = 3, 302 .has_pd = true, 303 .ops = &vfe_ops_4_7 304 } 305}; 306 307static const struct camss_subdev_resources csiphy_res_660[] = { 308 /* CSIPHY0 */ 309 { 310 .regulators = {}, 311 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer", 312 "csi0_phy", "csiphy_ahb2crif" }, 313 .clock_rate = { { 0 }, 314 { 0 }, 315 { 0 }, 316 { 100000000, 200000000, 269333333 }, 317 { 0 } }, 318 .reg = { "csiphy0", "csiphy0_clk_mux" }, 319 .interrupt = { "csiphy0" }, 320 .ops = &csiphy_ops_3ph_1_0 321 }, 322 323 /* CSIPHY1 */ 324 { 325 .regulators = {}, 326 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer", 327 "csi1_phy", "csiphy_ahb2crif" }, 328 .clock_rate = { { 0 }, 329 { 0 }, 330 { 0 }, 331 { 100000000, 200000000, 269333333 }, 332 { 0 } }, 333 .reg = { "csiphy1", "csiphy1_clk_mux" }, 334 .interrupt = { "csiphy1" }, 335 .ops = &csiphy_ops_3ph_1_0 336 }, 337 338 /* CSIPHY2 */ 339 { 340 .regulators = {}, 341 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer", 342 "csi2_phy", "csiphy_ahb2crif" }, 343 .clock_rate = { { 0 }, 344 { 0 }, 345 { 0 }, 346 { 100000000, 200000000, 269333333 }, 347 { 0 } }, 348 .reg = { "csiphy2", "csiphy2_clk_mux" }, 349 .interrupt = { "csiphy2" }, 350 .ops = &csiphy_ops_3ph_1_0 351 } 352}; 353 354static const struct camss_subdev_resources csid_res_660[] = { 355 /* CSID0 */ 356 { 357 .regulators = { "vdda", "vdd_sec" }, 358 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 359 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", 360 "cphy_csid0" }, 361 .clock_rate = { { 0 }, 362 { 0 }, 363 { 0 }, 364 { 0 }, 365 { 100000000, 200000000, 310000000, 366 404000000, 465000000 }, 367 { 0 }, 368 { 0 }, 369 { 0 }, 370 { 0 } }, 371 .reg = { "csid0" }, 372 .interrupt = { "csid0" }, 373 .ops = &csid_ops_4_7, 374 }, 375 376 /* CSID1 */ 377 { 378 .regulators = { "vdda", "vdd_sec" }, 379 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 380 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", 381 "cphy_csid1" }, 382 .clock_rate = { { 0 }, 383 { 0 }, 384 { 0 }, 385 { 0 }, 386 { 100000000, 200000000, 310000000, 387 404000000, 465000000 }, 388 { 0 }, 389 { 0 }, 390 { 0 }, 391 { 0 } }, 392 .reg = { "csid1" }, 393 .interrupt = { "csid1" }, 394 .ops = &csid_ops_4_7, 395 }, 396 397 /* CSID2 */ 398 { 399 .regulators = { "vdda", "vdd_sec" }, 400 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 401 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", 402 "cphy_csid2" }, 403 .clock_rate = { { 0 }, 404 { 0 }, 405 { 0 }, 406 { 0 }, 407 { 100000000, 200000000, 310000000, 408 404000000, 465000000 }, 409 { 0 }, 410 { 0 }, 411 { 0 }, 412 { 0 } }, 413 .reg = { "csid2" }, 414 .interrupt = { "csid2" }, 415 .ops = &csid_ops_4_7, 416 }, 417 418 /* CSID3 */ 419 { 420 .regulators = { "vdda", "vdd_sec" }, 421 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 422 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", 423 "cphy_csid3" }, 424 .clock_rate = { { 0 }, 425 { 0 }, 426 { 0 }, 427 { 0 }, 428 { 100000000, 200000000, 310000000, 429 404000000, 465000000 }, 430 { 0 }, 431 { 0 }, 432 { 0 }, 433 { 0 } }, 434 .reg = { "csid3" }, 435 .interrupt = { "csid3" }, 436 .ops = &csid_ops_4_7, 437 } 438}; 439 440static const struct camss_subdev_resources ispif_res_660 = { 441 /* ISPIF */ 442 .clock = { "top_ahb", "ahb", "ispif_ahb", 443 "csi0", "csi0_pix", "csi0_rdi", 444 "csi1", "csi1_pix", "csi1_rdi", 445 "csi2", "csi2_pix", "csi2_rdi", 446 "csi3", "csi3_pix", "csi3_rdi" }, 447 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" }, 448 .reg = { "ispif", "csi_clk_mux" }, 449 .interrupt = { "ispif" } 450}; 451 452static const struct camss_subdev_resources vfe_res_660[] = { 453 /* VFE0 */ 454 { 455 .regulators = {}, 456 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0", 457 "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi", 458 "vfe0_stream"}, 459 .clock_rate = { { 0 }, 460 { 0 }, 461 { 0 }, 462 { 120000000, 200000000, 256000000, 463 300000000, 404000000, 480000000, 464 540000000, 576000000 }, 465 { 0 }, 466 { 0 }, 467 { 0 }, 468 { 0 }, 469 { 0 } }, 470 .reg = { "vfe0" }, 471 .interrupt = { "vfe0" }, 472 .line_num = 3, 473 .has_pd = true, 474 .ops = &vfe_ops_4_8 475 }, 476 477 /* VFE1 */ 478 { 479 .regulators = {}, 480 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1", 481 "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi", 482 "vfe1_stream"}, 483 .clock_rate = { { 0 }, 484 { 0 }, 485 { 0 }, 486 { 120000000, 200000000, 256000000, 487 300000000, 404000000, 480000000, 488 540000000, 576000000 }, 489 { 0 }, 490 { 0 }, 491 { 0 }, 492 { 0 }, 493 { 0 } }, 494 .reg = { "vfe1" }, 495 .interrupt = { "vfe1" }, 496 .line_num = 3, 497 .has_pd = true, 498 .ops = &vfe_ops_4_8 499 } 500}; 501 502static const struct camss_subdev_resources csiphy_res_845[] = { 503 /* CSIPHY0 */ 504 { 505 .regulators = {}, 506 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 507 "cpas_ahb", "cphy_rx_src", "csiphy0", 508 "csiphy0_timer_src", "csiphy0_timer" }, 509 .clock_rate = { { 0 }, 510 { 0 }, 511 { 0 }, 512 { 0 }, 513 { 0 }, 514 { 0 }, 515 { 0 }, 516 { 19200000, 240000000, 269333333 } }, 517 .reg = { "csiphy0" }, 518 .interrupt = { "csiphy0" }, 519 .ops = &csiphy_ops_3ph_1_0 520 }, 521 522 /* CSIPHY1 */ 523 { 524 .regulators = {}, 525 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 526 "cpas_ahb", "cphy_rx_src", "csiphy1", 527 "csiphy1_timer_src", "csiphy1_timer" }, 528 .clock_rate = { { 0 }, 529 { 0 }, 530 { 0 }, 531 { 0 }, 532 { 0 }, 533 { 0 }, 534 { 0 }, 535 { 19200000, 240000000, 269333333 } }, 536 .reg = { "csiphy1" }, 537 .interrupt = { "csiphy1" }, 538 .ops = &csiphy_ops_3ph_1_0 539 }, 540 541 /* CSIPHY2 */ 542 { 543 .regulators = {}, 544 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 545 "cpas_ahb", "cphy_rx_src", "csiphy2", 546 "csiphy2_timer_src", "csiphy2_timer" }, 547 .clock_rate = { { 0 }, 548 { 0 }, 549 { 0 }, 550 { 0 }, 551 { 0 }, 552 { 0 }, 553 { 0 }, 554 { 19200000, 240000000, 269333333 } }, 555 .reg = { "csiphy2" }, 556 .interrupt = { "csiphy2" }, 557 .ops = &csiphy_ops_3ph_1_0 558 }, 559 560 /* CSIPHY3 */ 561 { 562 .regulators = {}, 563 .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", 564 "cpas_ahb", "cphy_rx_src", "csiphy3", 565 "csiphy3_timer_src", "csiphy3_timer" }, 566 .clock_rate = { { 0 }, 567 { 0 }, 568 { 0 }, 569 { 0 }, 570 { 0 }, 571 { 0 }, 572 { 0 }, 573 { 19200000, 240000000, 269333333 } }, 574 .reg = { "csiphy3" }, 575 .interrupt = { "csiphy3" }, 576 .ops = &csiphy_ops_3ph_1_0 577 } 578}; 579 580static const struct camss_subdev_resources csid_res_845[] = { 581 /* CSID0 */ 582 { 583 .regulators = { "vdda-phy", "vdda-pll" }, 584 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 585 "soc_ahb", "vfe0", "vfe0_src", 586 "vfe0_cphy_rx", "csi0", 587 "csi0_src" }, 588 .clock_rate = { { 0 }, 589 { 384000000 }, 590 { 80000000 }, 591 { 0 }, 592 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 593 { 320000000 }, 594 { 0 }, 595 { 19200000, 75000000, 384000000, 538666667 }, 596 { 384000000 } }, 597 .reg = { "csid0" }, 598 .interrupt = { "csid0" }, 599 .ops = &csid_ops_gen2 600 }, 601 602 /* CSID1 */ 603 { 604 .regulators = { "vdda-phy", "vdda-pll" }, 605 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 606 "soc_ahb", "vfe1", "vfe1_src", 607 "vfe1_cphy_rx", "csi1", 608 "csi1_src" }, 609 .clock_rate = { { 0 }, 610 { 384000000 }, 611 { 80000000 }, 612 { 0 }, 613 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 614 { 320000000 }, 615 { 0 }, 616 { 19200000, 75000000, 384000000, 538666667 }, 617 { 384000000 } }, 618 .reg = { "csid1" }, 619 .interrupt = { "csid1" }, 620 .ops = &csid_ops_gen2 621 }, 622 623 /* CSID2 */ 624 { 625 .regulators = { "vdda-phy", "vdda-pll" }, 626 .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", 627 "soc_ahb", "vfe_lite", "vfe_lite_src", 628 "vfe_lite_cphy_rx", "csi2", 629 "csi2_src" }, 630 .clock_rate = { { 0 }, 631 { 384000000 }, 632 { 80000000 }, 633 { 0 }, 634 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 635 { 320000000 }, 636 { 0 }, 637 { 19200000, 75000000, 384000000, 538666667 }, 638 { 384000000 } }, 639 .reg = { "csid2" }, 640 .interrupt = { "csid2" }, 641 .is_lite = true, 642 .ops = &csid_ops_gen2 643 } 644}; 645 646static const struct camss_subdev_resources vfe_res_845[] = { 647 /* VFE0 */ 648 { 649 .regulators = {}, 650 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", 651 "soc_ahb", "vfe0", "vfe0_axi", 652 "vfe0_src", "csi0", 653 "csi0_src"}, 654 .clock_rate = { { 0 }, 655 { 0 }, 656 { 80000000 }, 657 { 0 }, 658 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 659 { 0 }, 660 { 320000000 }, 661 { 19200000, 75000000, 384000000, 538666667 }, 662 { 384000000 } }, 663 .reg = { "vfe0" }, 664 .interrupt = { "vfe0" }, 665 .line_num = 4, 666 .has_pd = true, 667 .ops = &vfe_ops_170 668 }, 669 670 /* VFE1 */ 671 { 672 .regulators = {}, 673 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", 674 "soc_ahb", "vfe1", "vfe1_axi", 675 "vfe1_src", "csi1", 676 "csi1_src"}, 677 .clock_rate = { { 0 }, 678 { 0 }, 679 { 80000000 }, 680 { 0 }, 681 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 682 { 0 }, 683 { 320000000 }, 684 { 19200000, 75000000, 384000000, 538666667 }, 685 { 384000000 } }, 686 .reg = { "vfe1" }, 687 .interrupt = { "vfe1" }, 688 .line_num = 4, 689 .has_pd = true, 690 .ops = &vfe_ops_170 691 }, 692 693 /* VFE-lite */ 694 { 695 .regulators = {}, 696 .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", 697 "soc_ahb", "vfe_lite", 698 "vfe_lite_src", "csi2", 699 "csi2_src"}, 700 .clock_rate = { { 0 }, 701 { 0 }, 702 { 80000000 }, 703 { 0 }, 704 { 19200000, 100000000, 320000000, 404000000, 480000000, 600000000 }, 705 { 320000000 }, 706 { 19200000, 75000000, 384000000, 538666667 }, 707 { 384000000 } }, 708 .reg = { "vfe_lite" }, 709 .interrupt = { "vfe_lite" }, 710 .is_lite = true, 711 .line_num = 4, 712 .ops = &vfe_ops_170 713 } 714}; 715 716static const struct camss_subdev_resources csiphy_res_8250[] = { 717 /* CSIPHY0 */ 718 { 719 .regulators = {}, 720 .clock = { "csiphy0", "csiphy0_timer" }, 721 .clock_rate = { { 400000000 }, 722 { 300000000 } }, 723 .reg = { "csiphy0" }, 724 .interrupt = { "csiphy0" }, 725 .ops = &csiphy_ops_3ph_1_0 726 }, 727 /* CSIPHY1 */ 728 { 729 .regulators = {}, 730 .clock = { "csiphy1", "csiphy1_timer" }, 731 .clock_rate = { { 400000000 }, 732 { 300000000 } }, 733 .reg = { "csiphy1" }, 734 .interrupt = { "csiphy1" }, 735 .ops = &csiphy_ops_3ph_1_0 736 }, 737 /* CSIPHY2 */ 738 { 739 .regulators = {}, 740 .clock = { "csiphy2", "csiphy2_timer" }, 741 .clock_rate = { { 400000000 }, 742 { 300000000 } }, 743 .reg = { "csiphy2" }, 744 .interrupt = { "csiphy2" }, 745 .ops = &csiphy_ops_3ph_1_0 746 }, 747 /* CSIPHY3 */ 748 { 749 .regulators = {}, 750 .clock = { "csiphy3", "csiphy3_timer" }, 751 .clock_rate = { { 400000000 }, 752 { 300000000 } }, 753 .reg = { "csiphy3" }, 754 .interrupt = { "csiphy3" }, 755 .ops = &csiphy_ops_3ph_1_0 756 }, 757 /* CSIPHY4 */ 758 { 759 .regulators = {}, 760 .clock = { "csiphy4", "csiphy4_timer" }, 761 .clock_rate = { { 400000000 }, 762 { 300000000 } }, 763 .reg = { "csiphy4" }, 764 .interrupt = { "csiphy4" }, 765 .ops = &csiphy_ops_3ph_1_0 766 }, 767 /* CSIPHY5 */ 768 { 769 .regulators = {}, 770 .clock = { "csiphy5", "csiphy5_timer" }, 771 .clock_rate = { { 400000000 }, 772 { 300000000 } }, 773 .reg = { "csiphy5" }, 774 .interrupt = { "csiphy5" }, 775 .ops = &csiphy_ops_3ph_1_0 776 } 777}; 778 779static const struct camss_subdev_resources csid_res_8250[] = { 780 /* CSID0 */ 781 { 782 .regulators = { "vdda-phy", "vdda-pll" }, 783 .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, 784 .clock_rate = { { 400000000 }, 785 { 400000000 }, 786 { 350000000, 475000000, 576000000, 720000000 }, 787 { 100000000, 200000000, 300000000, 400000000 }, 788 { 0 } }, 789 .reg = { "csid0" }, 790 .interrupt = { "csid0" }, 791 .ops = &csid_ops_gen2 792 }, 793 /* CSID1 */ 794 { 795 .regulators = { "vdda-phy", "vdda-pll" }, 796 .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, 797 .clock_rate = { { 400000000 }, 798 { 400000000 }, 799 { 350000000, 475000000, 576000000, 720000000 }, 800 { 100000000, 200000000, 300000000, 400000000 }, 801 { 0 } }, 802 .reg = { "csid1" }, 803 .interrupt = { "csid1" }, 804 .ops = &csid_ops_gen2 805 }, 806 /* CSID2 */ 807 { 808 .regulators = { "vdda-phy", "vdda-pll" }, 809 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, 810 .clock_rate = { { 400000000 }, 811 { 400000000 }, 812 { 400000000, 480000000 }, 813 { 0 } }, 814 .reg = { "csid2" }, 815 .interrupt = { "csid2" }, 816 .is_lite = true, 817 .ops = &csid_ops_gen2 818 }, 819 /* CSID3 */ 820 { 821 .regulators = { "vdda-phy", "vdda-pll" }, 822 .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, 823 .clock_rate = { { 400000000 }, 824 { 400000000 }, 825 { 400000000, 480000000 }, 826 { 0 } }, 827 .reg = { "csid3" }, 828 .interrupt = { "csid3" }, 829 .is_lite = true, 830 .ops = &csid_ops_gen2 831 } 832}; 833 834static const struct camss_subdev_resources vfe_res_8250[] = { 835 /* VFE0 */ 836 { 837 .regulators = {}, 838 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 839 "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0", 840 "vfe0_axi", "cam_hf_axi" }, 841 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 842 { 19200000, 80000000 }, 843 { 19200000 }, 844 { 0 }, 845 { 0 }, 846 { 100000000, 200000000, 300000000, 400000000 }, 847 { 350000000, 475000000, 576000000, 720000000 }, 848 { 0 }, 849 { 0 } }, 850 .reg = { "vfe0" }, 851 .interrupt = { "vfe0" }, 852 .pd_name = "ife0", 853 .line_num = 3, 854 .has_pd = true, 855 .ops = &vfe_ops_480 856 }, 857 /* VFE1 */ 858 { 859 .regulators = {}, 860 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 861 "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1", 862 "vfe1_axi", "cam_hf_axi" }, 863 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 864 { 19200000, 80000000 }, 865 { 19200000 }, 866 { 0 }, 867 { 0 }, 868 { 100000000, 200000000, 300000000, 400000000 }, 869 { 350000000, 475000000, 576000000, 720000000 }, 870 { 0 }, 871 { 0 } }, 872 .reg = { "vfe1" }, 873 .interrupt = { "vfe1" }, 874 .pd_name = "ife1", 875 .line_num = 3, 876 .has_pd = true, 877 .ops = &vfe_ops_480 878 }, 879 /* VFE2 (lite) */ 880 { 881 .regulators = {}, 882 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 883 "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", 884 "vfe_lite", "cam_hf_axi" }, 885 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 886 { 19200000, 80000000 }, 887 { 19200000 }, 888 { 0 }, 889 { 0 }, 890 { 0 }, 891 { 400000000, 480000000 }, 892 { 0 } }, 893 .reg = { "vfe_lite0" }, 894 .interrupt = { "vfe_lite0" }, 895 .is_lite = true, 896 .line_num = 4, 897 .ops = &vfe_ops_480 898 }, 899 /* VFE3 (lite) */ 900 { 901 .regulators = {}, 902 .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", 903 "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", 904 "vfe_lite", "cam_hf_axi" }, 905 .clock_rate = { { 19200000, 300000000, 400000000, 480000000 }, 906 { 19200000, 80000000 }, 907 { 19200000 }, 908 { 0 }, 909 { 0 }, 910 { 0 }, 911 { 400000000, 480000000 }, 912 { 0 } }, 913 .reg = { "vfe_lite1" }, 914 .interrupt = { "vfe_lite1" }, 915 .is_lite = true, 916 .line_num = 4, 917 .ops = &vfe_ops_480 918 }, 919}; 920 921static const struct resources_icc icc_res_sm8250[] = { 922 { 923 .name = "cam_ahb", 924 .icc_bw_tbl.avg = 38400, 925 .icc_bw_tbl.peak = 76800, 926 }, 927 { 928 .name = "cam_hf_0_mnoc", 929 .icc_bw_tbl.avg = 2097152, 930 .icc_bw_tbl.peak = 2097152, 931 }, 932 { 933 .name = "cam_sf_0_mnoc", 934 .icc_bw_tbl.avg = 0, 935 .icc_bw_tbl.peak = 2097152, 936 }, 937 { 938 .name = "cam_sf_icp_mnoc", 939 .icc_bw_tbl.avg = 2097152, 940 .icc_bw_tbl.peak = 2097152, 941 }, 942}; 943 944/* 945 * camss_add_clock_margin - Add margin to clock frequency rate 946 * @rate: Clock frequency rate 947 * 948 * When making calculations with physical clock frequency values 949 * some safety margin must be added. Add it. 950 */ 951inline void camss_add_clock_margin(u64 *rate) 952{ 953 *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR; 954 *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR); 955} 956 957/* 958 * camss_enable_clocks - Enable multiple clocks 959 * @nclocks: Number of clocks in clock array 960 * @clock: Clock array 961 * @dev: Device 962 * 963 * Return 0 on success or a negative error code otherwise 964 */ 965int camss_enable_clocks(int nclocks, struct camss_clock *clock, 966 struct device *dev) 967{ 968 int ret; 969 int i; 970 971 for (i = 0; i < nclocks; i++) { 972 ret = clk_prepare_enable(clock[i].clk); 973 if (ret) { 974 dev_err(dev, "clock enable failed: %d\n", ret); 975 goto error; 976 } 977 } 978 979 return 0; 980 981error: 982 for (i--; i >= 0; i--) 983 clk_disable_unprepare(clock[i].clk); 984 985 return ret; 986} 987 988/* 989 * camss_disable_clocks - Disable multiple clocks 990 * @nclocks: Number of clocks in clock array 991 * @clock: Clock array 992 */ 993void camss_disable_clocks(int nclocks, struct camss_clock *clock) 994{ 995 int i; 996 997 for (i = nclocks - 1; i >= 0; i--) 998 clk_disable_unprepare(clock[i].clk); 999} 1000 1001/* 1002 * camss_find_sensor - Find a linked media entity which represents a sensor 1003 * @entity: Media entity to start searching from 1004 * 1005 * Return a pointer to sensor media entity or NULL if not found 1006 */ 1007struct media_entity *camss_find_sensor(struct media_entity *entity) 1008{ 1009 struct media_pad *pad; 1010 1011 while (1) { 1012 pad = &entity->pads[0]; 1013 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 1014 return NULL; 1015 1016 pad = media_pad_remote_pad_first(pad); 1017 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 1018 return NULL; 1019 1020 entity = pad->entity; 1021 1022 if (entity->function == MEDIA_ENT_F_CAM_SENSOR) 1023 return entity; 1024 } 1025} 1026 1027/** 1028 * camss_get_link_freq - Get link frequency from sensor 1029 * @entity: Media entity in the current pipeline 1030 * @bpp: Number of bits per pixel for the current format 1031 * @lanes: Number of lanes in the link to the sensor 1032 * 1033 * Return link frequency on success or a negative error code otherwise 1034 */ 1035s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, 1036 unsigned int lanes) 1037{ 1038 struct media_entity *sensor; 1039 struct v4l2_subdev *subdev; 1040 1041 sensor = camss_find_sensor(entity); 1042 if (!sensor) 1043 return -ENODEV; 1044 1045 subdev = media_entity_to_v4l2_subdev(sensor); 1046 1047 return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes); 1048} 1049 1050/* 1051 * camss_get_pixel_clock - Get pixel clock rate from sensor 1052 * @entity: Media entity in the current pipeline 1053 * @pixel_clock: Received pixel clock value 1054 * 1055 * Return 0 on success or a negative error code otherwise 1056 */ 1057int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock) 1058{ 1059 struct media_entity *sensor; 1060 struct v4l2_subdev *subdev; 1061 struct v4l2_ctrl *ctrl; 1062 1063 sensor = camss_find_sensor(entity); 1064 if (!sensor) 1065 return -ENODEV; 1066 1067 subdev = media_entity_to_v4l2_subdev(sensor); 1068 1069 ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); 1070 1071 if (!ctrl) 1072 return -EINVAL; 1073 1074 *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl); 1075 1076 return 0; 1077} 1078 1079int camss_pm_domain_on(struct camss *camss, int id) 1080{ 1081 int ret = 0; 1082 1083 if (id < camss->res->vfe_num) { 1084 struct vfe_device *vfe = &camss->vfe[id]; 1085 1086 ret = vfe->ops->pm_domain_on(vfe); 1087 } 1088 1089 return ret; 1090} 1091 1092void camss_pm_domain_off(struct camss *camss, int id) 1093{ 1094 if (id < camss->res->vfe_num) { 1095 struct vfe_device *vfe = &camss->vfe[id]; 1096 1097 vfe->ops->pm_domain_off(vfe); 1098 } 1099} 1100 1101/* 1102 * camss_of_parse_endpoint_node - Parse port endpoint node 1103 * @dev: Device 1104 * @node: Device node to be parsed 1105 * @csd: Parsed data from port endpoint node 1106 * 1107 * Return 0 on success or a negative error code on failure 1108 */ 1109static int camss_of_parse_endpoint_node(struct device *dev, 1110 struct device_node *node, 1111 struct camss_async_subdev *csd) 1112{ 1113 struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg; 1114 struct v4l2_mbus_config_mipi_csi2 *mipi_csi2; 1115 struct v4l2_fwnode_endpoint vep = { { 0 } }; 1116 unsigned int i; 1117 1118 v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep); 1119 1120 csd->interface.csiphy_id = vep.base.port; 1121 1122 mipi_csi2 = &vep.bus.mipi_csi2; 1123 lncfg->clk.pos = mipi_csi2->clock_lane; 1124 lncfg->clk.pol = mipi_csi2->lane_polarities[0]; 1125 lncfg->num_data = mipi_csi2->num_data_lanes; 1126 1127 lncfg->data = devm_kcalloc(dev, 1128 lncfg->num_data, sizeof(*lncfg->data), 1129 GFP_KERNEL); 1130 if (!lncfg->data) 1131 return -ENOMEM; 1132 1133 for (i = 0; i < lncfg->num_data; i++) { 1134 lncfg->data[i].pos = mipi_csi2->data_lanes[i]; 1135 lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1]; 1136 } 1137 1138 return 0; 1139} 1140 1141/* 1142 * camss_of_parse_ports - Parse ports node 1143 * @dev: Device 1144 * @notifier: v4l2_device notifier data 1145 * 1146 * Return number of "port" nodes found in "ports" node 1147 */ 1148static int camss_of_parse_ports(struct camss *camss) 1149{ 1150 struct device *dev = camss->dev; 1151 struct device_node *node = NULL; 1152 struct device_node *remote = NULL; 1153 int ret, num_subdevs = 0; 1154 1155 for_each_endpoint_of_node(dev->of_node, node) { 1156 struct camss_async_subdev *csd; 1157 1158 if (!of_device_is_available(node)) 1159 continue; 1160 1161 remote = of_graph_get_remote_port_parent(node); 1162 if (!remote) { 1163 dev_err(dev, "Cannot get remote parent\n"); 1164 ret = -EINVAL; 1165 goto err_cleanup; 1166 } 1167 1168 csd = v4l2_async_nf_add_fwnode(&camss->notifier, 1169 of_fwnode_handle(remote), 1170 struct camss_async_subdev); 1171 of_node_put(remote); 1172 if (IS_ERR(csd)) { 1173 ret = PTR_ERR(csd); 1174 goto err_cleanup; 1175 } 1176 1177 ret = camss_of_parse_endpoint_node(dev, node, csd); 1178 if (ret < 0) 1179 goto err_cleanup; 1180 1181 num_subdevs++; 1182 } 1183 1184 return num_subdevs; 1185 1186err_cleanup: 1187 of_node_put(node); 1188 return ret; 1189} 1190 1191/* 1192 * camss_init_subdevices - Initialize subdev structures and resources 1193 * @camss: CAMSS device 1194 * 1195 * Return 0 on success or a negative error code on failure 1196 */ 1197static int camss_init_subdevices(struct camss *camss) 1198{ 1199 const struct camss_resources *res = camss->res; 1200 unsigned int i; 1201 int ret; 1202 1203 for (i = 0; i < camss->res->csiphy_num; i++) { 1204 ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], 1205 &res->csiphy_res[i], i); 1206 if (ret < 0) { 1207 dev_err(camss->dev, 1208 "Failed to init csiphy%d sub-device: %d\n", 1209 i, ret); 1210 return ret; 1211 } 1212 } 1213 1214 /* note: SM8250 requires VFE to be initialized before CSID */ 1215 for (i = 0; i < camss->res->vfe_num; i++) { 1216 ret = msm_vfe_subdev_init(camss, &camss->vfe[i], 1217 &res->vfe_res[i], i); 1218 if (ret < 0) { 1219 dev_err(camss->dev, 1220 "Fail to init vfe%d sub-device: %d\n", i, ret); 1221 return ret; 1222 } 1223 } 1224 1225 for (i = 0; i < camss->res->csid_num; i++) { 1226 ret = msm_csid_subdev_init(camss, &camss->csid[i], 1227 &res->csid_res[i], i); 1228 if (ret < 0) { 1229 dev_err(camss->dev, 1230 "Failed to init csid%d sub-device: %d\n", 1231 i, ret); 1232 return ret; 1233 } 1234 } 1235 1236 ret = msm_ispif_subdev_init(camss, res->ispif_res); 1237 if (ret < 0) { 1238 dev_err(camss->dev, "Failed to init ispif sub-device: %d\n", 1239 ret); 1240 return ret; 1241 } 1242 1243 return 0; 1244} 1245 1246/* 1247 * camss_register_entities - Register subdev nodes and create links 1248 * @camss: CAMSS device 1249 * 1250 * Return 0 on success or a negative error code on failure 1251 */ 1252static int camss_register_entities(struct camss *camss) 1253{ 1254 int i, j, k; 1255 int ret; 1256 1257 for (i = 0; i < camss->res->csiphy_num; i++) { 1258 ret = msm_csiphy_register_entity(&camss->csiphy[i], 1259 &camss->v4l2_dev); 1260 if (ret < 0) { 1261 dev_err(camss->dev, 1262 "Failed to register csiphy%d entity: %d\n", 1263 i, ret); 1264 goto err_reg_csiphy; 1265 } 1266 } 1267 1268 for (i = 0; i < camss->res->csid_num; i++) { 1269 ret = msm_csid_register_entity(&camss->csid[i], 1270 &camss->v4l2_dev); 1271 if (ret < 0) { 1272 dev_err(camss->dev, 1273 "Failed to register csid%d entity: %d\n", 1274 i, ret); 1275 goto err_reg_csid; 1276 } 1277 } 1278 1279 ret = msm_ispif_register_entities(camss->ispif, 1280 &camss->v4l2_dev); 1281 if (ret < 0) { 1282 dev_err(camss->dev, "Failed to register ispif entities: %d\n", 1283 ret); 1284 goto err_reg_ispif; 1285 } 1286 1287 for (i = 0; i < camss->res->vfe_num; i++) { 1288 ret = msm_vfe_register_entities(&camss->vfe[i], 1289 &camss->v4l2_dev); 1290 if (ret < 0) { 1291 dev_err(camss->dev, 1292 "Failed to register vfe%d entities: %d\n", 1293 i, ret); 1294 goto err_reg_vfe; 1295 } 1296 } 1297 1298 for (i = 0; i < camss->res->csiphy_num; i++) { 1299 for (j = 0; j < camss->res->csid_num; j++) { 1300 ret = media_create_pad_link( 1301 &camss->csiphy[i].subdev.entity, 1302 MSM_CSIPHY_PAD_SRC, 1303 &camss->csid[j].subdev.entity, 1304 MSM_CSID_PAD_SINK, 1305 0); 1306 if (ret < 0) { 1307 dev_err(camss->dev, 1308 "Failed to link %s->%s entities: %d\n", 1309 camss->csiphy[i].subdev.entity.name, 1310 camss->csid[j].subdev.entity.name, 1311 ret); 1312 goto err_link; 1313 } 1314 } 1315 } 1316 1317 if (camss->ispif) { 1318 for (i = 0; i < camss->res->csid_num; i++) { 1319 for (j = 0; j < camss->ispif->line_num; j++) { 1320 ret = media_create_pad_link( 1321 &camss->csid[i].subdev.entity, 1322 MSM_CSID_PAD_SRC, 1323 &camss->ispif->line[j].subdev.entity, 1324 MSM_ISPIF_PAD_SINK, 1325 0); 1326 if (ret < 0) { 1327 dev_err(camss->dev, 1328 "Failed to link %s->%s entities: %d\n", 1329 camss->csid[i].subdev.entity.name, 1330 camss->ispif->line[j].subdev.entity.name, 1331 ret); 1332 goto err_link; 1333 } 1334 } 1335 } 1336 1337 for (i = 0; i < camss->ispif->line_num; i++) 1338 for (k = 0; k < camss->res->vfe_num; k++) 1339 for (j = 0; j < camss->vfe[k].line_num; j++) { 1340 struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev; 1341 struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; 1342 1343 ret = media_create_pad_link(&ispif->entity, 1344 MSM_ISPIF_PAD_SRC, 1345 &vfe->entity, 1346 MSM_VFE_PAD_SINK, 1347 0); 1348 if (ret < 0) { 1349 dev_err(camss->dev, 1350 "Failed to link %s->%s entities: %d\n", 1351 ispif->entity.name, 1352 vfe->entity.name, 1353 ret); 1354 goto err_link; 1355 } 1356 } 1357 } else { 1358 for (i = 0; i < camss->res->csid_num; i++) 1359 for (k = 0; k < camss->res->vfe_num; k++) 1360 for (j = 0; j < camss->vfe[k].line_num; j++) { 1361 struct v4l2_subdev *csid = &camss->csid[i].subdev; 1362 struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; 1363 1364 ret = media_create_pad_link(&csid->entity, 1365 MSM_CSID_PAD_FIRST_SRC + j, 1366 &vfe->entity, 1367 MSM_VFE_PAD_SINK, 1368 0); 1369 if (ret < 0) { 1370 dev_err(camss->dev, 1371 "Failed to link %s->%s entities: %d\n", 1372 csid->entity.name, 1373 vfe->entity.name, 1374 ret); 1375 goto err_link; 1376 } 1377 } 1378 } 1379 1380 return 0; 1381 1382err_link: 1383 i = camss->res->vfe_num; 1384err_reg_vfe: 1385 for (i--; i >= 0; i--) 1386 msm_vfe_unregister_entities(&camss->vfe[i]); 1387 1388err_reg_ispif: 1389 msm_ispif_unregister_entities(camss->ispif); 1390 1391 i = camss->res->csid_num; 1392err_reg_csid: 1393 for (i--; i >= 0; i--) 1394 msm_csid_unregister_entity(&camss->csid[i]); 1395 1396 i = camss->res->csiphy_num; 1397err_reg_csiphy: 1398 for (i--; i >= 0; i--) 1399 msm_csiphy_unregister_entity(&camss->csiphy[i]); 1400 1401 return ret; 1402} 1403 1404/* 1405 * camss_unregister_entities - Unregister subdev nodes 1406 * @camss: CAMSS device 1407 * 1408 * Return 0 on success or a negative error code on failure 1409 */ 1410static void camss_unregister_entities(struct camss *camss) 1411{ 1412 unsigned int i; 1413 1414 for (i = 0; i < camss->res->csiphy_num; i++) 1415 msm_csiphy_unregister_entity(&camss->csiphy[i]); 1416 1417 for (i = 0; i < camss->res->csid_num; i++) 1418 msm_csid_unregister_entity(&camss->csid[i]); 1419 1420 msm_ispif_unregister_entities(camss->ispif); 1421 1422 for (i = 0; i < camss->res->vfe_num; i++) 1423 msm_vfe_unregister_entities(&camss->vfe[i]); 1424} 1425 1426static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async, 1427 struct v4l2_subdev *subdev, 1428 struct v4l2_async_connection *asd) 1429{ 1430 struct camss *camss = container_of(async, struct camss, notifier); 1431 struct camss_async_subdev *csd = 1432 container_of(asd, struct camss_async_subdev, asd); 1433 u8 id = csd->interface.csiphy_id; 1434 struct csiphy_device *csiphy = &camss->csiphy[id]; 1435 1436 csiphy->cfg.csi2 = &csd->interface.csi2; 1437 subdev->host_priv = csiphy; 1438 1439 return 0; 1440} 1441 1442static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async) 1443{ 1444 struct camss *camss = container_of(async, struct camss, notifier); 1445 struct v4l2_device *v4l2_dev = &camss->v4l2_dev; 1446 struct v4l2_subdev *sd; 1447 int ret; 1448 1449 list_for_each_entry(sd, &v4l2_dev->subdevs, list) { 1450 if (sd->host_priv) { 1451 struct media_entity *sensor = &sd->entity; 1452 struct csiphy_device *csiphy = 1453 (struct csiphy_device *) sd->host_priv; 1454 struct media_entity *input = &csiphy->subdev.entity; 1455 unsigned int i; 1456 1457 for (i = 0; i < sensor->num_pads; i++) { 1458 if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE) 1459 break; 1460 } 1461 if (i == sensor->num_pads) { 1462 dev_err(camss->dev, 1463 "No source pad in external entity\n"); 1464 return -EINVAL; 1465 } 1466 1467 ret = media_create_pad_link(sensor, i, 1468 input, MSM_CSIPHY_PAD_SINK, 1469 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 1470 if (ret < 0) { 1471 dev_err(camss->dev, 1472 "Failed to link %s->%s entities: %d\n", 1473 sensor->name, input->name, ret); 1474 return ret; 1475 } 1476 } 1477 } 1478 1479 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev); 1480 if (ret < 0) 1481 return ret; 1482 1483 return media_device_register(&camss->media_dev); 1484} 1485 1486static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = { 1487 .bound = camss_subdev_notifier_bound, 1488 .complete = camss_subdev_notifier_complete, 1489}; 1490 1491static const struct media_device_ops camss_media_ops = { 1492 .link_notify = v4l2_pipeline_link_notify, 1493}; 1494 1495static int camss_configure_pd(struct camss *camss) 1496{ 1497 const struct camss_resources *res = camss->res; 1498 struct device *dev = camss->dev; 1499 int vfepd_num; 1500 int i; 1501 int ret; 1502 1503 camss->genpd_num = of_count_phandle_with_args(dev->of_node, 1504 "power-domains", 1505 "#power-domain-cells"); 1506 if (camss->genpd_num < 0) { 1507 dev_err(dev, "Power domains are not defined for camss\n"); 1508 return camss->genpd_num; 1509 } 1510 1511 /* 1512 * If a platform device has just one power domain, then it is attached 1513 * at platform_probe() level, thus there shall be no need and even no 1514 * option to attach it again, this is the case for CAMSS on MSM8916. 1515 */ 1516 if (camss->genpd_num == 1) 1517 return 0; 1518 1519 /* count the # of VFEs which have flagged power-domain */ 1520 for (vfepd_num = i = 0; i < camss->res->vfe_num; i++) { 1521 if (res->vfe_res[i].has_pd) 1522 vfepd_num++; 1523 } 1524 1525 /* 1526 * If the number of power-domains is greater than the number of VFEs 1527 * then the additional power-domain is for the entire CAMSS block. 1528 */ 1529 if (!(camss->genpd_num > vfepd_num)) 1530 return 0; 1531 1532 /* 1533 * If a power-domain name is defined try to use it. 1534 * It is possible we are running a new kernel with an old dtb so 1535 * fallback to indexes even if a pd_name is defined but not found. 1536 */ 1537 if (camss->res->pd_name) { 1538 camss->genpd = dev_pm_domain_attach_by_name(camss->dev, 1539 camss->res->pd_name); 1540 if (IS_ERR(camss->genpd)) { 1541 ret = PTR_ERR(camss->genpd); 1542 goto fail_pm; 1543 } 1544 } 1545 1546 if (!camss->genpd) { 1547 /* 1548 * Legacy magic index. TITAN_TOP GDSC must be the last 1549 * item in the power-domain list. 1550 */ 1551 camss->genpd = dev_pm_domain_attach_by_id(camss->dev, 1552 camss->genpd_num - 1); 1553 } 1554 if (IS_ERR_OR_NULL(camss->genpd)) { 1555 if (!camss->genpd) 1556 ret = -ENODEV; 1557 else 1558 ret = PTR_ERR(camss->genpd); 1559 goto fail_pm; 1560 } 1561 camss->genpd_link = device_link_add(camss->dev, camss->genpd, 1562 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | 1563 DL_FLAG_RPM_ACTIVE); 1564 if (!camss->genpd_link) { 1565 ret = -EINVAL; 1566 goto fail_pm; 1567 } 1568 1569 return 0; 1570 1571fail_pm: 1572 dev_pm_domain_detach(camss->genpd, true); 1573 1574 return ret; 1575} 1576 1577static int camss_icc_get(struct camss *camss) 1578{ 1579 const struct resources_icc *icc_res; 1580 int i; 1581 1582 icc_res = camss->res->icc_res; 1583 1584 for (i = 0; i < camss->res->icc_path_num; i++) { 1585 camss->icc_path[i] = devm_of_icc_get(camss->dev, 1586 icc_res[i].name); 1587 if (IS_ERR(camss->icc_path[i])) 1588 return PTR_ERR(camss->icc_path[i]); 1589 } 1590 1591 return 0; 1592} 1593 1594static void camss_genpd_subdevice_cleanup(struct camss *camss) 1595{ 1596 int i; 1597 1598 for (i = 0; i < camss->res->vfe_num; i++) 1599 msm_vfe_genpd_cleanup(&camss->vfe[i]); 1600} 1601 1602static void camss_genpd_cleanup(struct camss *camss) 1603{ 1604 if (camss->genpd_num == 1) 1605 return; 1606 1607 camss_genpd_subdevice_cleanup(camss); 1608 1609 if (camss->genpd_link) 1610 device_link_del(camss->genpd_link); 1611 1612 dev_pm_domain_detach(camss->genpd, true); 1613} 1614 1615/* 1616 * camss_probe - Probe CAMSS platform device 1617 * @pdev: Pointer to CAMSS platform device 1618 * 1619 * Return 0 on success or a negative error code on failure 1620 */ 1621static int camss_probe(struct platform_device *pdev) 1622{ 1623 struct device *dev = &pdev->dev; 1624 struct camss *camss; 1625 int num_subdevs; 1626 int ret; 1627 1628 camss = devm_kzalloc(dev, sizeof(*camss), GFP_KERNEL); 1629 if (!camss) 1630 return -ENOMEM; 1631 1632 camss->res = of_device_get_match_data(dev); 1633 1634 atomic_set(&camss->ref_count, 0); 1635 camss->dev = dev; 1636 platform_set_drvdata(pdev, camss); 1637 1638 camss->csiphy = devm_kcalloc(dev, camss->res->csiphy_num, 1639 sizeof(*camss->csiphy), GFP_KERNEL); 1640 if (!camss->csiphy) 1641 return -ENOMEM; 1642 1643 camss->csid = devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->csid), 1644 GFP_KERNEL); 1645 if (!camss->csid) 1646 return -ENOMEM; 1647 1648 if (camss->res->version == CAMSS_8x16 || 1649 camss->res->version == CAMSS_8x96) { 1650 camss->ispif = devm_kcalloc(dev, 1, sizeof(*camss->ispif), GFP_KERNEL); 1651 if (!camss->ispif) 1652 return -ENOMEM; 1653 } 1654 1655 camss->vfe = devm_kcalloc(dev, camss->res->vfe_num, 1656 sizeof(*camss->vfe), GFP_KERNEL); 1657 if (!camss->vfe) 1658 return -ENOMEM; 1659 1660 ret = camss_icc_get(camss); 1661 if (ret < 0) 1662 return ret; 1663 1664 ret = camss_configure_pd(camss); 1665 if (ret < 0) { 1666 dev_err(dev, "Failed to configure power domains: %d\n", ret); 1667 return ret; 1668 } 1669 1670 ret = camss_init_subdevices(camss); 1671 if (ret < 0) 1672 goto err_genpd_cleanup; 1673 1674 ret = dma_set_mask_and_coherent(dev, 0xffffffff); 1675 if (ret) 1676 goto err_genpd_cleanup; 1677 1678 camss->media_dev.dev = camss->dev; 1679 strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem", 1680 sizeof(camss->media_dev.model)); 1681 camss->media_dev.ops = &camss_media_ops; 1682 media_device_init(&camss->media_dev); 1683 1684 camss->v4l2_dev.mdev = &camss->media_dev; 1685 ret = v4l2_device_register(camss->dev, &camss->v4l2_dev); 1686 if (ret < 0) { 1687 dev_err(dev, "Failed to register V4L2 device: %d\n", ret); 1688 goto err_genpd_cleanup; 1689 } 1690 1691 v4l2_async_nf_init(&camss->notifier, &camss->v4l2_dev); 1692 1693 num_subdevs = camss_of_parse_ports(camss); 1694 if (num_subdevs < 0) { 1695 ret = num_subdevs; 1696 goto err_v4l2_device_unregister; 1697 } 1698 1699 ret = camss_register_entities(camss); 1700 if (ret < 0) 1701 goto err_v4l2_device_unregister; 1702 1703 if (num_subdevs) { 1704 camss->notifier.ops = &camss_subdev_notifier_ops; 1705 1706 ret = v4l2_async_nf_register(&camss->notifier); 1707 if (ret) { 1708 dev_err(dev, 1709 "Failed to register async subdev nodes: %d\n", 1710 ret); 1711 goto err_register_subdevs; 1712 } 1713 } else { 1714 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev); 1715 if (ret < 0) { 1716 dev_err(dev, "Failed to register subdev nodes: %d\n", 1717 ret); 1718 goto err_register_subdevs; 1719 } 1720 1721 ret = media_device_register(&camss->media_dev); 1722 if (ret < 0) { 1723 dev_err(dev, "Failed to register media device: %d\n", 1724 ret); 1725 goto err_register_subdevs; 1726 } 1727 } 1728 1729 pm_runtime_enable(dev); 1730 1731 return 0; 1732 1733err_register_subdevs: 1734 camss_unregister_entities(camss); 1735err_v4l2_device_unregister: 1736 v4l2_device_unregister(&camss->v4l2_dev); 1737 v4l2_async_nf_cleanup(&camss->notifier); 1738err_genpd_cleanup: 1739 camss_genpd_cleanup(camss); 1740 1741 return ret; 1742} 1743 1744void camss_delete(struct camss *camss) 1745{ 1746 v4l2_device_unregister(&camss->v4l2_dev); 1747 media_device_unregister(&camss->media_dev); 1748 media_device_cleanup(&camss->media_dev); 1749 1750 pm_runtime_disable(camss->dev); 1751} 1752 1753/* 1754 * camss_remove - Remove CAMSS platform device 1755 * @pdev: Pointer to CAMSS platform device 1756 * 1757 * Always returns 0. 1758 */ 1759static void camss_remove(struct platform_device *pdev) 1760{ 1761 struct camss *camss = platform_get_drvdata(pdev); 1762 1763 v4l2_async_nf_unregister(&camss->notifier); 1764 v4l2_async_nf_cleanup(&camss->notifier); 1765 camss_unregister_entities(camss); 1766 1767 if (atomic_read(&camss->ref_count) == 0) 1768 camss_delete(camss); 1769 1770 camss_genpd_cleanup(camss); 1771} 1772 1773static const struct camss_resources msm8916_resources = { 1774 .version = CAMSS_8x16, 1775 .csiphy_res = csiphy_res_8x16, 1776 .csid_res = csid_res_8x16, 1777 .ispif_res = &ispif_res_8x16, 1778 .vfe_res = vfe_res_8x16, 1779 .csiphy_num = ARRAY_SIZE(csiphy_res_8x16), 1780 .csid_num = ARRAY_SIZE(csid_res_8x16), 1781 .vfe_num = ARRAY_SIZE(vfe_res_8x16), 1782}; 1783 1784static const struct camss_resources msm8996_resources = { 1785 .version = CAMSS_8x96, 1786 .csiphy_res = csiphy_res_8x96, 1787 .csid_res = csid_res_8x96, 1788 .ispif_res = &ispif_res_8x96, 1789 .vfe_res = vfe_res_8x96, 1790 .csiphy_num = ARRAY_SIZE(csiphy_res_8x96), 1791 .csid_num = ARRAY_SIZE(csid_res_8x96), 1792 .vfe_num = ARRAY_SIZE(vfe_res_8x96), 1793}; 1794 1795static const struct camss_resources sdm660_resources = { 1796 .version = CAMSS_660, 1797 .csiphy_res = csiphy_res_660, 1798 .csid_res = csid_res_660, 1799 .ispif_res = &ispif_res_660, 1800 .vfe_res = vfe_res_660, 1801 .csiphy_num = ARRAY_SIZE(csiphy_res_660), 1802 .csid_num = ARRAY_SIZE(csid_res_660), 1803 .vfe_num = ARRAY_SIZE(vfe_res_660), 1804}; 1805 1806static const struct camss_resources sdm845_resources = { 1807 .version = CAMSS_845, 1808 .csiphy_res = csiphy_res_845, 1809 .csid_res = csid_res_845, 1810 .vfe_res = vfe_res_845, 1811 .csiphy_num = ARRAY_SIZE(csiphy_res_845), 1812 .csid_num = ARRAY_SIZE(csid_res_845), 1813 .vfe_num = ARRAY_SIZE(vfe_res_845), 1814}; 1815 1816static const struct camss_resources sm8250_resources = { 1817 .version = CAMSS_8250, 1818 .pd_name = "top", 1819 .csiphy_res = csiphy_res_8250, 1820 .csid_res = csid_res_8250, 1821 .vfe_res = vfe_res_8250, 1822 .icc_res = icc_res_sm8250, 1823 .icc_path_num = ARRAY_SIZE(icc_res_sm8250), 1824 .csiphy_num = ARRAY_SIZE(csiphy_res_8250), 1825 .csid_num = ARRAY_SIZE(csid_res_8250), 1826 .vfe_num = ARRAY_SIZE(vfe_res_8250), 1827}; 1828 1829static const struct of_device_id camss_dt_match[] = { 1830 { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, 1831 { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, 1832 { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, 1833 { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, 1834 { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, 1835 { } 1836}; 1837 1838MODULE_DEVICE_TABLE(of, camss_dt_match); 1839 1840static int __maybe_unused camss_runtime_suspend(struct device *dev) 1841{ 1842 struct camss *camss = dev_get_drvdata(dev); 1843 int i; 1844 int ret; 1845 1846 for (i = 0; i < camss->res->icc_path_num; i++) { 1847 ret = icc_set_bw(camss->icc_path[i], 0, 0); 1848 if (ret) 1849 return ret; 1850 } 1851 1852 return 0; 1853} 1854 1855static int __maybe_unused camss_runtime_resume(struct device *dev) 1856{ 1857 struct camss *camss = dev_get_drvdata(dev); 1858 const struct resources_icc *icc_res = camss->res->icc_res; 1859 int i; 1860 int ret; 1861 1862 for (i = 0; i < camss->res->icc_path_num; i++) { 1863 ret = icc_set_bw(camss->icc_path[i], 1864 icc_res[i].icc_bw_tbl.avg, 1865 icc_res[i].icc_bw_tbl.peak); 1866 if (ret) 1867 return ret; 1868 } 1869 1870 return 0; 1871} 1872 1873static const struct dev_pm_ops camss_pm_ops = { 1874 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1875 pm_runtime_force_resume) 1876 SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL) 1877}; 1878 1879static struct platform_driver qcom_camss_driver = { 1880 .probe = camss_probe, 1881 .remove_new = camss_remove, 1882 .driver = { 1883 .name = "qcom-camss", 1884 .of_match_table = camss_dt_match, 1885 .pm = &camss_pm_ops, 1886 }, 1887}; 1888 1889module_platform_driver(qcom_camss_driver); 1890 1891MODULE_ALIAS("platform:qcom-camss"); 1892MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver"); 1893MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 1894MODULE_LICENSE("GPL v2"); 1895