1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2020 Intel Corporation. 3 4#include <asm/unaligned.h> 5#include <linux/acpi.h> 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/gpio/consumer.h> 9#include <linux/i2c.h> 10#include <linux/module.h> 11#include <linux/pm_runtime.h> 12#include <linux/nvmem-provider.h> 13#include <linux/regmap.h> 14#include <media/v4l2-ctrls.h> 15#include <media/v4l2-device.h> 16#include <media/v4l2-fwnode.h> 17 18#define OV2740_LINK_FREQ_360MHZ 360000000ULL 19#define OV2740_LINK_FREQ_180MHZ 180000000ULL 20#define OV2740_SCLK 72000000LL 21#define OV2740_MCLK 19200000 22#define OV2740_DATA_LANES 2 23#define OV2740_RGB_DEPTH 10 24 25#define OV2740_REG_CHIP_ID 0x300a 26#define OV2740_CHIP_ID 0x2740 27 28#define OV2740_REG_MODE_SELECT 0x0100 29#define OV2740_MODE_STANDBY 0x00 30#define OV2740_MODE_STREAMING 0x01 31 32/* vertical-timings from sensor */ 33#define OV2740_REG_VTS 0x380e 34 35/* horizontal-timings from sensor */ 36#define OV2740_REG_HTS 0x380c 37 38/* Exposure controls from sensor */ 39#define OV2740_REG_EXPOSURE 0x3500 40#define OV2740_EXPOSURE_MIN 4 41#define OV2740_EXPOSURE_MAX_MARGIN 8 42#define OV2740_EXPOSURE_STEP 1 43 44/* Analog gain controls from sensor */ 45#define OV2740_REG_ANALOG_GAIN 0x3508 46#define OV2740_ANAL_GAIN_MIN 128 47#define OV2740_ANAL_GAIN_MAX 1983 48#define OV2740_ANAL_GAIN_STEP 1 49 50/* Digital gain controls from sensor */ 51#define OV2740_REG_MWB_R_GAIN 0x500a 52#define OV2740_REG_MWB_G_GAIN 0x500c 53#define OV2740_REG_MWB_B_GAIN 0x500e 54#define OV2740_DGTL_GAIN_MIN 1024 55#define OV2740_DGTL_GAIN_MAX 4095 56#define OV2740_DGTL_GAIN_STEP 1 57#define OV2740_DGTL_GAIN_DEFAULT 1024 58 59/* Test Pattern Control */ 60#define OV2740_REG_TEST_PATTERN 0x5040 61#define OV2740_TEST_PATTERN_ENABLE BIT(7) 62#define OV2740_TEST_PATTERN_BAR_SHIFT 2 63 64/* Group Access */ 65#define OV2740_REG_GROUP_ACCESS 0x3208 66#define OV2740_GROUP_HOLD_START 0x0 67#define OV2740_GROUP_HOLD_END 0x10 68#define OV2740_GROUP_HOLD_LAUNCH 0xa0 69 70/* ISP CTRL00 */ 71#define OV2740_REG_ISP_CTRL00 0x5000 72/* ISP CTRL01 */ 73#define OV2740_REG_ISP_CTRL01 0x5001 74/* Customer Addresses: 0x7010 - 0x710F */ 75#define CUSTOMER_USE_OTP_SIZE 0x100 76/* OTP registers from sensor */ 77#define OV2740_REG_OTP_CUSTOMER 0x7010 78 79struct nvm_data { 80 struct nvmem_device *nvmem; 81 struct regmap *regmap; 82 char *nvm_buffer; 83}; 84 85enum { 86 OV2740_LINK_FREQ_360MHZ_INDEX, 87 OV2740_LINK_FREQ_180MHZ_INDEX, 88}; 89 90struct ov2740_reg { 91 u16 address; 92 u8 val; 93}; 94 95struct ov2740_reg_list { 96 u32 num_of_regs; 97 const struct ov2740_reg *regs; 98}; 99 100struct ov2740_link_freq_config { 101 const struct ov2740_reg_list reg_list; 102}; 103 104struct ov2740_mode { 105 /* Frame width in pixels */ 106 u32 width; 107 108 /* Frame height in pixels */ 109 u32 height; 110 111 /* Horizontal timining size */ 112 u32 hts; 113 114 /* Default vertical timining size */ 115 u32 vts_def; 116 117 /* Min vertical timining size */ 118 u32 vts_min; 119 120 /* Max vertical timining size */ 121 u32 vts_max; 122 123 /* Link frequency needed for this resolution */ 124 u32 link_freq_index; 125 126 /* Sensor register settings for this resolution */ 127 const struct ov2740_reg_list reg_list; 128}; 129 130static const struct ov2740_reg mipi_data_rate_720mbps[] = { 131 {0x0302, 0x4b}, 132 {0x030d, 0x4b}, 133 {0x030e, 0x02}, 134 {0x030a, 0x01}, 135 {0x0312, 0x11}, 136}; 137 138static const struct ov2740_reg mipi_data_rate_360mbps[] = { 139 {0x0302, 0x4b}, 140 {0x0303, 0x01}, 141 {0x030d, 0x4b}, 142 {0x030e, 0x02}, 143 {0x030a, 0x01}, 144 {0x0312, 0x11}, 145 {0x4837, 0x2c}, 146}; 147 148static const struct ov2740_reg mode_1932x1092_regs_360mhz[] = { 149 {0x3000, 0x00}, 150 {0x3018, 0x32}, 151 {0x3031, 0x0a}, 152 {0x3080, 0x08}, 153 {0x3083, 0xB4}, 154 {0x3103, 0x00}, 155 {0x3104, 0x01}, 156 {0x3106, 0x01}, 157 {0x3500, 0x00}, 158 {0x3501, 0x44}, 159 {0x3502, 0x40}, 160 {0x3503, 0x88}, 161 {0x3507, 0x00}, 162 {0x3508, 0x00}, 163 {0x3509, 0x80}, 164 {0x350c, 0x00}, 165 {0x350d, 0x80}, 166 {0x3510, 0x00}, 167 {0x3511, 0x00}, 168 {0x3512, 0x20}, 169 {0x3632, 0x00}, 170 {0x3633, 0x10}, 171 {0x3634, 0x10}, 172 {0x3635, 0x10}, 173 {0x3645, 0x13}, 174 {0x3646, 0x81}, 175 {0x3636, 0x10}, 176 {0x3651, 0x0a}, 177 {0x3656, 0x02}, 178 {0x3659, 0x04}, 179 {0x365a, 0xda}, 180 {0x365b, 0xa2}, 181 {0x365c, 0x04}, 182 {0x365d, 0x1d}, 183 {0x365e, 0x1a}, 184 {0x3662, 0xd7}, 185 {0x3667, 0x78}, 186 {0x3669, 0x0a}, 187 {0x366a, 0x92}, 188 {0x3700, 0x54}, 189 {0x3702, 0x10}, 190 {0x3706, 0x42}, 191 {0x3709, 0x30}, 192 {0x370b, 0xc2}, 193 {0x3714, 0x63}, 194 {0x3715, 0x01}, 195 {0x3716, 0x00}, 196 {0x371a, 0x3e}, 197 {0x3732, 0x0e}, 198 {0x3733, 0x10}, 199 {0x375f, 0x0e}, 200 {0x3768, 0x30}, 201 {0x3769, 0x44}, 202 {0x376a, 0x22}, 203 {0x377b, 0x20}, 204 {0x377c, 0x00}, 205 {0x377d, 0x0c}, 206 {0x3798, 0x00}, 207 {0x37a1, 0x55}, 208 {0x37a8, 0x6d}, 209 {0x37c2, 0x04}, 210 {0x37c5, 0x00}, 211 {0x37c8, 0x00}, 212 {0x3800, 0x00}, 213 {0x3801, 0x00}, 214 {0x3802, 0x00}, 215 {0x3803, 0x00}, 216 {0x3804, 0x07}, 217 {0x3805, 0x8f}, 218 {0x3806, 0x04}, 219 {0x3807, 0x47}, 220 {0x3808, 0x07}, 221 {0x3809, 0x88}, 222 {0x380a, 0x04}, 223 {0x380b, 0x40}, 224 {0x380c, 0x04}, 225 {0x380d, 0x38}, 226 {0x380e, 0x04}, 227 {0x380f, 0x60}, 228 {0x3810, 0x00}, 229 {0x3811, 0x04}, 230 {0x3812, 0x00}, 231 {0x3813, 0x04}, 232 {0x3814, 0x01}, 233 {0x3815, 0x01}, 234 {0x3820, 0x80}, 235 {0x3821, 0x46}, 236 {0x3822, 0x84}, 237 {0x3829, 0x00}, 238 {0x382a, 0x01}, 239 {0x382b, 0x01}, 240 {0x3830, 0x04}, 241 {0x3836, 0x01}, 242 {0x3837, 0x08}, 243 {0x3839, 0x01}, 244 {0x383a, 0x00}, 245 {0x383b, 0x08}, 246 {0x383c, 0x00}, 247 {0x3f0b, 0x00}, 248 {0x4001, 0x20}, 249 {0x4009, 0x07}, 250 {0x4003, 0x10}, 251 {0x4010, 0xe0}, 252 {0x4016, 0x00}, 253 {0x4017, 0x10}, 254 {0x4044, 0x02}, 255 {0x4304, 0x08}, 256 {0x4307, 0x30}, 257 {0x4320, 0x80}, 258 {0x4322, 0x00}, 259 {0x4323, 0x00}, 260 {0x4324, 0x00}, 261 {0x4325, 0x00}, 262 {0x4326, 0x00}, 263 {0x4327, 0x00}, 264 {0x4328, 0x00}, 265 {0x4329, 0x00}, 266 {0x432c, 0x03}, 267 {0x432d, 0x81}, 268 {0x4501, 0x84}, 269 {0x4502, 0x40}, 270 {0x4503, 0x18}, 271 {0x4504, 0x04}, 272 {0x4508, 0x02}, 273 {0x4601, 0x10}, 274 {0x4800, 0x00}, 275 {0x4816, 0x52}, 276 {0x4837, 0x16}, 277 {0x5000, 0x7f}, 278 {0x5001, 0x00}, 279 {0x5005, 0x38}, 280 {0x501e, 0x0d}, 281 {0x5040, 0x00}, 282 {0x5901, 0x00}, 283 {0x3800, 0x00}, 284 {0x3801, 0x00}, 285 {0x3802, 0x00}, 286 {0x3803, 0x00}, 287 {0x3804, 0x07}, 288 {0x3805, 0x8f}, 289 {0x3806, 0x04}, 290 {0x3807, 0x47}, 291 {0x3808, 0x07}, 292 {0x3809, 0x8c}, 293 {0x380a, 0x04}, 294 {0x380b, 0x44}, 295 {0x3810, 0x00}, 296 {0x3811, 0x00}, 297 {0x3812, 0x00}, 298 {0x3813, 0x01}, 299}; 300 301static const struct ov2740_reg mode_1932x1092_regs_180mhz[] = { 302 {0x3000, 0x00}, 303 {0x3018, 0x32}, /* 0x32 for 2 lanes, 0x12 for 1 lane */ 304 {0x3031, 0x0a}, 305 {0x3080, 0x08}, 306 {0x3083, 0xB4}, 307 {0x3103, 0x00}, 308 {0x3104, 0x01}, 309 {0x3106, 0x01}, 310 {0x3500, 0x00}, 311 {0x3501, 0x44}, 312 {0x3502, 0x40}, 313 {0x3503, 0x88}, 314 {0x3507, 0x00}, 315 {0x3508, 0x00}, 316 {0x3509, 0x80}, 317 {0x350c, 0x00}, 318 {0x350d, 0x80}, 319 {0x3510, 0x00}, 320 {0x3511, 0x00}, 321 {0x3512, 0x20}, 322 {0x3632, 0x00}, 323 {0x3633, 0x10}, 324 {0x3634, 0x10}, 325 {0x3635, 0x10}, 326 {0x3645, 0x13}, 327 {0x3646, 0x81}, 328 {0x3636, 0x10}, 329 {0x3651, 0x0a}, 330 {0x3656, 0x02}, 331 {0x3659, 0x04}, 332 {0x365a, 0xda}, 333 {0x365b, 0xa2}, 334 {0x365c, 0x04}, 335 {0x365d, 0x1d}, 336 {0x365e, 0x1a}, 337 {0x3662, 0xd7}, 338 {0x3667, 0x78}, 339 {0x3669, 0x0a}, 340 {0x366a, 0x92}, 341 {0x3700, 0x54}, 342 {0x3702, 0x10}, 343 {0x3706, 0x42}, 344 {0x3709, 0x30}, 345 {0x370b, 0xc2}, 346 {0x3714, 0x63}, 347 {0x3715, 0x01}, 348 {0x3716, 0x00}, 349 {0x371a, 0x3e}, 350 {0x3732, 0x0e}, 351 {0x3733, 0x10}, 352 {0x375f, 0x0e}, 353 {0x3768, 0x30}, 354 {0x3769, 0x44}, 355 {0x376a, 0x22}, 356 {0x377b, 0x20}, 357 {0x377c, 0x00}, 358 {0x377d, 0x0c}, 359 {0x3798, 0x00}, 360 {0x37a1, 0x55}, 361 {0x37a8, 0x6d}, 362 {0x37c2, 0x04}, 363 {0x37c5, 0x00}, 364 {0x37c8, 0x00}, 365 {0x3800, 0x00}, 366 {0x3801, 0x00}, 367 {0x3802, 0x00}, 368 {0x3803, 0x00}, 369 {0x3804, 0x07}, 370 {0x3805, 0x8f}, 371 {0x3806, 0x04}, 372 {0x3807, 0x47}, 373 {0x3808, 0x07}, 374 {0x3809, 0x88}, 375 {0x380a, 0x04}, 376 {0x380b, 0x40}, 377 {0x380c, 0x08}, 378 {0x380d, 0x70}, 379 {0x380e, 0x04}, 380 {0x380f, 0x56}, 381 {0x3810, 0x00}, 382 {0x3811, 0x04}, 383 {0x3812, 0x00}, 384 {0x3813, 0x04}, 385 {0x3814, 0x01}, 386 {0x3815, 0x01}, 387 {0x3820, 0x80}, 388 {0x3821, 0x46}, 389 {0x3822, 0x84}, 390 {0x3829, 0x00}, 391 {0x382a, 0x01}, 392 {0x382b, 0x01}, 393 {0x3830, 0x04}, 394 {0x3836, 0x01}, 395 {0x3837, 0x08}, 396 {0x3839, 0x01}, 397 {0x383a, 0x00}, 398 {0x383b, 0x08}, 399 {0x383c, 0x00}, 400 {0x3f0b, 0x00}, 401 {0x4001, 0x20}, 402 {0x4009, 0x07}, 403 {0x4003, 0x10}, 404 {0x4010, 0xe0}, 405 {0x4016, 0x00}, 406 {0x4017, 0x10}, 407 {0x4044, 0x02}, 408 {0x4304, 0x08}, 409 {0x4307, 0x30}, 410 {0x4320, 0x80}, 411 {0x4322, 0x00}, 412 {0x4323, 0x00}, 413 {0x4324, 0x00}, 414 {0x4325, 0x00}, 415 {0x4326, 0x00}, 416 {0x4327, 0x00}, 417 {0x4328, 0x00}, 418 {0x4329, 0x00}, 419 {0x432c, 0x03}, 420 {0x432d, 0x81}, 421 {0x4501, 0x84}, 422 {0x4502, 0x40}, 423 {0x4503, 0x18}, 424 {0x4504, 0x04}, 425 {0x4508, 0x02}, 426 {0x4601, 0x10}, 427 {0x4800, 0x00}, 428 {0x4816, 0x52}, 429 {0x5000, 0x73}, /* 0x7f enable DPC */ 430 {0x5001, 0x00}, 431 {0x5005, 0x38}, 432 {0x501e, 0x0d}, 433 {0x5040, 0x00}, 434 {0x5901, 0x00}, 435 {0x3800, 0x00}, 436 {0x3801, 0x00}, 437 {0x3802, 0x00}, 438 {0x3803, 0x00}, 439 {0x3804, 0x07}, 440 {0x3805, 0x8f}, 441 {0x3806, 0x04}, 442 {0x3807, 0x47}, 443 {0x3808, 0x07}, 444 {0x3809, 0x8c}, 445 {0x380a, 0x04}, 446 {0x380b, 0x44}, 447 {0x3810, 0x00}, 448 {0x3811, 0x00}, 449 {0x3812, 0x00}, 450 {0x3813, 0x01}, 451 {0x4003, 0x40}, /* set Black level to 0x40 */ 452}; 453 454static const char * const ov2740_test_pattern_menu[] = { 455 "Disabled", 456 "Color Bar", 457 "Top-Bottom Darker Color Bar", 458 "Right-Left Darker Color Bar", 459 "Bottom-Top Darker Color Bar", 460}; 461 462static const s64 link_freq_menu_items[] = { 463 OV2740_LINK_FREQ_360MHZ, 464 OV2740_LINK_FREQ_180MHZ, 465}; 466 467static const struct ov2740_link_freq_config link_freq_configs[] = { 468 [OV2740_LINK_FREQ_360MHZ_INDEX] = { 469 .reg_list = { 470 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps), 471 .regs = mipi_data_rate_720mbps, 472 } 473 }, 474 [OV2740_LINK_FREQ_180MHZ_INDEX] = { 475 .reg_list = { 476 .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps), 477 .regs = mipi_data_rate_360mbps, 478 } 479 }, 480}; 481 482static const struct ov2740_mode supported_modes_360mhz[] = { 483 { 484 .width = 1932, 485 .height = 1092, 486 .hts = 2160, 487 .vts_min = 1120, 488 .vts_def = 2186, 489 .vts_max = 32767, 490 .reg_list = { 491 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_360mhz), 492 .regs = mode_1932x1092_regs_360mhz, 493 }, 494 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX, 495 }, 496}; 497 498static const struct ov2740_mode supported_modes_180mhz[] = { 499 { 500 .width = 1932, 501 .height = 1092, 502 .hts = 2160, 503 .vts_min = 1110, 504 .vts_def = 1110, 505 .vts_max = 2047, 506 .reg_list = { 507 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_180mhz), 508 .regs = mode_1932x1092_regs_180mhz, 509 }, 510 .link_freq_index = OV2740_LINK_FREQ_180MHZ_INDEX, 511 }, 512}; 513 514struct ov2740 { 515 struct v4l2_subdev sd; 516 struct media_pad pad; 517 struct v4l2_ctrl_handler ctrl_handler; 518 519 /* V4L2 Controls */ 520 struct v4l2_ctrl *link_freq; 521 struct v4l2_ctrl *pixel_rate; 522 struct v4l2_ctrl *vblank; 523 struct v4l2_ctrl *hblank; 524 struct v4l2_ctrl *exposure; 525 526 /* GPIOs, clocks */ 527 struct gpio_desc *reset_gpio; 528 struct clk *clk; 529 530 /* Current mode */ 531 const struct ov2740_mode *cur_mode; 532 533 /* NVM data inforamtion */ 534 struct nvm_data *nvm; 535 536 /* Supported modes */ 537 const struct ov2740_mode *supported_modes; 538 int supported_modes_count; 539 540 /* True if the device has been identified */ 541 bool identified; 542}; 543 544static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev) 545{ 546 return container_of(subdev, struct ov2740, sd); 547} 548 549static u64 to_pixel_rate(u32 f_index) 550{ 551 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES; 552 553 do_div(pixel_rate, OV2740_RGB_DEPTH); 554 555 return pixel_rate; 556} 557 558static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val) 559{ 560 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 561 struct i2c_msg msgs[2]; 562 u8 addr_buf[2]; 563 u8 data_buf[4] = {0}; 564 int ret; 565 566 if (len > sizeof(data_buf)) 567 return -EINVAL; 568 569 put_unaligned_be16(reg, addr_buf); 570 msgs[0].addr = client->addr; 571 msgs[0].flags = 0; 572 msgs[0].len = sizeof(addr_buf); 573 msgs[0].buf = addr_buf; 574 msgs[1].addr = client->addr; 575 msgs[1].flags = I2C_M_RD; 576 msgs[1].len = len; 577 msgs[1].buf = &data_buf[sizeof(data_buf) - len]; 578 579 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 580 if (ret != ARRAY_SIZE(msgs)) 581 return ret < 0 ? ret : -EIO; 582 583 *val = get_unaligned_be32(data_buf); 584 585 return 0; 586} 587 588static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val) 589{ 590 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 591 u8 buf[6]; 592 int ret; 593 594 if (len > 4) 595 return -EINVAL; 596 597 put_unaligned_be16(reg, buf); 598 put_unaligned_be32(val << 8 * (4 - len), buf + 2); 599 600 ret = i2c_master_send(client, buf, len + 2); 601 if (ret != len + 2) 602 return ret < 0 ? ret : -EIO; 603 604 return 0; 605} 606 607static int ov2740_write_reg_list(struct ov2740 *ov2740, 608 const struct ov2740_reg_list *r_list) 609{ 610 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 611 unsigned int i; 612 int ret; 613 614 for (i = 0; i < r_list->num_of_regs; i++) { 615 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1, 616 r_list->regs[i].val); 617 if (ret) { 618 dev_err_ratelimited(&client->dev, 619 "write reg 0x%4.4x return err = %d\n", 620 r_list->regs[i].address, ret); 621 return ret; 622 } 623 } 624 625 return 0; 626} 627 628static int ov2740_identify_module(struct ov2740 *ov2740) 629{ 630 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 631 int ret; 632 u32 val; 633 634 if (ov2740->identified) 635 return 0; 636 637 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val); 638 if (ret) 639 return ret; 640 641 if (val != OV2740_CHIP_ID) { 642 dev_err(&client->dev, "chip id mismatch: %x != %x\n", 643 OV2740_CHIP_ID, val); 644 return -ENXIO; 645 } 646 647 ov2740->identified = true; 648 649 return 0; 650} 651 652static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain) 653{ 654 int ret; 655 656 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 657 OV2740_GROUP_HOLD_START); 658 if (ret) 659 return ret; 660 661 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain); 662 if (ret) 663 return ret; 664 665 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain); 666 if (ret) 667 return ret; 668 669 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain); 670 if (ret) 671 return ret; 672 673 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 674 OV2740_GROUP_HOLD_END); 675 if (ret) 676 return ret; 677 678 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1, 679 OV2740_GROUP_HOLD_LAUNCH); 680 return ret; 681} 682 683static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern) 684{ 685 if (pattern) 686 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT | 687 OV2740_TEST_PATTERN_ENABLE; 688 689 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern); 690} 691 692static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl) 693{ 694 struct ov2740 *ov2740 = container_of(ctrl->handler, 695 struct ov2740, ctrl_handler); 696 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 697 s64 exposure_max; 698 int ret; 699 700 /* Propagate change of current control to all related controls */ 701 if (ctrl->id == V4L2_CID_VBLANK) { 702 /* Update max exposure while meeting expected vblanking */ 703 exposure_max = ov2740->cur_mode->height + ctrl->val - 704 OV2740_EXPOSURE_MAX_MARGIN; 705 __v4l2_ctrl_modify_range(ov2740->exposure, 706 ov2740->exposure->minimum, 707 exposure_max, ov2740->exposure->step, 708 exposure_max); 709 } 710 711 /* V4L2 controls values will be applied only when power is already up */ 712 if (!pm_runtime_get_if_in_use(&client->dev)) 713 return 0; 714 715 switch (ctrl->id) { 716 case V4L2_CID_ANALOGUE_GAIN: 717 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2, 718 ctrl->val); 719 break; 720 721 case V4L2_CID_DIGITAL_GAIN: 722 ret = ov2740_update_digital_gain(ov2740, ctrl->val); 723 break; 724 725 case V4L2_CID_EXPOSURE: 726 /* 4 least significant bits of expsoure are fractional part */ 727 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3, 728 ctrl->val << 4); 729 break; 730 731 case V4L2_CID_VBLANK: 732 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2, 733 ov2740->cur_mode->height + ctrl->val); 734 break; 735 736 case V4L2_CID_TEST_PATTERN: 737 ret = ov2740_test_pattern(ov2740, ctrl->val); 738 break; 739 740 default: 741 ret = -EINVAL; 742 break; 743 } 744 745 pm_runtime_put(&client->dev); 746 747 return ret; 748} 749 750static const struct v4l2_ctrl_ops ov2740_ctrl_ops = { 751 .s_ctrl = ov2740_set_ctrl, 752}; 753 754static int ov2740_init_controls(struct ov2740 *ov2740) 755{ 756 struct v4l2_ctrl_handler *ctrl_hdlr; 757 const struct ov2740_mode *cur_mode; 758 s64 exposure_max, h_blank, pixel_rate; 759 u32 vblank_min, vblank_max, vblank_default; 760 int size; 761 int ret; 762 763 ctrl_hdlr = &ov2740->ctrl_handler; 764 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8); 765 if (ret) 766 return ret; 767 768 cur_mode = ov2740->cur_mode; 769 size = ARRAY_SIZE(link_freq_menu_items); 770 771 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops, 772 V4L2_CID_LINK_FREQ, 773 size - 1, 0, 774 link_freq_menu_items); 775 if (ov2740->link_freq) 776 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 777 778 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX); 779 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 780 V4L2_CID_PIXEL_RATE, 0, 781 pixel_rate, 1, pixel_rate); 782 783 vblank_min = cur_mode->vts_min - cur_mode->height; 784 vblank_max = cur_mode->vts_max - cur_mode->height; 785 vblank_default = cur_mode->vts_def - cur_mode->height; 786 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 787 V4L2_CID_VBLANK, vblank_min, 788 vblank_max, 1, vblank_default); 789 790 h_blank = cur_mode->hts - cur_mode->width; 791 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 792 V4L2_CID_HBLANK, h_blank, h_blank, 1, 793 h_blank); 794 if (ov2740->hblank) 795 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 796 797 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 798 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX, 799 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN); 800 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 801 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX, 802 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT); 803 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN; 804 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, 805 V4L2_CID_EXPOSURE, 806 OV2740_EXPOSURE_MIN, exposure_max, 807 OV2740_EXPOSURE_STEP, 808 exposure_max); 809 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops, 810 V4L2_CID_TEST_PATTERN, 811 ARRAY_SIZE(ov2740_test_pattern_menu) - 1, 812 0, 0, ov2740_test_pattern_menu); 813 if (ctrl_hdlr->error) { 814 v4l2_ctrl_handler_free(ctrl_hdlr); 815 return ctrl_hdlr->error; 816 } 817 818 ov2740->sd.ctrl_handler = ctrl_hdlr; 819 820 return 0; 821} 822 823static void ov2740_update_pad_format(const struct ov2740_mode *mode, 824 struct v4l2_mbus_framefmt *fmt) 825{ 826 fmt->width = mode->width; 827 fmt->height = mode->height; 828 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; 829 fmt->field = V4L2_FIELD_NONE; 830} 831 832static int ov2740_load_otp_data(struct nvm_data *nvm) 833{ 834 struct device *dev = regmap_get_device(nvm->regmap); 835 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 836 u32 isp_ctrl00 = 0; 837 u32 isp_ctrl01 = 0; 838 int ret; 839 840 if (nvm->nvm_buffer) 841 return 0; 842 843 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL); 844 if (!nvm->nvm_buffer) 845 return -ENOMEM; 846 847 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00); 848 if (ret) { 849 dev_err(dev, "failed to read ISP CTRL00\n"); 850 goto err; 851 } 852 853 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01); 854 if (ret) { 855 dev_err(dev, "failed to read ISP CTRL01\n"); 856 goto err; 857 } 858 859 /* Clear bit 5 of ISP CTRL00 */ 860 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, 861 isp_ctrl00 & ~BIT(5)); 862 if (ret) { 863 dev_err(dev, "failed to set ISP CTRL00\n"); 864 goto err; 865 } 866 867 /* Clear bit 7 of ISP CTRL01 */ 868 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, 869 isp_ctrl01 & ~BIT(7)); 870 if (ret) { 871 dev_err(dev, "failed to set ISP CTRL01\n"); 872 goto err; 873 } 874 875 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 876 OV2740_MODE_STREAMING); 877 if (ret) { 878 dev_err(dev, "failed to set streaming mode\n"); 879 goto err; 880 } 881 882 /* 883 * Users are not allowed to access OTP-related registers and memory 884 * during the 20 ms period after streaming starts (0x100 = 0x01). 885 */ 886 msleep(20); 887 888 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER, 889 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE); 890 if (ret) { 891 dev_err(dev, "failed to read OTP data, ret %d\n", ret); 892 goto err; 893 } 894 895 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 896 OV2740_MODE_STANDBY); 897 if (ret) { 898 dev_err(dev, "failed to set streaming mode\n"); 899 goto err; 900 } 901 902 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01); 903 if (ret) { 904 dev_err(dev, "failed to set ISP CTRL01\n"); 905 goto err; 906 } 907 908 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00); 909 if (ret) { 910 dev_err(dev, "failed to set ISP CTRL00\n"); 911 goto err; 912 } 913 914 return 0; 915err: 916 kfree(nvm->nvm_buffer); 917 nvm->nvm_buffer = NULL; 918 919 return ret; 920} 921 922static int ov2740_start_streaming(struct ov2740 *ov2740) 923{ 924 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 925 const struct ov2740_reg_list *reg_list; 926 int link_freq_index; 927 int ret; 928 929 ret = ov2740_identify_module(ov2740); 930 if (ret) 931 return ret; 932 933 if (ov2740->nvm) 934 ov2740_load_otp_data(ov2740->nvm); 935 936 /* Reset the sensor */ 937 ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01); 938 if (ret) { 939 dev_err(&client->dev, "failed to reset\n"); 940 return ret; 941 } 942 943 usleep_range(10000, 15000); 944 945 link_freq_index = ov2740->cur_mode->link_freq_index; 946 reg_list = &link_freq_configs[link_freq_index].reg_list; 947 ret = ov2740_write_reg_list(ov2740, reg_list); 948 if (ret) { 949 dev_err(&client->dev, "failed to set plls\n"); 950 return ret; 951 } 952 953 reg_list = &ov2740->cur_mode->reg_list; 954 ret = ov2740_write_reg_list(ov2740, reg_list); 955 if (ret) { 956 dev_err(&client->dev, "failed to set mode\n"); 957 return ret; 958 } 959 960 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler); 961 if (ret) 962 return ret; 963 964 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 965 OV2740_MODE_STREAMING); 966 if (ret) 967 dev_err(&client->dev, "failed to start streaming\n"); 968 969 return ret; 970} 971 972static void ov2740_stop_streaming(struct ov2740 *ov2740) 973{ 974 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd); 975 976 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1, 977 OV2740_MODE_STANDBY)) 978 dev_err(&client->dev, "failed to stop streaming\n"); 979} 980 981static int ov2740_set_stream(struct v4l2_subdev *sd, int enable) 982{ 983 struct ov2740 *ov2740 = to_ov2740(sd); 984 struct i2c_client *client = v4l2_get_subdevdata(sd); 985 struct v4l2_subdev_state *sd_state; 986 int ret = 0; 987 988 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 989 990 if (enable) { 991 ret = pm_runtime_resume_and_get(&client->dev); 992 if (ret < 0) 993 goto out_unlock; 994 995 ret = ov2740_start_streaming(ov2740); 996 if (ret) { 997 enable = 0; 998 ov2740_stop_streaming(ov2740); 999 pm_runtime_put(&client->dev); 1000 } 1001 } else { 1002 ov2740_stop_streaming(ov2740); 1003 pm_runtime_put(&client->dev); 1004 } 1005 1006out_unlock: 1007 v4l2_subdev_unlock_state(sd_state); 1008 1009 return ret; 1010} 1011 1012static int ov2740_set_format(struct v4l2_subdev *sd, 1013 struct v4l2_subdev_state *sd_state, 1014 struct v4l2_subdev_format *fmt) 1015{ 1016 struct ov2740 *ov2740 = to_ov2740(sd); 1017 const struct ov2740_mode *mode; 1018 s32 vblank_def, h_blank; 1019 1020 mode = v4l2_find_nearest_size(ov2740->supported_modes, 1021 ov2740->supported_modes_count, 1022 width, height, 1023 fmt->format.width, fmt->format.height); 1024 1025 ov2740_update_pad_format(mode, &fmt->format); 1026 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format; 1027 1028 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 1029 return 0; 1030 1031 ov2740->cur_mode = mode; 1032 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index); 1033 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate, 1034 to_pixel_rate(mode->link_freq_index)); 1035 1036 /* Update limits and set FPS to default */ 1037 vblank_def = mode->vts_def - mode->height; 1038 __v4l2_ctrl_modify_range(ov2740->vblank, 1039 mode->vts_min - mode->height, 1040 mode->vts_max - mode->height, 1, vblank_def); 1041 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def); 1042 h_blank = mode->hts - mode->width; 1043 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank); 1044 1045 return 0; 1046} 1047 1048static int ov2740_enum_mbus_code(struct v4l2_subdev *sd, 1049 struct v4l2_subdev_state *sd_state, 1050 struct v4l2_subdev_mbus_code_enum *code) 1051{ 1052 if (code->index > 0) 1053 return -EINVAL; 1054 1055 code->code = MEDIA_BUS_FMT_SGRBG10_1X10; 1056 1057 return 0; 1058} 1059 1060static int ov2740_enum_frame_size(struct v4l2_subdev *sd, 1061 struct v4l2_subdev_state *sd_state, 1062 struct v4l2_subdev_frame_size_enum *fse) 1063{ 1064 struct ov2740 *ov2740 = to_ov2740(sd); 1065 const struct ov2740_mode *supported_modes = ov2740->supported_modes; 1066 1067 if (fse->index >= ov2740->supported_modes_count) 1068 return -EINVAL; 1069 1070 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10) 1071 return -EINVAL; 1072 1073 fse->min_width = supported_modes[fse->index].width; 1074 fse->max_width = fse->min_width; 1075 fse->min_height = supported_modes[fse->index].height; 1076 fse->max_height = fse->min_height; 1077 1078 return 0; 1079} 1080 1081static int ov2740_init_state(struct v4l2_subdev *sd, 1082 struct v4l2_subdev_state *sd_state) 1083{ 1084 struct ov2740 *ov2740 = to_ov2740(sd); 1085 1086 ov2740_update_pad_format(&ov2740->supported_modes[0], 1087 v4l2_subdev_state_get_format(sd_state, 0)); 1088 return 0; 1089} 1090 1091static const struct v4l2_subdev_video_ops ov2740_video_ops = { 1092 .s_stream = ov2740_set_stream, 1093}; 1094 1095static const struct v4l2_subdev_pad_ops ov2740_pad_ops = { 1096 .get_fmt = v4l2_subdev_get_fmt, 1097 .set_fmt = ov2740_set_format, 1098 .enum_mbus_code = ov2740_enum_mbus_code, 1099 .enum_frame_size = ov2740_enum_frame_size, 1100}; 1101 1102static const struct v4l2_subdev_ops ov2740_subdev_ops = { 1103 .video = &ov2740_video_ops, 1104 .pad = &ov2740_pad_ops, 1105}; 1106 1107static const struct v4l2_subdev_internal_ops ov2740_internal_ops = { 1108 .init_state = ov2740_init_state, 1109}; 1110 1111static const struct media_entity_operations ov2740_subdev_entity_ops = { 1112 .link_validate = v4l2_subdev_link_validate, 1113}; 1114 1115static int ov2740_check_hwcfg(struct device *dev) 1116{ 1117 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1118 struct ov2740 *ov2740 = to_ov2740(sd); 1119 struct fwnode_handle *ep; 1120 struct fwnode_handle *fwnode = dev_fwnode(dev); 1121 struct v4l2_fwnode_endpoint bus_cfg = { 1122 .bus_type = V4L2_MBUS_CSI2_DPHY 1123 }; 1124 u32 mclk; 1125 int ret; 1126 unsigned int i, j; 1127 1128 /* 1129 * Sometimes the fwnode graph is initialized by the bridge driver, 1130 * wait for this. 1131 */ 1132 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1133 if (!ep) 1134 return -EPROBE_DEFER; 1135 1136 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk); 1137 if (ret) { 1138 fwnode_handle_put(ep); 1139 return dev_err_probe(dev, ret, 1140 "reading clock-frequency property\n"); 1141 } 1142 1143 if (mclk != OV2740_MCLK) { 1144 fwnode_handle_put(ep); 1145 return dev_err_probe(dev, -EINVAL, 1146 "external clock %d is not supported\n", 1147 mclk); 1148 } 1149 1150 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1151 fwnode_handle_put(ep); 1152 if (ret) 1153 return dev_err_probe(dev, ret, "parsing endpoint failed\n"); 1154 1155 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) { 1156 ret = dev_err_probe(dev, -EINVAL, 1157 "number of CSI2 data lanes %d is not supported\n", 1158 bus_cfg.bus.mipi_csi2.num_data_lanes); 1159 goto check_hwcfg_error; 1160 } 1161 1162 if (!bus_cfg.nr_of_link_frequencies) { 1163 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n"); 1164 goto check_hwcfg_error; 1165 } 1166 1167 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 1168 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) { 1169 if (link_freq_menu_items[i] == 1170 bus_cfg.link_frequencies[j]) 1171 break; 1172 } 1173 1174 if (j == bus_cfg.nr_of_link_frequencies) 1175 continue; 1176 1177 switch (i) { 1178 case OV2740_LINK_FREQ_360MHZ_INDEX: 1179 ov2740->supported_modes = supported_modes_360mhz; 1180 ov2740->supported_modes_count = 1181 ARRAY_SIZE(supported_modes_360mhz); 1182 break; 1183 case OV2740_LINK_FREQ_180MHZ_INDEX: 1184 ov2740->supported_modes = supported_modes_180mhz; 1185 ov2740->supported_modes_count = 1186 ARRAY_SIZE(supported_modes_180mhz); 1187 break; 1188 } 1189 1190 break; /* Prefer modes from first available link-freq */ 1191 } 1192 1193 if (!ov2740->supported_modes) 1194 ret = dev_err_probe(dev, -EINVAL, 1195 "no supported link frequencies\n"); 1196 1197check_hwcfg_error: 1198 v4l2_fwnode_endpoint_free(&bus_cfg); 1199 1200 return ret; 1201} 1202 1203static void ov2740_remove(struct i2c_client *client) 1204{ 1205 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1206 1207 v4l2_async_unregister_subdev(sd); 1208 media_entity_cleanup(&sd->entity); 1209 v4l2_subdev_cleanup(sd); 1210 v4l2_ctrl_handler_free(sd->ctrl_handler); 1211 pm_runtime_disable(&client->dev); 1212} 1213 1214static int ov2740_nvmem_read(void *priv, unsigned int off, void *val, 1215 size_t count) 1216{ 1217 struct nvm_data *nvm = priv; 1218 struct device *dev = regmap_get_device(nvm->regmap); 1219 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev)); 1220 struct v4l2_subdev_state *sd_state; 1221 int ret = 0; 1222 1223 /* Serialise sensor access */ 1224 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd); 1225 1226 if (nvm->nvm_buffer) { 1227 memcpy(val, nvm->nvm_buffer + off, count); 1228 goto exit; 1229 } 1230 1231 ret = pm_runtime_resume_and_get(dev); 1232 if (ret < 0) { 1233 goto exit; 1234 } 1235 1236 ret = ov2740_load_otp_data(nvm); 1237 if (!ret) 1238 memcpy(val, nvm->nvm_buffer + off, count); 1239 1240 pm_runtime_put(dev); 1241exit: 1242 v4l2_subdev_unlock_state(sd_state); 1243 return ret; 1244} 1245 1246static int ov2740_register_nvmem(struct i2c_client *client, 1247 struct ov2740 *ov2740) 1248{ 1249 struct nvm_data *nvm; 1250 struct regmap_config regmap_config = { }; 1251 struct nvmem_config nvmem_config = { }; 1252 struct regmap *regmap; 1253 struct device *dev = &client->dev; 1254 1255 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL); 1256 if (!nvm) 1257 return -ENOMEM; 1258 1259 regmap_config.val_bits = 8; 1260 regmap_config.reg_bits = 16; 1261 regmap_config.disable_locking = true; 1262 regmap = devm_regmap_init_i2c(client, ®map_config); 1263 if (IS_ERR(regmap)) 1264 return PTR_ERR(regmap); 1265 1266 nvm->regmap = regmap; 1267 1268 nvmem_config.name = dev_name(dev); 1269 nvmem_config.dev = dev; 1270 nvmem_config.read_only = true; 1271 nvmem_config.root_only = true; 1272 nvmem_config.owner = THIS_MODULE; 1273 nvmem_config.compat = true; 1274 nvmem_config.base_dev = dev; 1275 nvmem_config.reg_read = ov2740_nvmem_read; 1276 nvmem_config.reg_write = NULL; 1277 nvmem_config.priv = nvm; 1278 nvmem_config.stride = 1; 1279 nvmem_config.word_size = 1; 1280 nvmem_config.size = CUSTOMER_USE_OTP_SIZE; 1281 1282 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config); 1283 if (IS_ERR(nvm->nvmem)) 1284 return PTR_ERR(nvm->nvmem); 1285 1286 ov2740->nvm = nvm; 1287 return 0; 1288} 1289 1290static int ov2740_suspend(struct device *dev) 1291{ 1292 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1293 struct ov2740 *ov2740 = to_ov2740(sd); 1294 1295 gpiod_set_value_cansleep(ov2740->reset_gpio, 1); 1296 clk_disable_unprepare(ov2740->clk); 1297 return 0; 1298} 1299 1300static int ov2740_resume(struct device *dev) 1301{ 1302 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1303 struct ov2740 *ov2740 = to_ov2740(sd); 1304 int ret; 1305 1306 ret = clk_prepare_enable(ov2740->clk); 1307 if (ret) 1308 return ret; 1309 1310 gpiod_set_value_cansleep(ov2740->reset_gpio, 0); 1311 msleep(20); 1312 1313 return 0; 1314} 1315 1316static int ov2740_probe(struct i2c_client *client) 1317{ 1318 struct device *dev = &client->dev; 1319 struct ov2740 *ov2740; 1320 bool full_power; 1321 int ret; 1322 1323 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL); 1324 if (!ov2740) 1325 return -ENOMEM; 1326 1327 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops); 1328 ov2740->sd.internal_ops = &ov2740_internal_ops; 1329 1330 ret = ov2740_check_hwcfg(dev); 1331 if (ret) 1332 return dev_err_probe(dev, ret, "failed to check HW configuration\n"); 1333 1334 ov2740->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1335 if (IS_ERR(ov2740->reset_gpio)) 1336 return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio), 1337 "failed to get reset GPIO\n"); 1338 1339 ov2740->clk = devm_clk_get_optional(dev, "clk"); 1340 if (IS_ERR(ov2740->clk)) 1341 return dev_err_probe(dev, PTR_ERR(ov2740->clk), 1342 "failed to get clock\n"); 1343 1344 full_power = acpi_dev_state_d0(&client->dev); 1345 if (full_power) { 1346 /* ACPI does not always clear the reset GPIO / enable the clock */ 1347 ret = ov2740_resume(dev); 1348 if (ret) 1349 return dev_err_probe(dev, ret, "failed to power on sensor\n"); 1350 1351 ret = ov2740_identify_module(ov2740); 1352 if (ret) { 1353 dev_err_probe(dev, ret, "failed to find sensor\n"); 1354 goto probe_error_power_off; 1355 } 1356 } 1357 1358 ov2740->cur_mode = &ov2740->supported_modes[0]; 1359 ret = ov2740_init_controls(ov2740); 1360 if (ret) { 1361 dev_err_probe(dev, ret, "failed to init controls\n"); 1362 goto probe_error_v4l2_ctrl_handler_free; 1363 } 1364 1365 ov2740->sd.state_lock = ov2740->ctrl_handler.lock; 1366 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1367 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops; 1368 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1369 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE; 1370 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad); 1371 if (ret) { 1372 dev_err_probe(dev, ret, "failed to init entity pads\n"); 1373 goto probe_error_v4l2_ctrl_handler_free; 1374 } 1375 1376 ret = v4l2_subdev_init_finalize(&ov2740->sd); 1377 if (ret) 1378 goto probe_error_media_entity_cleanup; 1379 1380 /* Set the device's state to active if it's in D0 state. */ 1381 if (full_power) 1382 pm_runtime_set_active(&client->dev); 1383 pm_runtime_enable(&client->dev); 1384 pm_runtime_idle(&client->dev); 1385 1386 ret = v4l2_async_register_subdev_sensor(&ov2740->sd); 1387 if (ret < 0) { 1388 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n"); 1389 goto probe_error_v4l2_subdev_cleanup; 1390 } 1391 1392 ret = ov2740_register_nvmem(client, ov2740); 1393 if (ret) 1394 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret); 1395 1396 return 0; 1397 1398probe_error_v4l2_subdev_cleanup: 1399 v4l2_subdev_cleanup(&ov2740->sd); 1400 1401probe_error_media_entity_cleanup: 1402 media_entity_cleanup(&ov2740->sd.entity); 1403 pm_runtime_disable(&client->dev); 1404 pm_runtime_set_suspended(&client->dev); 1405 1406probe_error_v4l2_ctrl_handler_free: 1407 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler); 1408 1409probe_error_power_off: 1410 if (full_power) 1411 ov2740_suspend(dev); 1412 1413 return ret; 1414} 1415 1416static DEFINE_RUNTIME_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume, 1417 NULL); 1418 1419static const struct acpi_device_id ov2740_acpi_ids[] = { 1420 {"INT3474"}, 1421 {} 1422}; 1423 1424MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids); 1425 1426static struct i2c_driver ov2740_i2c_driver = { 1427 .driver = { 1428 .name = "ov2740", 1429 .acpi_match_table = ov2740_acpi_ids, 1430 .pm = pm_sleep_ptr(&ov2740_pm_ops), 1431 }, 1432 .probe = ov2740_probe, 1433 .remove = ov2740_remove, 1434 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE, 1435}; 1436 1437module_i2c_driver(ov2740_i2c_driver); 1438 1439MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>"); 1440MODULE_AUTHOR("Shawn Tu"); 1441MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>"); 1442MODULE_DESCRIPTION("OmniVision OV2740 sensor driver"); 1443MODULE_LICENSE("GPL v2"); 1444