Searched refs:pix_clk_100hz (Results 26 - 50 of 57) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c289 ((float)timing->pix_clk_100hz / 10.0));
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1702 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);
1706 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
1756 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
1796 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h937 * @pix_clk_100hz: Pipe pixel precision
942 uint32_t pix_clk_100hz; member in struct:dc_crtc_timing
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c614 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
981 m_vid_l *= param->timing.pix_clk_100hz / 10;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c828 int pix_clk_100hz, int bpp, int seg_size_kb)
833 return (int)(soc->dram_clock_change_latency_us * pix_clk_100hz * bpp
826 dcn_get_approx_det_segs_required_for_pstate( struct _vcs_dpi_soc_bounding_box_st *soc, int pix_clk_100hz, int bpp, int seg_size_kb) argument
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c277 pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00;
278 pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total;
H A Ddml2_translation_helper.c602 out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
604 out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;
727 out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c2021 stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz;
2153 pipe->stream->timing.pix_clk_100hz * 100 /
2219 hw_crtc_timing[i].pix_clk_100hz = pclk;
2257 grouped_pipes[i]->stream->timing.pix_clk_100hz =
2316 grouped_pipes[master]->stream->timing.pix_clk_100hz,
2317 grouped_pipes[i]->stream->timing.pix_clk_100hz,
3487 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
3888 params.timing.pix_clk_100hz /= 2;
/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c766 timing.pix_clk_100hz * 100),
980 (stream->timing.pix_clk_100hz / 10)) + 1;
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c1309 unsigned int pix_clk_100hz = 0; local
1323 tg_inst, &pix_clk_100hz);
1329 if (pix_clk_100hz != requested_pix_clk_100hz) {
1796 unsigned int pix_clk_100hz = 0; local
1802 tg_inst, &pix_clk_100hz);
1809 pix_clk_100hz *= 2;
1811 pix_clk_100hz *= 4;
1815 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
2072 context->streams[i]->timing.pix_clk_100hz / 1
[all...]
/linux-master/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h1512 uint32_t pix_clk_100hz; member in struct:dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2::__anon373::__anon374
1537 uint32_t pix_clk_100hz; member in struct:dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2::__anon373::__anon375
4184 uint32_t pix_clk_100hz; member in struct:dmub_cmd_fw_assisted_mclk_switch_pipe_data
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c417 ((float)timing->pix_clk_100hz / 10.0));
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c451 ((float)timing->pix_clk_100hz / 10.0));
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_stream_encoder.c543 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c363 v_freq = (uint64_t)hw_crtc_timing.pix_clk_100hz * 100;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c605 params.timing.pix_clk_100hz /= 2;
/linux-master/drivers/gpu/drm/amd/display/modules/power/
H A Dpower_helpers.c892 vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10);
894 line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing.pix_clk_100hz / 10)) + 1;
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c573 pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
576 refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1357 (stream->timing.pix_clk_100hz*100)/
1381 (stream->timing.pix_clk_100hz)) {
1874 stream->timing.pix_clk_100hz +
2891 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2965 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
3146 pipes[i].stream->timing.pix_clk_100hz;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c444 input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
736 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
912 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1905 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1937 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1943 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
/linux-master/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c799 stream->timing.pix_clk_100hz > 480000;
1927 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2106 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c984 stream->timing.pix_clk_100hz > 480000;
1235 params.timing.pix_clk_100hz /= 2;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c1011 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c949 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *

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