1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27#include "dm_services.h" 28#include "dc.h" 29 30#include "dcn31/dcn31_init.h" 31 32#include "resource.h" 33#include "include/irq_service_interface.h" 34#include "dcn315_resource.h" 35 36#include "dcn20/dcn20_resource.h" 37#include "dcn30/dcn30_resource.h" 38#include "dcn31/dcn31_resource.h" 39 40#include "dcn10/dcn10_ipp.h" 41#include "dcn30/dcn30_hubbub.h" 42#include "dcn31/dcn31_hubbub.h" 43#include "dcn30/dcn30_mpc.h" 44#include "dcn31/dcn31_hubp.h" 45#include "irq/dcn315/irq_service_dcn315.h" 46#include "dcn30/dcn30_dpp.h" 47#include "dcn31/dcn31_optc.h" 48#include "dcn20/dcn20_hwseq.h" 49#include "dcn30/dcn30_hwseq.h" 50#include "dce110/dce110_hwseq.h" 51#include "dcn30/dcn30_opp.h" 52#include "dcn20/dcn20_dsc.h" 53#include "dcn30/dcn30_vpg.h" 54#include "dcn30/dcn30_afmt.h" 55#include "dcn30/dcn30_dio_stream_encoder.h" 56#include "dcn31/dcn31_hpo_dp_stream_encoder.h" 57#include "dcn31/dcn31_hpo_dp_link_encoder.h" 58#include "dcn31/dcn31_apg.h" 59#include "dcn31/dcn31_dio_link_encoder.h" 60#include "dcn31/dcn31_vpg.h" 61#include "dcn31/dcn31_afmt.h" 62#include "dce/dce_clock_source.h" 63#include "dce/dce_audio.h" 64#include "dce/dce_hwseq.h" 65#include "clk_mgr.h" 66#include "virtual/virtual_stream_encoder.h" 67#include "dce110/dce110_resource.h" 68#include "dml/display_mode_vba.h" 69#include "dml/dcn31/dcn31_fpu.h" 70#include "dcn31/dcn31_dccg.h" 71#include "dcn10/dcn10_resource.h" 72#include "dcn31/dcn31_panel_cntl.h" 73 74#include "dcn30/dcn30_dwb.h" 75#include "dcn30/dcn30_mmhubbub.h" 76 77#include "dcn/dcn_3_1_5_offset.h" 78#include "dcn/dcn_3_1_5_sh_mask.h" 79#include "dpcs/dpcs_4_2_2_offset.h" 80#include "dpcs/dpcs_4_2_2_sh_mask.h" 81 82#define NBIO_BASE__INST0_SEG0 0x00000000 83#define NBIO_BASE__INST0_SEG1 0x00000014 84#define NBIO_BASE__INST0_SEG2 0x00000D20 85#define NBIO_BASE__INST0_SEG3 0x00010400 86#define NBIO_BASE__INST0_SEG4 0x0241B000 87#define NBIO_BASE__INST0_SEG5 0x04040000 88 89#define DPCS_BASE__INST0_SEG0 0x00000012 90#define DPCS_BASE__INST0_SEG1 0x000000C0 91#define DPCS_BASE__INST0_SEG2 0x000034C0 92#define DPCS_BASE__INST0_SEG3 0x00009000 93#define DPCS_BASE__INST0_SEG4 0x02403C00 94#define DPCS_BASE__INST0_SEG5 0 95 96#define DCN_BASE__INST0_SEG0 0x00000012 97#define DCN_BASE__INST0_SEG1 0x000000C0 98#define DCN_BASE__INST0_SEG2 0x000034C0 99#define DCN_BASE__INST0_SEG3 0x00009000 100#define DCN_BASE__INST0_SEG4 0x02403C00 101#define DCN_BASE__INST0_SEG5 0 102 103#define regBIF_BX_PF2_RSMU_INDEX 0x0000 104#define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1 105#define regBIF_BX_PF2_RSMU_DATA 0x0001 106#define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1 107#define regBIF_BX2_BIOS_SCRATCH_6 0x003e 108#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1 109#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 110#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL 111#define regBIF_BX2_BIOS_SCRATCH_2 0x003a 112#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1 113#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 114#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL 115#define regBIF_BX2_BIOS_SCRATCH_3 0x003b 116#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1 117#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 118#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL 119 120#define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 121#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 122#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 123#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 124 125#include "reg_helper.h" 126#include "dce/dmub_abm.h" 127#include "dce/dmub_psr.h" 128#include "dce/dce_aux.h" 129#include "dce/dce_i2c.h" 130 131#include "dml/dcn30/display_mode_vba_30.h" 132#include "vm_helper.h" 133#include "dcn20/dcn20_vmid.h" 134 135#include "link_enc_cfg.h" 136 137#define DCN3_15_MAX_DET_SIZE 384 138#define DCN3_15_CRB_SEGMENT_SIZE_KB 64 139#define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB) 140/* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */ 141#define MIN_RESERVED_DET_SEGS 3 142 143enum dcn31_clk_src_array_id { 144 DCN31_CLK_SRC_PLL0, 145 DCN31_CLK_SRC_PLL1, 146 DCN31_CLK_SRC_PLL2, 147 DCN31_CLK_SRC_PLL3, 148 DCN31_CLK_SRC_PLL4, 149 DCN30_CLK_SRC_TOTAL 150}; 151 152/* begin ********************* 153 * macros to expend register list macro defined in HW object header file 154 */ 155 156/* DCN */ 157#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 158 159#define BASE(seg) BASE_INNER(seg) 160 161#define SR(reg_name)\ 162 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 163 reg ## reg_name 164 165#define SRI(reg_name, block, id)\ 166 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 167 reg ## block ## id ## _ ## reg_name 168 169#define SRI2(reg_name, block, id)\ 170 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 171 reg ## reg_name 172 173#define SRIR(var_name, reg_name, block, id)\ 174 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 reg ## block ## id ## _ ## reg_name 176 177#define SRII(reg_name, block, id)\ 178 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 179 reg ## block ## id ## _ ## reg_name 180 181#define SRII_MPC_RMU(reg_name, block, id)\ 182 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 183 reg ## block ## id ## _ ## reg_name 184 185#define SRII_DWB(reg_name, temp_name, block, id)\ 186 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 187 reg ## block ## id ## _ ## temp_name 188 189#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 190 .field_name = reg_name ## __ ## field_name ## post_fix 191 192#define DCCG_SRII(reg_name, block, id)\ 193 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 194 reg ## block ## id ## _ ## reg_name 195 196#define VUPDATE_SRII(reg_name, block, id)\ 197 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 198 reg ## reg_name ## _ ## block ## id 199 200/* NBIO */ 201#define NBIO_BASE_INNER(seg) \ 202 NBIO_BASE__INST0_SEG ## seg 203 204#define NBIO_BASE(seg) \ 205 NBIO_BASE_INNER(seg) 206 207#define NBIO_SR(reg_name)\ 208 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 209 regBIF_BX2_ ## reg_name 210 211static const struct bios_registers bios_regs = { 212 NBIO_SR(BIOS_SCRATCH_3), 213 NBIO_SR(BIOS_SCRATCH_6) 214}; 215 216#define clk_src_regs(index, pllid)\ 217[index] = {\ 218 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 219} 220 221static const struct dce110_clk_src_regs clk_src_regs[] = { 222 clk_src_regs(0, A), 223 clk_src_regs(1, B), 224 clk_src_regs(2, C), 225 clk_src_regs(3, D), 226 clk_src_regs(4, E) 227}; 228 229static const struct dce110_clk_src_shift cs_shift = { 230 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 231}; 232 233static const struct dce110_clk_src_mask cs_mask = { 234 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 235}; 236 237#define abm_regs(id)\ 238[id] = {\ 239 ABM_DCN302_REG_LIST(id)\ 240} 241 242static const struct dce_abm_registers abm_regs[] = { 243 abm_regs(0), 244 abm_regs(1), 245 abm_regs(2), 246 abm_regs(3), 247}; 248 249static const struct dce_abm_shift abm_shift = { 250 ABM_MASK_SH_LIST_DCN30(__SHIFT) 251}; 252 253static const struct dce_abm_mask abm_mask = { 254 ABM_MASK_SH_LIST_DCN30(_MASK) 255}; 256 257#define audio_regs(id)\ 258[id] = {\ 259 AUD_COMMON_REG_LIST(id)\ 260} 261 262static const struct dce_audio_registers audio_regs[] = { 263 audio_regs(0), 264 audio_regs(1), 265 audio_regs(2), 266 audio_regs(3), 267 audio_regs(4), 268 audio_regs(5), 269 audio_regs(6) 270}; 271 272#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 273 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 274 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 275 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 276 277static const struct dce_audio_shift audio_shift = { 278 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 279}; 280 281static const struct dce_audio_mask audio_mask = { 282 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 283}; 284 285#define vpg_regs(id)\ 286[id] = {\ 287 VPG_DCN31_REG_LIST(id)\ 288} 289 290static const struct dcn31_vpg_registers vpg_regs[] = { 291 vpg_regs(0), 292 vpg_regs(1), 293 vpg_regs(2), 294 vpg_regs(3), 295 vpg_regs(4), 296 vpg_regs(5), 297 vpg_regs(6), 298 vpg_regs(7), 299 vpg_regs(8), 300 vpg_regs(9), 301}; 302 303static const struct dcn31_vpg_shift vpg_shift = { 304 DCN31_VPG_MASK_SH_LIST(__SHIFT) 305}; 306 307static const struct dcn31_vpg_mask vpg_mask = { 308 DCN31_VPG_MASK_SH_LIST(_MASK) 309}; 310 311#define afmt_regs(id)\ 312[id] = {\ 313 AFMT_DCN31_REG_LIST(id)\ 314} 315 316static const struct dcn31_afmt_registers afmt_regs[] = { 317 afmt_regs(0), 318 afmt_regs(1), 319 afmt_regs(2), 320 afmt_regs(3), 321 afmt_regs(4), 322 afmt_regs(5) 323}; 324 325static const struct dcn31_afmt_shift afmt_shift = { 326 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 327}; 328 329static const struct dcn31_afmt_mask afmt_mask = { 330 DCN31_AFMT_MASK_SH_LIST(_MASK) 331}; 332 333#define apg_regs(id)\ 334[id] = {\ 335 APG_DCN31_REG_LIST(id)\ 336} 337 338static const struct dcn31_apg_registers apg_regs[] = { 339 apg_regs(0), 340 apg_regs(1), 341 apg_regs(2), 342 apg_regs(3) 343}; 344 345static const struct dcn31_apg_shift apg_shift = { 346 DCN31_APG_MASK_SH_LIST(__SHIFT) 347}; 348 349static const struct dcn31_apg_mask apg_mask = { 350 DCN31_APG_MASK_SH_LIST(_MASK) 351}; 352 353#define stream_enc_regs(id)\ 354[id] = {\ 355 SE_DCN3_REG_LIST(id)\ 356} 357 358static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 359 stream_enc_regs(0), 360 stream_enc_regs(1), 361 stream_enc_regs(2), 362 stream_enc_regs(3), 363 stream_enc_regs(4) 364}; 365 366static const struct dcn10_stream_encoder_shift se_shift = { 367 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 368}; 369 370static const struct dcn10_stream_encoder_mask se_mask = { 371 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 372}; 373 374 375#define aux_regs(id)\ 376[id] = {\ 377 DCN2_AUX_REG_LIST(id)\ 378} 379 380static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 381 aux_regs(0), 382 aux_regs(1), 383 aux_regs(2), 384 aux_regs(3), 385 aux_regs(4) 386}; 387 388#define hpd_regs(id)\ 389[id] = {\ 390 HPD_REG_LIST(id)\ 391} 392 393static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 394 hpd_regs(0), 395 hpd_regs(1), 396 hpd_regs(2), 397 hpd_regs(3), 398 hpd_regs(4) 399}; 400 401#define link_regs(id, phyid)\ 402[id] = {\ 403 LE_DCN31_REG_LIST(id), \ 404 UNIPHY_DCN2_REG_LIST(phyid), \ 405 DPCS_DCN31_REG_LIST(id), \ 406} 407 408static const struct dce110_aux_registers_shift aux_shift = { 409 DCN_AUX_MASK_SH_LIST(__SHIFT) 410}; 411 412static const struct dce110_aux_registers_mask aux_mask = { 413 DCN_AUX_MASK_SH_LIST(_MASK) 414}; 415 416static const struct dcn10_link_enc_registers link_enc_regs[] = { 417 link_regs(0, A), 418 link_regs(1, B), 419 link_regs(2, C), 420 link_regs(3, D), 421 link_regs(4, E) 422}; 423 424static const struct dcn10_link_enc_shift le_shift = { 425 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 426 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 427}; 428 429static const struct dcn10_link_enc_mask le_mask = { 430 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 431 DPCS_DCN31_MASK_SH_LIST(_MASK) 432}; 433 434#define hpo_dp_stream_encoder_reg_list(id)\ 435[id] = {\ 436 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 437} 438 439static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 440 hpo_dp_stream_encoder_reg_list(0), 441 hpo_dp_stream_encoder_reg_list(1), 442 hpo_dp_stream_encoder_reg_list(2), 443 hpo_dp_stream_encoder_reg_list(3), 444}; 445 446static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 447 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 448}; 449 450static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 451 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 452}; 453 454 455#define hpo_dp_link_encoder_reg_list(id)\ 456[id] = {\ 457 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 458 DCN3_1_RDPCSTX_REG_LIST(0),\ 459 DCN3_1_RDPCSTX_REG_LIST(1),\ 460 DCN3_1_RDPCSTX_REG_LIST(2),\ 461 DCN3_1_RDPCSTX_REG_LIST(3),\ 462 DCN3_1_RDPCSTX_REG_LIST(4)\ 463} 464 465static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 466 hpo_dp_link_encoder_reg_list(0), 467 hpo_dp_link_encoder_reg_list(1), 468}; 469 470static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 471 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 472}; 473 474static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 475 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 476}; 477 478#define dpp_regs(id)\ 479[id] = {\ 480 DPP_REG_LIST_DCN30(id),\ 481} 482 483static const struct dcn3_dpp_registers dpp_regs[] = { 484 dpp_regs(0), 485 dpp_regs(1), 486 dpp_regs(2), 487 dpp_regs(3) 488}; 489 490static const struct dcn3_dpp_shift tf_shift = { 491 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 492}; 493 494static const struct dcn3_dpp_mask tf_mask = { 495 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 496}; 497 498#define opp_regs(id)\ 499[id] = {\ 500 OPP_REG_LIST_DCN30(id),\ 501} 502 503static const struct dcn20_opp_registers opp_regs[] = { 504 opp_regs(0), 505 opp_regs(1), 506 opp_regs(2), 507 opp_regs(3) 508}; 509 510static const struct dcn20_opp_shift opp_shift = { 511 OPP_MASK_SH_LIST_DCN20(__SHIFT) 512}; 513 514static const struct dcn20_opp_mask opp_mask = { 515 OPP_MASK_SH_LIST_DCN20(_MASK) 516}; 517 518#define aux_engine_regs(id)\ 519[id] = {\ 520 AUX_COMMON_REG_LIST0(id), \ 521 .AUXN_IMPCAL = 0, \ 522 .AUXP_IMPCAL = 0, \ 523 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 524} 525 526static const struct dce110_aux_registers aux_engine_regs[] = { 527 aux_engine_regs(0), 528 aux_engine_regs(1), 529 aux_engine_regs(2), 530 aux_engine_regs(3), 531 aux_engine_regs(4) 532}; 533 534#define dwbc_regs_dcn3(id)\ 535[id] = {\ 536 DWBC_COMMON_REG_LIST_DCN30(id),\ 537} 538 539static const struct dcn30_dwbc_registers dwbc30_regs[] = { 540 dwbc_regs_dcn3(0), 541}; 542 543static const struct dcn30_dwbc_shift dwbc30_shift = { 544 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 545}; 546 547static const struct dcn30_dwbc_mask dwbc30_mask = { 548 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 549}; 550 551#define mcif_wb_regs_dcn3(id)\ 552[id] = {\ 553 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 554} 555 556static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 557 mcif_wb_regs_dcn3(0) 558}; 559 560static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 561 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 562}; 563 564static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 565 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 566}; 567 568#define dsc_regsDCN20(id)\ 569[id] = {\ 570 DSC_REG_LIST_DCN20(id)\ 571} 572 573static const struct dcn20_dsc_registers dsc_regs[] = { 574 dsc_regsDCN20(0), 575 dsc_regsDCN20(1), 576 dsc_regsDCN20(2) 577}; 578 579static const struct dcn20_dsc_shift dsc_shift = { 580 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 581}; 582 583static const struct dcn20_dsc_mask dsc_mask = { 584 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 585}; 586 587static const struct dcn30_mpc_registers mpc_regs = { 588 MPC_REG_LIST_DCN3_0(0), 589 MPC_REG_LIST_DCN3_0(1), 590 MPC_REG_LIST_DCN3_0(2), 591 MPC_REG_LIST_DCN3_0(3), 592 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 593 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 594 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 595 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 596 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 597}; 598 599static const struct dcn30_mpc_shift mpc_shift = { 600 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 601}; 602 603static const struct dcn30_mpc_mask mpc_mask = { 604 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 605}; 606 607#define optc_regs(id)\ 608[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 609 610static const struct dcn_optc_registers optc_regs[] = { 611 optc_regs(0), 612 optc_regs(1), 613 optc_regs(2), 614 optc_regs(3) 615}; 616 617static const struct dcn_optc_shift optc_shift = { 618 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 619}; 620 621static const struct dcn_optc_mask optc_mask = { 622 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 623}; 624 625#define hubp_regs(id)\ 626[id] = {\ 627 HUBP_REG_LIST_DCN30(id)\ 628} 629 630static const struct dcn_hubp2_registers hubp_regs[] = { 631 hubp_regs(0), 632 hubp_regs(1), 633 hubp_regs(2), 634 hubp_regs(3) 635}; 636 637 638static const struct dcn_hubp2_shift hubp_shift = { 639 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 640}; 641 642static const struct dcn_hubp2_mask hubp_mask = { 643 HUBP_MASK_SH_LIST_DCN31(_MASK) 644}; 645static const struct dcn_hubbub_registers hubbub_reg = { 646 HUBBUB_REG_LIST_DCN31(0) 647}; 648 649static const struct dcn_hubbub_shift hubbub_shift = { 650 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 651}; 652 653static const struct dcn_hubbub_mask hubbub_mask = { 654 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 655}; 656 657static const struct dccg_registers dccg_regs = { 658 DCCG_REG_LIST_DCN31() 659}; 660 661static const struct dccg_shift dccg_shift = { 662 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 663}; 664 665static const struct dccg_mask dccg_mask = { 666 DCCG_MASK_SH_LIST_DCN31(_MASK) 667}; 668 669 670#define SRII2(reg_name_pre, reg_name_post, id)\ 671 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 672 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 673 reg ## reg_name_pre ## id ## _ ## reg_name_post 674 675 676#define HWSEQ_DCN31_REG_LIST()\ 677 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 678 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 679 SR(DIO_MEM_PWR_CTRL), \ 680 SR(ODM_MEM_PWR_CTRL3), \ 681 SR(DMU_MEM_PWR_CNTL), \ 682 SR(MMHUBBUB_MEM_PWR_CNTL), \ 683 SR(DCCG_GATE_DISABLE_CNTL), \ 684 SR(DCCG_GATE_DISABLE_CNTL2), \ 685 SR(DCFCLK_CNTL),\ 686 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 687 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 688 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 689 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 690 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 691 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 695 SR(MICROSECOND_TIME_BASE_DIV), \ 696 SR(MILLISECOND_TIME_BASE_DIV), \ 697 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 698 SR(RBBMIF_TIMEOUT_DIS), \ 699 SR(RBBMIF_TIMEOUT_DIS_2), \ 700 SR(DCHUBBUB_CRC_CTRL), \ 701 SR(DPP_TOP0_DPP_CRC_CTRL), \ 702 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 703 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 704 SR(MPC_CRC_CTRL), \ 705 SR(MPC_CRC_RESULT_GB), \ 706 SR(MPC_CRC_RESULT_C), \ 707 SR(MPC_CRC_RESULT_AR), \ 708 SR(DOMAIN0_PG_CONFIG), \ 709 SR(DOMAIN1_PG_CONFIG), \ 710 SR(DOMAIN2_PG_CONFIG), \ 711 SR(DOMAIN3_PG_CONFIG), \ 712 SR(DOMAIN16_PG_CONFIG), \ 713 SR(DOMAIN17_PG_CONFIG), \ 714 SR(DOMAIN18_PG_CONFIG), \ 715 SR(DOMAIN0_PG_STATUS), \ 716 SR(DOMAIN1_PG_STATUS), \ 717 SR(DOMAIN2_PG_STATUS), \ 718 SR(DOMAIN3_PG_STATUS), \ 719 SR(DOMAIN16_PG_STATUS), \ 720 SR(DOMAIN17_PG_STATUS), \ 721 SR(DOMAIN18_PG_STATUS), \ 722 SR(D1VGA_CONTROL), \ 723 SR(D2VGA_CONTROL), \ 724 SR(D3VGA_CONTROL), \ 725 SR(D4VGA_CONTROL), \ 726 SR(D5VGA_CONTROL), \ 727 SR(D6VGA_CONTROL), \ 728 SR(DC_IP_REQUEST_CNTL), \ 729 SR(AZALIA_AUDIO_DTO), \ 730 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 731 SR(HPO_TOP_HW_CONTROL) 732 733static const struct dce_hwseq_registers hwseq_reg = { 734 HWSEQ_DCN31_REG_LIST() 735}; 736 737#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 738 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 739 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 740 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 741 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 742 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 743 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 744 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 745 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 746 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 747 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 748 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 749 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 752 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 753 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 754 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 755 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 756 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 757 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 762 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 763 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 764 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 765 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 766 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 767 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 768 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 769 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 770 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 771 772static const struct dce_hwseq_shift hwseq_shift = { 773 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 774}; 775 776static const struct dce_hwseq_mask hwseq_mask = { 777 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 778}; 779#define vmid_regs(id)\ 780[id] = {\ 781 DCN20_VMID_REG_LIST(id)\ 782} 783 784static const struct dcn_vmid_registers vmid_regs[] = { 785 vmid_regs(0), 786 vmid_regs(1), 787 vmid_regs(2), 788 vmid_regs(3), 789 vmid_regs(4), 790 vmid_regs(5), 791 vmid_regs(6), 792 vmid_regs(7), 793 vmid_regs(8), 794 vmid_regs(9), 795 vmid_regs(10), 796 vmid_regs(11), 797 vmid_regs(12), 798 vmid_regs(13), 799 vmid_regs(14), 800 vmid_regs(15) 801}; 802 803static const struct dcn20_vmid_shift vmid_shifts = { 804 DCN20_VMID_MASK_SH_LIST(__SHIFT) 805}; 806 807static const struct dcn20_vmid_mask vmid_masks = { 808 DCN20_VMID_MASK_SH_LIST(_MASK) 809}; 810 811static const struct resource_caps res_cap_dcn31 = { 812 .num_timing_generator = 4, 813 .num_opp = 4, 814 .num_video_plane = 4, 815 .num_audio = 5, 816 .num_stream_encoder = 5, 817 .num_dig_link_enc = 5, 818 .num_hpo_dp_stream_encoder = 4, 819 .num_hpo_dp_link_encoder = 2, 820 .num_pll = 5, 821 .num_dwb = 1, 822 .num_ddc = 5, 823 .num_vmid = 16, 824 .num_mpc_3dlut = 2, 825 .num_dsc = 3, 826}; 827 828static const struct dc_plane_cap plane_cap = { 829 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 830 .per_pixel_alpha = true, 831 832 .pixel_format_support = { 833 .argb8888 = true, 834 .nv12 = true, 835 .fp16 = true, 836 .p010 = true, 837 .ayuv = false, 838 }, 839 840 .max_upscale_factor = { 841 .argb8888 = 16000, 842 .nv12 = 16000, 843 .fp16 = 16000 844 }, 845 846 // 6:1 downscaling ratio: 1000/6 = 166.666 847 .max_downscale_factor = { 848 .argb8888 = 167, 849 .nv12 = 167, 850 .fp16 = 167 851 }, 852 64, 853 64 854}; 855 856static const struct dc_debug_options debug_defaults_drv = { 857 .disable_z10 = true, /*hw not support it*/ 858 .disable_dmcu = true, 859 .force_abm_enable = false, 860 .timing_trace = false, 861 .clock_trace = true, 862 .disable_pplib_clock_request = false, 863 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 864 .force_single_disp_pipe_split = false, 865 .disable_dcc = DCC_ENABLE, 866 .vsr_support = true, 867 .performance_trace = false, 868 .max_downscale_src_width = 4096,/*upto true 4k*/ 869 .disable_pplib_wm_range = false, 870 .scl_reset_length10 = true, 871 .sanity_checks = false, 872 .underflow_assert_delay_us = 0xFFFFFFFF, 873 .dwb_fi_phase = -1, // -1 = disable, 874 .dmub_command_table = true, 875 .pstate_enabled = true, 876 .use_max_lb = true, 877 .enable_mem_low_power = { 878 .bits = { 879 .vga = true, 880 .i2c = true, 881 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 882 .dscl = true, 883 .cm = true, 884 .mpc = true, 885 .optc = true, 886 .vpg = true, 887 .afmt = true, 888 } 889 }, 890 .enable_legacy_fast_update = true, 891 .psr_power_use_phy_fsm = 0, 892 .using_dml2 = false, 893}; 894 895static const struct dc_panel_config panel_config_defaults = { 896 .psr = { 897 .disable_psr = false, 898 .disallow_psrsu = false, 899 .disallow_replay = false, 900 }, 901 .ilr = { 902 .optimize_edp_link_rate = true, 903 }, 904}; 905 906static void dcn31_dpp_destroy(struct dpp **dpp) 907{ 908 kfree(TO_DCN20_DPP(*dpp)); 909 *dpp = NULL; 910} 911 912static struct dpp *dcn31_dpp_create( 913 struct dc_context *ctx, 914 uint32_t inst) 915{ 916 struct dcn3_dpp *dpp = 917 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 918 919 if (!dpp) 920 return NULL; 921 922 if (dpp3_construct(dpp, ctx, inst, 923 &dpp_regs[inst], &tf_shift, &tf_mask)) 924 return &dpp->base; 925 926 BREAK_TO_DEBUGGER(); 927 kfree(dpp); 928 return NULL; 929} 930 931static struct output_pixel_processor *dcn31_opp_create( 932 struct dc_context *ctx, uint32_t inst) 933{ 934 struct dcn20_opp *opp = 935 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 936 937 if (!opp) { 938 BREAK_TO_DEBUGGER(); 939 return NULL; 940 } 941 942 dcn20_opp_construct(opp, ctx, inst, 943 &opp_regs[inst], &opp_shift, &opp_mask); 944 return &opp->base; 945} 946 947static struct dce_aux *dcn31_aux_engine_create( 948 struct dc_context *ctx, 949 uint32_t inst) 950{ 951 struct aux_engine_dce110 *aux_engine = 952 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 953 954 if (!aux_engine) 955 return NULL; 956 957 dce110_aux_engine_construct(aux_engine, ctx, inst, 958 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 959 &aux_engine_regs[inst], 960 &aux_mask, 961 &aux_shift, 962 ctx->dc->caps.extended_aux_timeout_support); 963 964 return &aux_engine->base; 965} 966#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 967 968static const struct dce_i2c_registers i2c_hw_regs[] = { 969 i2c_inst_regs(1), 970 i2c_inst_regs(2), 971 i2c_inst_regs(3), 972 i2c_inst_regs(4), 973 i2c_inst_regs(5), 974}; 975 976static const struct dce_i2c_shift i2c_shifts = { 977 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 978}; 979 980static const struct dce_i2c_mask i2c_masks = { 981 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 982}; 983 984static struct dce_i2c_hw *dcn31_i2c_hw_create( 985 struct dc_context *ctx, 986 uint32_t inst) 987{ 988 struct dce_i2c_hw *dce_i2c_hw = 989 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 990 991 if (!dce_i2c_hw) 992 return NULL; 993 994 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 995 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 996 997 return dce_i2c_hw; 998} 999static struct mpc *dcn31_mpc_create( 1000 struct dc_context *ctx, 1001 int num_mpcc, 1002 int num_rmu) 1003{ 1004 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1005 GFP_KERNEL); 1006 1007 if (!mpc30) 1008 return NULL; 1009 1010 dcn30_mpc_construct(mpc30, ctx, 1011 &mpc_regs, 1012 &mpc_shift, 1013 &mpc_mask, 1014 num_mpcc, 1015 num_rmu); 1016 1017 return &mpc30->base; 1018} 1019 1020static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1021{ 1022 int i; 1023 1024 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1025 GFP_KERNEL); 1026 1027 if (!hubbub3) 1028 return NULL; 1029 1030 hubbub31_construct(hubbub3, ctx, 1031 &hubbub_reg, 1032 &hubbub_shift, 1033 &hubbub_mask, 1034 dcn3_15_ip.det_buffer_size_kbytes, 1035 dcn3_15_ip.pixel_chunk_size_kbytes, 1036 dcn3_15_ip.config_return_buffer_size_in_kbytes); 1037 1038 1039 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1040 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1041 1042 vmid->ctx = ctx; 1043 1044 vmid->regs = &vmid_regs[i]; 1045 vmid->shifts = &vmid_shifts; 1046 vmid->masks = &vmid_masks; 1047 } 1048 1049 return &hubbub3->base; 1050} 1051 1052static struct timing_generator *dcn31_timing_generator_create( 1053 struct dc_context *ctx, 1054 uint32_t instance) 1055{ 1056 struct optc *tgn10 = 1057 kzalloc(sizeof(struct optc), GFP_KERNEL); 1058 1059 if (!tgn10) 1060 return NULL; 1061 1062 tgn10->base.inst = instance; 1063 tgn10->base.ctx = ctx; 1064 1065 tgn10->tg_regs = &optc_regs[instance]; 1066 tgn10->tg_shift = &optc_shift; 1067 tgn10->tg_mask = &optc_mask; 1068 1069 dcn31_timing_generator_init(tgn10); 1070 1071 return &tgn10->base; 1072} 1073 1074static const struct encoder_feature_support link_enc_feature = { 1075 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1076 .max_hdmi_pixel_clock = 600000, 1077 .hdmi_ycbcr420_supported = true, 1078 .dp_ycbcr420_supported = true, 1079 .fec_supported = true, 1080 .flags.bits.IS_HBR2_CAPABLE = true, 1081 .flags.bits.IS_HBR3_CAPABLE = true, 1082 .flags.bits.IS_TPS3_CAPABLE = true, 1083 .flags.bits.IS_TPS4_CAPABLE = true 1084}; 1085 1086static struct link_encoder *dcn31_link_encoder_create( 1087 struct dc_context *ctx, 1088 const struct encoder_init_data *enc_init_data) 1089{ 1090 struct dcn20_link_encoder *enc20 = 1091 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1092 1093 if (!enc20) 1094 return NULL; 1095 1096 dcn31_link_encoder_construct(enc20, 1097 enc_init_data, 1098 &link_enc_feature, 1099 &link_enc_regs[enc_init_data->transmitter], 1100 &link_enc_aux_regs[enc_init_data->channel - 1], 1101 &link_enc_hpd_regs[enc_init_data->hpd_source], 1102 &le_shift, 1103 &le_mask); 1104 1105 return &enc20->enc10.base; 1106} 1107 1108/* Create a minimal link encoder object not associated with a particular 1109 * physical connector. 1110 * resource_funcs.link_enc_create_minimal 1111 */ 1112static struct link_encoder *dcn31_link_enc_create_minimal( 1113 struct dc_context *ctx, enum engine_id eng_id) 1114{ 1115 struct dcn20_link_encoder *enc20; 1116 1117 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1118 return NULL; 1119 1120 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1121 if (!enc20) 1122 return NULL; 1123 1124 dcn31_link_encoder_construct_minimal( 1125 enc20, 1126 ctx, 1127 &link_enc_feature, 1128 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1129 eng_id); 1130 1131 return &enc20->enc10.base; 1132} 1133 1134static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1135{ 1136 struct dcn31_panel_cntl *panel_cntl = 1137 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1138 1139 if (!panel_cntl) 1140 return NULL; 1141 1142 dcn31_panel_cntl_construct(panel_cntl, init_data); 1143 1144 return &panel_cntl->base; 1145} 1146 1147static void read_dce_straps( 1148 struct dc_context *ctx, 1149 struct resource_straps *straps) 1150{ 1151 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1152 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1153 1154} 1155 1156static struct audio *dcn31_create_audio( 1157 struct dc_context *ctx, unsigned int inst) 1158{ 1159 return dce_audio_create(ctx, inst, 1160 &audio_regs[inst], &audio_shift, &audio_mask); 1161} 1162 1163static struct vpg *dcn31_vpg_create( 1164 struct dc_context *ctx, 1165 uint32_t inst) 1166{ 1167 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1168 1169 if (!vpg31) 1170 return NULL; 1171 1172 vpg31_construct(vpg31, ctx, inst, 1173 &vpg_regs[inst], 1174 &vpg_shift, 1175 &vpg_mask); 1176 1177 return &vpg31->base; 1178} 1179 1180static struct afmt *dcn31_afmt_create( 1181 struct dc_context *ctx, 1182 uint32_t inst) 1183{ 1184 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1185 1186 if (!afmt31) 1187 return NULL; 1188 1189 afmt31_construct(afmt31, ctx, inst, 1190 &afmt_regs[inst], 1191 &afmt_shift, 1192 &afmt_mask); 1193 1194 // Light sleep by default, no need to power down here 1195 1196 return &afmt31->base; 1197} 1198 1199static struct apg *dcn31_apg_create( 1200 struct dc_context *ctx, 1201 uint32_t inst) 1202{ 1203 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1204 1205 if (!apg31) 1206 return NULL; 1207 1208 apg31_construct(apg31, ctx, inst, 1209 &apg_regs[inst], 1210 &apg_shift, 1211 &apg_mask); 1212 1213 return &apg31->base; 1214} 1215 1216static struct stream_encoder *dcn315_stream_encoder_create( 1217 enum engine_id eng_id, 1218 struct dc_context *ctx) 1219{ 1220 struct dcn10_stream_encoder *enc1; 1221 struct vpg *vpg; 1222 struct afmt *afmt; 1223 int vpg_inst; 1224 int afmt_inst; 1225 1226 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ 1227 1228 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1229 if (eng_id <= ENGINE_ID_DIGF) { 1230 vpg_inst = eng_id; 1231 afmt_inst = eng_id; 1232 } else 1233 return NULL; 1234 1235 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1236 vpg = dcn31_vpg_create(ctx, vpg_inst); 1237 afmt = dcn31_afmt_create(ctx, afmt_inst); 1238 1239 if (!enc1 || !vpg || !afmt) { 1240 kfree(enc1); 1241 kfree(vpg); 1242 kfree(afmt); 1243 return NULL; 1244 } 1245 1246 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1247 eng_id, vpg, afmt, 1248 &stream_enc_regs[eng_id], 1249 &se_shift, &se_mask); 1250 1251 return &enc1->base; 1252} 1253 1254static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1255 enum engine_id eng_id, 1256 struct dc_context *ctx) 1257{ 1258 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1259 struct vpg *vpg; 1260 struct apg *apg; 1261 uint32_t hpo_dp_inst; 1262 uint32_t vpg_inst; 1263 uint32_t apg_inst; 1264 1265 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1266 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1267 1268 /* Mapping of VPG register blocks to HPO DP block instance: 1269 * VPG[6] -> HPO_DP[0] 1270 * VPG[7] -> HPO_DP[1] 1271 * VPG[8] -> HPO_DP[2] 1272 * VPG[9] -> HPO_DP[3] 1273 */ 1274 vpg_inst = hpo_dp_inst + 6; 1275 1276 /* Mapping of APG register blocks to HPO DP block instance: 1277 * APG[0] -> HPO_DP[0] 1278 * APG[1] -> HPO_DP[1] 1279 * APG[2] -> HPO_DP[2] 1280 * APG[3] -> HPO_DP[3] 1281 */ 1282 apg_inst = hpo_dp_inst; 1283 1284 /* allocate HPO stream encoder and create VPG sub-block */ 1285 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1286 vpg = dcn31_vpg_create(ctx, vpg_inst); 1287 apg = dcn31_apg_create(ctx, apg_inst); 1288 1289 if (!hpo_dp_enc31 || !vpg || !apg) { 1290 kfree(hpo_dp_enc31); 1291 kfree(vpg); 1292 kfree(apg); 1293 return NULL; 1294 } 1295 1296 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1297 hpo_dp_inst, eng_id, vpg, apg, 1298 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1299 &hpo_dp_se_shift, &hpo_dp_se_mask); 1300 1301 return &hpo_dp_enc31->base; 1302} 1303 1304static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1305 uint8_t inst, 1306 struct dc_context *ctx) 1307{ 1308 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1309 1310 /* allocate HPO link encoder */ 1311 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1312 if (!hpo_dp_enc31) 1313 return NULL; /* out of memory */ 1314 1315 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1316 &hpo_dp_link_enc_regs[inst], 1317 &hpo_dp_le_shift, &hpo_dp_le_mask); 1318 1319 return &hpo_dp_enc31->base; 1320} 1321 1322static struct dce_hwseq *dcn31_hwseq_create( 1323 struct dc_context *ctx) 1324{ 1325 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1326 1327 if (hws) { 1328 hws->ctx = ctx; 1329 hws->regs = &hwseq_reg; 1330 hws->shifts = &hwseq_shift; 1331 hws->masks = &hwseq_mask; 1332 } 1333 return hws; 1334} 1335static const struct resource_create_funcs res_create_funcs = { 1336 .read_dce_straps = read_dce_straps, 1337 .create_audio = dcn31_create_audio, 1338 .create_stream_encoder = dcn315_stream_encoder_create, 1339 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1340 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1341 .create_hwseq = dcn31_hwseq_create, 1342}; 1343 1344static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) 1345{ 1346 unsigned int i; 1347 1348 for (i = 0; i < pool->base.stream_enc_count; i++) { 1349 if (pool->base.stream_enc[i] != NULL) { 1350 if (pool->base.stream_enc[i]->vpg != NULL) { 1351 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1352 pool->base.stream_enc[i]->vpg = NULL; 1353 } 1354 if (pool->base.stream_enc[i]->afmt != NULL) { 1355 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1356 pool->base.stream_enc[i]->afmt = NULL; 1357 } 1358 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1359 pool->base.stream_enc[i] = NULL; 1360 } 1361 } 1362 1363 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1364 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1365 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1366 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1367 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1368 } 1369 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1370 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1371 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1372 } 1373 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1374 pool->base.hpo_dp_stream_enc[i] = NULL; 1375 } 1376 } 1377 1378 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1379 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1380 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1381 pool->base.hpo_dp_link_enc[i] = NULL; 1382 } 1383 } 1384 1385 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1386 if (pool->base.dscs[i] != NULL) 1387 dcn20_dsc_destroy(&pool->base.dscs[i]); 1388 } 1389 1390 if (pool->base.mpc != NULL) { 1391 kfree(TO_DCN20_MPC(pool->base.mpc)); 1392 pool->base.mpc = NULL; 1393 } 1394 if (pool->base.hubbub != NULL) { 1395 kfree(pool->base.hubbub); 1396 pool->base.hubbub = NULL; 1397 } 1398 for (i = 0; i < pool->base.pipe_count; i++) { 1399 if (pool->base.dpps[i] != NULL) 1400 dcn31_dpp_destroy(&pool->base.dpps[i]); 1401 1402 if (pool->base.ipps[i] != NULL) 1403 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1404 1405 if (pool->base.hubps[i] != NULL) { 1406 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1407 pool->base.hubps[i] = NULL; 1408 } 1409 1410 if (pool->base.irqs != NULL) { 1411 dal_irq_service_destroy(&pool->base.irqs); 1412 } 1413 } 1414 1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1416 if (pool->base.engines[i] != NULL) 1417 dce110_engine_destroy(&pool->base.engines[i]); 1418 if (pool->base.hw_i2cs[i] != NULL) { 1419 kfree(pool->base.hw_i2cs[i]); 1420 pool->base.hw_i2cs[i] = NULL; 1421 } 1422 if (pool->base.sw_i2cs[i] != NULL) { 1423 kfree(pool->base.sw_i2cs[i]); 1424 pool->base.sw_i2cs[i] = NULL; 1425 } 1426 } 1427 1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1429 if (pool->base.opps[i] != NULL) 1430 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1431 } 1432 1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1434 if (pool->base.timing_generators[i] != NULL) { 1435 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1436 pool->base.timing_generators[i] = NULL; 1437 } 1438 } 1439 1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1441 if (pool->base.dwbc[i] != NULL) { 1442 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1443 pool->base.dwbc[i] = NULL; 1444 } 1445 if (pool->base.mcif_wb[i] != NULL) { 1446 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1447 pool->base.mcif_wb[i] = NULL; 1448 } 1449 } 1450 1451 for (i = 0; i < pool->base.audio_count; i++) { 1452 if (pool->base.audios[i]) 1453 dce_aud_destroy(&pool->base.audios[i]); 1454 } 1455 1456 for (i = 0; i < pool->base.clk_src_count; i++) { 1457 if (pool->base.clock_sources[i] != NULL) { 1458 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1459 pool->base.clock_sources[i] = NULL; 1460 } 1461 } 1462 1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1464 if (pool->base.mpc_lut[i] != NULL) { 1465 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1466 pool->base.mpc_lut[i] = NULL; 1467 } 1468 if (pool->base.mpc_shaper[i] != NULL) { 1469 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1470 pool->base.mpc_shaper[i] = NULL; 1471 } 1472 } 1473 1474 if (pool->base.dp_clock_source != NULL) { 1475 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1476 pool->base.dp_clock_source = NULL; 1477 } 1478 1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1480 if (pool->base.multiple_abms[i] != NULL) 1481 dce_abm_destroy(&pool->base.multiple_abms[i]); 1482 } 1483 1484 if (pool->base.psr != NULL) 1485 dmub_psr_destroy(&pool->base.psr); 1486 1487 if (pool->base.dccg != NULL) 1488 dcn_dccg_destroy(&pool->base.dccg); 1489} 1490 1491static struct hubp *dcn31_hubp_create( 1492 struct dc_context *ctx, 1493 uint32_t inst) 1494{ 1495 struct dcn20_hubp *hubp2 = 1496 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1497 1498 if (!hubp2) 1499 return NULL; 1500 1501 if (hubp31_construct(hubp2, ctx, inst, 1502 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1503 return &hubp2->base; 1504 1505 BREAK_TO_DEBUGGER(); 1506 kfree(hubp2); 1507 return NULL; 1508} 1509 1510static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1511{ 1512 int i; 1513 uint32_t pipe_count = pool->res_cap->num_dwb; 1514 1515 for (i = 0; i < pipe_count; i++) { 1516 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1517 GFP_KERNEL); 1518 1519 if (!dwbc30) { 1520 dm_error("DC: failed to create dwbc30!\n"); 1521 return false; 1522 } 1523 1524 dcn30_dwbc_construct(dwbc30, ctx, 1525 &dwbc30_regs[i], 1526 &dwbc30_shift, 1527 &dwbc30_mask, 1528 i); 1529 1530 pool->dwbc[i] = &dwbc30->base; 1531 } 1532 return true; 1533} 1534 1535static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1536{ 1537 int i; 1538 uint32_t pipe_count = pool->res_cap->num_dwb; 1539 1540 for (i = 0; i < pipe_count; i++) { 1541 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1542 GFP_KERNEL); 1543 1544 if (!mcif_wb30) { 1545 dm_error("DC: failed to create mcif_wb30!\n"); 1546 return false; 1547 } 1548 1549 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1550 &mcif_wb30_regs[i], 1551 &mcif_wb30_shift, 1552 &mcif_wb30_mask, 1553 i); 1554 1555 pool->mcif_wb[i] = &mcif_wb30->base; 1556 } 1557 return true; 1558} 1559 1560static struct display_stream_compressor *dcn31_dsc_create( 1561 struct dc_context *ctx, uint32_t inst) 1562{ 1563 struct dcn20_dsc *dsc = 1564 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1565 1566 if (!dsc) { 1567 BREAK_TO_DEBUGGER(); 1568 return NULL; 1569 } 1570 1571 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1572 return &dsc->base; 1573} 1574 1575static void dcn315_destroy_resource_pool(struct resource_pool **pool) 1576{ 1577 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool); 1578 1579 dcn315_resource_destruct(dcn31_pool); 1580 kfree(dcn31_pool); 1581 *pool = NULL; 1582} 1583 1584static struct clock_source *dcn31_clock_source_create( 1585 struct dc_context *ctx, 1586 struct dc_bios *bios, 1587 enum clock_source_id id, 1588 const struct dce110_clk_src_regs *regs, 1589 bool dp_clk_src) 1590{ 1591 struct dce110_clk_src *clk_src = 1592 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1593 1594 if (!clk_src) 1595 return NULL; 1596 1597 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1598 regs, &cs_shift, &cs_mask)) { 1599 clk_src->base.dp_clk_src = dp_clk_src; 1600 return &clk_src->base; 1601 } 1602 1603 kfree(clk_src); 1604 BREAK_TO_DEBUGGER(); 1605 return NULL; 1606} 1607 1608static bool is_dual_plane(enum surface_pixel_format format) 1609{ 1610 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1611} 1612 1613static int source_format_to_bpp (enum source_format_class SourcePixelFormat) 1614{ 1615 if (SourcePixelFormat == dm_444_64) 1616 return 8; 1617 else if (SourcePixelFormat == dm_444_16) 1618 return 2; 1619 else if (SourcePixelFormat == dm_444_8) 1620 return 1; 1621 else if (SourcePixelFormat == dm_rgbe_alpha) 1622 return 5; 1623 else if (SourcePixelFormat == dm_420_8) 1624 return 3; 1625 else if (SourcePixelFormat == dm_420_12) 1626 return 6; 1627 else 1628 return 4; 1629} 1630 1631static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) 1632{ 1633 int i; 1634 struct resource_context *res_ctx = &context->res_ctx; 1635 1636 /* Only apply for dual stream scenarios with edp*/ 1637 if (context->stream_count != 2) 1638 return false; 1639 if (context->streams[0]->signal != SIGNAL_TYPE_EDP && context->streams[1]->signal != SIGNAL_TYPE_EDP) 1640 return false; 1641 1642 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1643 if (!res_ctx->pipe_ctx[i].stream) 1644 continue; 1645 1646 /*Don't apply if scaling*/ 1647 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width || 1648 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height || 1649 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width 1650 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width || 1651 res_ctx->pipe_ctx[i].plane_state->src_rect.height 1652 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height))) 1653 return false; 1654 /*Don't apply if MPO to avoid transition issues*/ 1655 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state) 1656 return false; 1657 } 1658 return true; 1659} 1660 1661static int dcn315_populate_dml_pipes_from_context( 1662 struct dc *dc, struct dc_state *context, 1663 display_e2e_pipe_params_st *pipes, 1664 bool fast_validate) 1665{ 1666 int i, pipe_cnt, crb_idx, crb_pipes; 1667 struct resource_context *res_ctx = &context->res_ctx; 1668 struct pipe_ctx *pipe = NULL; 1669 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; 1670 int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB; 1671 bool pixel_rate_crb = allow_pixel_rate_crb(dc, context); 1672 1673 DC_FP_START(); 1674 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1675 DC_FP_END(); 1676 1677 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { 1678 struct dc_crtc_timing *timing; 1679 1680 if (!res_ctx->pipe_ctx[i].stream) 1681 continue; 1682 pipe = &res_ctx->pipe_ctx[i]; 1683 timing = &pipe->stream->timing; 1684 1685 /* 1686 * Immediate flip can be set dynamically after enabling the plane. 1687 * We need to require support for immediate flip or underflow can be 1688 * intermittently experienced depending on peak b/w requirements. 1689 */ 1690 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1691 1692 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1693 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1694 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1695 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1696 DC_FP_START(); 1697 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1698 if (pixel_rate_crb && !pipe->top_pipe && !pipe->prev_odm_pipe) { 1699 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); 1700 /* Ceil to crb segment size */ 1701 int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate( 1702 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB); 1703 1704 if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) { 1705 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS; 1706 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); 1707 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1708 1709 /* Minimum 2 segments to allow mpc/odm combine if its used later */ 1710 if (approx_det_segs_required_for_pstate < 2) 1711 approx_det_segs_required_for_pstate = 2; 1712 if (split_required) 1713 approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2; 1714 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; 1715 remaining_det_segs -= approx_det_segs_required_for_pstate; 1716 } else 1717 remaining_det_segs = -1; 1718 crb_pipes++; 1719 } 1720 DC_FP_END(); 1721 1722 if (pipes[pipe_cnt].dout.dsc_enable) { 1723 switch (timing->display_color_depth) { 1724 case COLOR_DEPTH_888: 1725 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1726 break; 1727 case COLOR_DEPTH_101010: 1728 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1729 break; 1730 case COLOR_DEPTH_121212: 1731 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1732 break; 1733 default: 1734 ASSERT(0); 1735 break; 1736 } 1737 } 1738 pipe_cnt++; 1739 } 1740 1741 /* Spread remaining unreserved crb evenly among all pipes*/ 1742 if (pixel_rate_crb) { 1743 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { 1744 pipe = &res_ctx->pipe_ctx[i]; 1745 if (!pipe->stream) 1746 continue; 1747 1748 /* Do not use asymetric crb if not enough for pstate support */ 1749 if (remaining_det_segs < 0) { 1750 pipes[pipe_cnt].pipe.src.det_size_override = 0; 1751 pipe_cnt++; 1752 continue; 1753 } 1754 1755 if (!pipe->top_pipe && !pipe->prev_odm_pipe) { 1756 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) 1757 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); 1758 1759 if (remaining_det_segs > MIN_RESERVED_DET_SEGS) 1760 pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes + 1761 (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0); 1762 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) { 1763 /* Clamp to 2 pipe split max det segments */ 1764 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS); 1765 pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS; 1766 } 1767 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) { 1768 /* If we are splitting we must have an even number of segments */ 1769 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2; 1770 pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; 1771 } 1772 /* Convert segments into size for DML use */ 1773 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB; 1774 1775 crb_idx++; 1776 } 1777 pipe_cnt++; 1778 } 1779 } 1780 1781 if (pipe_cnt) 1782 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1783 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1784 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) 1785 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; 1786 1787 dc->config.enable_4to1MPC = false; 1788 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1789 if (is_dual_plane(pipe->plane_state->format) 1790 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1791 dc->config.enable_4to1MPC = true; 1792 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 1793 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; 1794 } else if (!is_dual_plane(pipe->plane_state->format) 1795 && pipe->plane_state->src_rect.width <= 5120 1796 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { 1797 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1798 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1799 pipes[0].pipe.src.unbounded_req_mode = true; 1800 } 1801 } 1802 1803 return pipe_cnt; 1804} 1805 1806static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) 1807{ 1808 *panel_config = panel_config_defaults; 1809} 1810 1811static struct dc_cap_funcs cap_funcs = { 1812 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1813}; 1814 1815static struct resource_funcs dcn315_res_pool_funcs = { 1816 .destroy = dcn315_destroy_resource_pool, 1817 .link_enc_create = dcn31_link_encoder_create, 1818 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1819 .link_encs_assign = link_enc_cfg_link_encs_assign, 1820 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1821 .panel_cntl_create = dcn31_panel_cntl_create, 1822 .validate_bandwidth = dcn31_validate_bandwidth, 1823 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1824 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a, 1825 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, 1826 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1827 .release_pipe = dcn20_release_pipe, 1828 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1829 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1830 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1831 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1832 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1833 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1834 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1835 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1836 .update_bw_bounding_box = dcn315_update_bw_bounding_box, 1837 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1838 .get_panel_config_defaults = dcn315_get_panel_config_defaults, 1839}; 1840 1841static bool dcn315_resource_construct( 1842 uint8_t num_virtual_links, 1843 struct dc *dc, 1844 struct dcn315_resource_pool *pool) 1845{ 1846 int i; 1847 struct dc_context *ctx = dc->ctx; 1848 struct irq_service_init_data init_data; 1849 1850 ctx->dc_bios->regs = &bios_regs; 1851 1852 pool->base.res_cap = &res_cap_dcn31; 1853 1854 pool->base.funcs = &dcn315_res_pool_funcs; 1855 1856 /************************************************* 1857 * Resource + asic cap harcoding * 1858 *************************************************/ 1859 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1860 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1861 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1862 dc->caps.max_downscale_ratio = 600; 1863 dc->caps.i2c_speed_in_khz = 100; 1864 dc->caps.i2c_speed_in_khz_hdcp = 100; 1865 dc->caps.max_cursor_size = 256; 1866 dc->caps.min_horizontal_blanking_period = 80; 1867 dc->caps.dmdata_alloc_size = 2048; 1868 dc->caps.max_slave_planes = 2; 1869 dc->caps.max_slave_yuv_planes = 2; 1870 dc->caps.max_slave_rgb_planes = 2; 1871 dc->caps.post_blend_color_processing = true; 1872 dc->caps.force_dp_tps4_for_cp2520 = true; 1873 if (dc->config.forceHBR2CP2520) 1874 dc->caps.force_dp_tps4_for_cp2520 = false; 1875 dc->caps.dp_hpo = true; 1876 dc->caps.dp_hdmi21_pcon_support = true; 1877 dc->caps.edp_dsc_support = true; 1878 dc->caps.extended_aux_timeout_support = true; 1879 dc->caps.dmcub_support = true; 1880 dc->caps.is_apu = true; 1881 1882 /* Color pipeline capabilities */ 1883 dc->caps.color.dpp.dcn_arch = 1; 1884 dc->caps.color.dpp.input_lut_shared = 0; 1885 dc->caps.color.dpp.icsc = 1; 1886 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1887 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1888 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1889 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1890 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1891 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1892 dc->caps.color.dpp.post_csc = 1; 1893 dc->caps.color.dpp.gamma_corr = 1; 1894 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1895 1896 dc->caps.color.dpp.hw_3d_lut = 1; 1897 dc->caps.color.dpp.ogam_ram = 1; 1898 // no OGAM ROM on DCN301 1899 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1900 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1901 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1902 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1903 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1904 dc->caps.color.dpp.ocsc = 0; 1905 1906 dc->caps.color.mpc.gamut_remap = 1; 1907 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1908 dc->caps.color.mpc.ogam_ram = 1; 1909 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1910 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1911 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1912 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1913 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1914 dc->caps.color.mpc.ocsc = 1; 1915 1916 /* read VBIOS LTTPR caps */ 1917 { 1918 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1919 enum bp_result bp_query_result; 1920 uint8_t is_vbios_lttpr_enable = 0; 1921 1922 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1923 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1924 } 1925 1926 /* interop bit is implicit */ 1927 { 1928 dc->caps.vbios_lttpr_aware = true; 1929 } 1930 } 1931 1932 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1933 dc->debug = debug_defaults_drv; 1934 1935 // Init the vm_helper 1936 if (dc->vm_helper) 1937 vm_helper_init(dc->vm_helper, 16); 1938 1939 /************************************************* 1940 * Create resources * 1941 *************************************************/ 1942 1943 /* Clock Sources for Pixel Clock*/ 1944 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1945 dcn31_clock_source_create(ctx, ctx->dc_bios, 1946 CLOCK_SOURCE_COMBO_PHY_PLL0, 1947 &clk_src_regs[0], false); 1948 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 1949 dcn31_clock_source_create(ctx, ctx->dc_bios, 1950 CLOCK_SOURCE_COMBO_PHY_PLL1, 1951 &clk_src_regs[1], false); 1952 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 1953 dcn31_clock_source_create(ctx, ctx->dc_bios, 1954 CLOCK_SOURCE_COMBO_PHY_PLL2, 1955 &clk_src_regs[2], false); 1956 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 1957 dcn31_clock_source_create(ctx, ctx->dc_bios, 1958 CLOCK_SOURCE_COMBO_PHY_PLL3, 1959 &clk_src_regs[3], false); 1960 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 1961 dcn31_clock_source_create(ctx, ctx->dc_bios, 1962 CLOCK_SOURCE_COMBO_PHY_PLL4, 1963 &clk_src_regs[4], false); 1964 1965 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 1966 1967 /* todo: not reuse phy_pll registers */ 1968 pool->base.dp_clock_source = 1969 dcn31_clock_source_create(ctx, ctx->dc_bios, 1970 CLOCK_SOURCE_ID_DP_DTO, 1971 &clk_src_regs[0], true); 1972 1973 for (i = 0; i < pool->base.clk_src_count; i++) { 1974 if (pool->base.clock_sources[i] == NULL) { 1975 dm_error("DC: failed to create clock sources!\n"); 1976 BREAK_TO_DEBUGGER(); 1977 goto create_fail; 1978 } 1979 } 1980 1981 /* TODO: DCCG */ 1982 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1983 if (pool->base.dccg == NULL) { 1984 dm_error("DC: failed to create dccg!\n"); 1985 BREAK_TO_DEBUGGER(); 1986 goto create_fail; 1987 } 1988 1989 /* TODO: IRQ */ 1990 init_data.ctx = dc->ctx; 1991 pool->base.irqs = dal_irq_service_dcn315_create(&init_data); 1992 if (!pool->base.irqs) 1993 goto create_fail; 1994 1995 /* HUBBUB */ 1996 pool->base.hubbub = dcn31_hubbub_create(ctx); 1997 if (pool->base.hubbub == NULL) { 1998 BREAK_TO_DEBUGGER(); 1999 dm_error("DC: failed to create hubbub!\n"); 2000 goto create_fail; 2001 } 2002 2003 /* HUBPs, DPPs, OPPs and TGs */ 2004 for (i = 0; i < pool->base.pipe_count; i++) { 2005 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2006 if (pool->base.hubps[i] == NULL) { 2007 BREAK_TO_DEBUGGER(); 2008 dm_error( 2009 "DC: failed to create hubps!\n"); 2010 goto create_fail; 2011 } 2012 2013 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2014 if (pool->base.dpps[i] == NULL) { 2015 BREAK_TO_DEBUGGER(); 2016 dm_error( 2017 "DC: failed to create dpps!\n"); 2018 goto create_fail; 2019 } 2020 } 2021 2022 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2023 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2024 if (pool->base.opps[i] == NULL) { 2025 BREAK_TO_DEBUGGER(); 2026 dm_error( 2027 "DC: failed to create output pixel processor!\n"); 2028 goto create_fail; 2029 } 2030 } 2031 2032 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2033 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2034 ctx, i); 2035 if (pool->base.timing_generators[i] == NULL) { 2036 BREAK_TO_DEBUGGER(); 2037 dm_error("DC: failed to create tg!\n"); 2038 goto create_fail; 2039 } 2040 } 2041 pool->base.timing_generator_count = i; 2042 2043 /* PSR */ 2044 pool->base.psr = dmub_psr_create(ctx); 2045 if (pool->base.psr == NULL) { 2046 dm_error("DC: failed to create psr obj!\n"); 2047 BREAK_TO_DEBUGGER(); 2048 goto create_fail; 2049 } 2050 2051 /* ABM */ 2052 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2053 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2054 &abm_regs[i], 2055 &abm_shift, 2056 &abm_mask); 2057 if (pool->base.multiple_abms[i] == NULL) { 2058 dm_error("DC: failed to create abm for pipe %d!\n", i); 2059 BREAK_TO_DEBUGGER(); 2060 goto create_fail; 2061 } 2062 } 2063 2064 /* MPC and DSC */ 2065 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2066 if (pool->base.mpc == NULL) { 2067 BREAK_TO_DEBUGGER(); 2068 dm_error("DC: failed to create mpc!\n"); 2069 goto create_fail; 2070 } 2071 2072 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2073 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2074 if (pool->base.dscs[i] == NULL) { 2075 BREAK_TO_DEBUGGER(); 2076 dm_error("DC: failed to create display stream compressor %d!\n", i); 2077 goto create_fail; 2078 } 2079 } 2080 2081 /* DWB and MMHUBBUB */ 2082 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2083 BREAK_TO_DEBUGGER(); 2084 dm_error("DC: failed to create dwbc!\n"); 2085 goto create_fail; 2086 } 2087 2088 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2089 BREAK_TO_DEBUGGER(); 2090 dm_error("DC: failed to create mcif_wb!\n"); 2091 goto create_fail; 2092 } 2093 2094 /* AUX and I2C */ 2095 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2096 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2097 if (pool->base.engines[i] == NULL) { 2098 BREAK_TO_DEBUGGER(); 2099 dm_error( 2100 "DC:failed to create aux engine!!\n"); 2101 goto create_fail; 2102 } 2103 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2104 if (pool->base.hw_i2cs[i] == NULL) { 2105 BREAK_TO_DEBUGGER(); 2106 dm_error( 2107 "DC:failed to create hw i2c!!\n"); 2108 goto create_fail; 2109 } 2110 pool->base.sw_i2cs[i] = NULL; 2111 } 2112 2113 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2114 if (!resource_construct(num_virtual_links, dc, &pool->base, 2115 &res_create_funcs)) 2116 goto create_fail; 2117 2118 /* HW Sequencer and Plane caps */ 2119 dcn31_hw_sequencer_construct(dc); 2120 2121 dc->caps.max_planes = pool->base.pipe_count; 2122 2123 for (i = 0; i < dc->caps.max_planes; ++i) 2124 dc->caps.planes[i] = plane_cap; 2125 2126 dc->cap_funcs = cap_funcs; 2127 2128 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; 2129 2130 return true; 2131 2132create_fail: 2133 2134 dcn315_resource_destruct(pool); 2135 2136 return false; 2137} 2138 2139struct resource_pool *dcn315_create_resource_pool( 2140 const struct dc_init_data *init_data, 2141 struct dc *dc) 2142{ 2143 struct dcn315_resource_pool *pool = 2144 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL); 2145 2146 if (!pool) 2147 return NULL; 2148 2149 if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) 2150 return &pool->base; 2151 2152 BREAK_TO_DEBUGGER(); 2153 kfree(pool); 2154 return NULL; 2155} 2156