Searched refs:lut (Results 76 - 100 of 103) sorted by relevance

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/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Ddss.h449 const struct drm_color_lut *lut,
H A Ddispc.c3853 const struct drm_color_lut *lut,
3860 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3866 if (lut == NULL || length < 2) {
3867 lut = dispc_mgr_gamma_default_lut;
3882 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w;
3883 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w;
3884 b = (lut[i].blue * (w - j) + lut[
3851 dispc_mgr_set_gamma(struct dispc_device *dispc, enum omap_channel channel, const struct drm_color_lut *lut, unsigned int length) argument
[all...]
/linux-master/drivers/ntb/hw/mscc/
H A Dntb_hw_switchtec.c197 int lut; local
203 lut = widx >= sndev->peer_nr_direct_mw;
210 *addr_align = lut ? size : SZ_4K;
213 *size_align = lut ? size : SZ_4K;
942 "Error setting up reserved lut window: %08x / %08x\n",
1207 dev_dbg(&sndev->stdev->dev, "MWs: %d direct, %d lut\n",
1217 dev_dbg(&sndev->stdev->dev, "Peer MWs: %d direct, %d lut\n",
/linux-master/drivers/gpu/drm/ingenic/
H A Dingenic-drm-drv.c643 const struct drm_color_lut *lut)
648 u16 color = drm_color_lut_extract(lut[i].red, 5) << 11
649 | drm_color_lut_extract(lut[i].green, 6) << 5
650 | drm_color_lut_extract(lut[i].blue, 5);
642 ingenic_drm_update_palette(struct ingenic_drm *priv, const struct drm_color_lut *lut) argument
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dcrtc.c811 * mark the lut values as dirty by setting depth==0, and it'll be
815 nv_crtc->lut.depth = 0;
857 if (nv_crtc->lut.depth != drm_fb->format->depth) {
858 nv_crtc->lut.depth = drm_fb->format->depth;
1296 nv_crtc->lut.depth = 0;
/linux-master/drivers/net/ethernet/intel/idpf/
H A Dvirtchnl2.h902 * @lut: RSS lookup table.
915 __le32 lut[] __counted_by_le(lut_entries);
H A Didpf_virtchnl.c2315 * idpf_send_get_set_rss_lut_msg - Send virtchnl get or set rss lut message
2333 buf_size = struct_size(rl, lut, rss_data->rss_lut_size);
2354 rl->lut[i] = cpu_to_le32(rss_data->rss_lut[i]);
2370 /* size didn't change, we can reuse existing lut buf */
2384 memcpy(rss_data->rss_lut, recv_rl->lut, rss_data->rss_lut_size);
/linux-master/drivers/gpu/drm/mgag200/
H A Dmgag200_drv.h403 struct drm_color_lut *lut);
/linux-master/drivers/gpu/drm/ast/
H A Dast_mode.c91 struct drm_color_lut *lut)
101 lut[i].red >> 8,
102 lut[i].green >> 8,
103 lut[i].blue >> 8);
89 ast_crtc_set_gamma(struct ast_device *ast, const struct drm_format_info *format, struct drm_color_lut *lut) argument
/linux-master/drivers/staging/media/ipu3/include/uapi/
H A Dintel-ipu3.h841 * @lut: lookup table &ipu3_uapi_bnr_static_config_lut_config
856 struct ipu3_uapi_bnr_static_config_lut_config lut; member in struct:ipu3_uapi_bnr_static_config
1013 * @lut: 256 tabulated values of the gamma function. LUT[1].. LUT[256]
1021 __u16 lut[IPU3_UAPI_GAMMA_CORR_LUT_ENTRIES]; member in struct:ipu3_uapi_gamma_corr_lut
/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_prototype.h59 bool pf_lut, u8 *lut, u16 lut_size);
61 bool pf_lut, u8 *lut, u16 lut_size);
H A Di40e_common.c237 * @lut: pointer to the lut buffer provided by the caller
238 * @lut_size: size of the lut buffer
245 u8 *lut, u16 lut_size,
277 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
287 * @lut: pointer to the lut buffer provided by the caller
288 * @lut_size: size of the lut buffer
293 bool pf_lut, u8 *lut, u16 lut_size)
295 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_siz
243 i40e_aq_get_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, bool pf_lut, u8 *lut, u16 lut_size, bool set) argument
292 i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, bool pf_lut, u8 *lut, u16 lut_size) argument
309 i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, bool pf_lut, u8 *lut, u16 lut_size) argument
[all...]
H A Di40e_ethtool.c5128 u8 *lut, *seed = NULL; local
5138 lut = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
5139 if (!lut)
5141 ret = i40e_get_rss(vsi, seed, lut, I40E_HLUT_ARRAY_SIZE);
5145 rxfh->indir[i] = (u32)(lut[i]);
5148 kfree(lut);
5192 /* Each 32 bits pointed by 'indir' is stored with a lut entry */
/linux-master/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c1264 struct drm_color_lut *lut = crtc->state->gamma_lut->data; local
1270 word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
1271 (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
1272 drm_color_lut_extract(lut[i].blue, bpc);
/linux-master/drivers/staging/media/atomisp/pci/
H A Dsh_css_params.c2632 static void host_lut_store(const void *lut) argument
2637 gdc_lut_store((gdc_ID_t)i, (const int (*)[HRT_GDC_N]) lut);
2641 const void *lut)
2646 IA_CSS_ENTER("pipe=%p lut=%p", pipe, lut);
2648 if (!lut || !pipe) {
2655 * safe to store lut to gdc HW. If pipe->stream is NULL, then no stream is
2660 "unable to set scaler lut since stream has started\n");
2679 gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])lut,
2687 IA_CSS_LEAVE("lut(
2640 ia_css_pipe_set_bci_scaler_lut(struct ia_css_pipe *pipe, const void *lut) argument
[all...]
/linux-master/drivers/net/ethernet/intel/ice/
H A Dice_main.c3685 * @lut: Lookup table
3689 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size) argument
3694 lut[i] = i % rss_size;
7892 * @lut: Lookup table
7897 int ice_set_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size)
7903 if (!lut)
7909 params.lut = lut;
7913 dev_err(ice_pf_to_dev(vsi->back), "Cannot set RSS lut, err %d aq_err %s\n",
7945 * @lut
7889 ice_set_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size) argument
7942 ice_get_rss_lut(struct ice_vsi *vsi, u8 *lut, u16 lut_size) argument
[all...]
H A Dice_common.c4003 u8 *lut = params->lut; local
4006 if (!lut || !ice_is_vsi_valid(hw, vsi_handle))
4031 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
H A Dice_type.h1056 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ member in struct:ice_aq_get_set_rss_lut_params
/linux-master/drivers/media/platform/renesas/
H A Drcar_fdp1.c846 static void fdp1_write_lut(struct fdp1_dev *fdp1, const u8 *lut, argument
856 fdp1_write(fdp1, lut[i], base + (i*4));
859 pad = lut[i-1];
/linux-master/drivers/mtd/nand/raw/
H A Dsunxi_nand.c1371 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration, argument
1378 if (clk_cycles <= lut[i])
/linux-master/drivers/net/ethernet/intel/iavf/
H A Diavf_virtchnl.c1126 len = virtchnl_struct_size(vrl, lut, adapter->rss_lut_size);
1132 memcpy(vrl->lut, adapter->rss_lut, adapter->rss_lut_size);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h86 struct dc_3dlut **lut,
92 struct dc_3dlut **lut,
/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c501 dev_err(dev, "invalid gamma lut size: %zu bytes\n",
519 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data;
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c2237 struct dc_3dlut **lut,
2262 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
2264 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
2293 * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
2294 * but forcing lut memory to shutdown state is immediate. This causes
2295 * single frame corruption as lut gets disabled mid-frame unless shutdown
2234 dc_acquire_release_mpc_3dlut( struct dc *dc, bool acquire, struct dc_stream_state *stream, struct dc_3dlut **lut, struct dc_transfer_func **shaper) argument
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_display.c5183 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5186 current_config->lut, pipe_config->lut, \
5188 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \

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