Searched refs:clr (Results 201 - 225 of 230) sorted by relevance

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/linux-master/arch/m68k/fpsp040/
H A Dskeleton.S153 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit
H A Dres_func.S633 | clr sticky
643 | clr sticky
963 | and aovfl, and clr the mantissa (incorrectly set by the
1144 | and aovfl, and clr the mantissa (incorrectly set by the
/linux-master/arch/sparc/lib/
H A Dcsum_copy.S75 clr %o4
H A Dchecksum_32.S457 clr %o0
/linux-master/drivers/media/i2c/
H A Dtc358743.c927 unsigned int clr = 0; local
933 clr |= MASK_CECRICLR;
935 clr |= MASK_CECTICLR;
936 i2c_wr32(sd, CECICLR, clr);
/linux-master/drivers/gpu/drm/i915/
H A Di915_debugfs.c492 wa->set, wa->clr);
/linux-master/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_minidump.c1313 if (fw_dump->clr) {
1389 fw_dump->clr = 1;
H A Dqlcnic.h444 u8 clr; /* flag to indicate if dump is cleared */ member in struct:qlcnic_fw_dump
/linux-master/arch/powerpc/kvm/
H A Dbook3s_64_mmu_radix.c375 unsigned long clr, unsigned long set,
378 return __radix_pte_update(ptep, clr, set);
374 kvmppc_radix_update_pte(struct kvm *kvm, pte_t *ptep, unsigned long clr, unsigned long set, unsigned long addr, unsigned int shift) argument
/linux-master/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c337 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr) argument
339 zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
/linux-master/drivers/mailbox/
H A Dimx-mailbox.c208 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) argument
215 val &= ~clr;
/linux-master/drivers/dma/xilinx/
H A Dxilinx_dpdma.c478 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr) argument
480 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);
H A Dxilinx_dma.c563 u32 clr)
565 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
562 dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, u32 clr) argument
/linux-master/drivers/spi/
H A Dspi-mtk-snfi.c356 static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) argument
361 val &= ~clr;
H A Dspi-topcliff-pch.c241 u32 set, u32 clr)
244 tmp = (tmp & ~clr) | set;
240 pch_spi_setclr_reg(struct spi_controller *host, int idx, u32 set, u32 clr) argument
/linux-master/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h5232 * clr bit set.
5249 * Clear counters. Setting the clr bit will reset the counter value
5254 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
7585 /* Clear. Setting the clr bit will reset the counter value for
10872 * The PTP_ING_FIFO trap provides MTPPTR with clr according
10881 * The PTP_EGR_FIFO trap provides MTPPTR with clr according
11075 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
12759 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
12763 * writing to the clr field.
12788 enum mlxsw_reg_sbxx_dir dir, bool clr,
12787 mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, enum mlxsw_reg_sbxx_dir dir, bool clr, u32 min_buff, u32 max_buff) argument
12933 mlxsw_reg_sbsr_pack(char *payload, bool clr) argument
[all...]
/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-mio-defs.h323 uint64_t clr:1; member in struct:cvmx_mio_boot_dma_cfgx::cvmx_mio_boot_dma_cfgx_s
339 uint64_t clr:1;
2502 uint64_t clr:1; member in struct:cvmx_mio_ndf_dma_cfg::cvmx_mio_ndf_dma_cfg_s
2518 uint64_t clr:1;
/linux-master/drivers/ata/
H A Dpata_octeon_cf.c571 mio_boot_dma_cfg.s.clr = 0;
/linux-master/include/soc/tegra/
H A Dbpmp-abi.h2985 int32_t clr; member in struct:cmd_uphy_margin_control_request
/linux-master/include/ufs/
H A Dufshcd.h1434 const u16 *other_mask, u16 set, u16 clr);
/linux-master/arch/sparc/kernel/
H A Dhead_64.S716 clr %g5
/linux-master/drivers/infiniband/hw/qib/
H A Dqib_iba7322.c5535 u64 clr; local
5540 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5543 if (clr)
5544 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5570 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5571 if (clr == ppd->cpspec->iblnkdownsnap)
/linux-master/drivers/dma/
H A Dste_dma40.c259 * @clr: Interrupt clear register.
266 u32 clr; member in struct:d40_interrupt_lookup
1706 writel(BIT(idx), base->virtbase + il[row].clr);
/linux-master/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c3357 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) argument
3367 reg &= ~clr;
/linux-master/drivers/infiniband/hw/hns/
H A Dhns_roce_hw_v2.c5585 struct hns_roce_sccc_clr *clr; local
5604 clr = (struct hns_roce_sccc_clr *)desc.data;
5605 clr->qpn = cpu_to_le32(hr_qp->qpn);
5619 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
5630 ibdev_err(ibdev, "query SCC clr done flag overtime.\n");

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