#
d9d441e8 |
|
14-Dec-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Add nve_flood_prf_id field to SFMR The field is used for setting a flood profile for lookup of KVD entry for NVE underlay. As the other uses of flood profile, this references a traffic type-to-offset mapping, except here it is not applied to PGT offsets, but KVD offsets. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6b10371c |
|
20-Nov-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Add to SFMR register the fields related to CFF flood mode Add the field cff_mid_base, which specifies at which point in PGT the per-FID flood table is stored. Add cff_prf_id, the profile ID, which determines on which row of the flood table a flood vector can be found for a given traffic type. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/3ad7ae38cf6534bedcd876f16090d109a814b3e3.1700503644.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
446bc1e9 |
|
20-Nov-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Extract flood-mode specific part of mlxsw_reg_sfmr_pack() In CFF mode, it is necessary to set a different set of SFMR fields. Leave in mlxsw_reg_sfmr_pack() only the common bits, and move the parts relevant to controlled flood mode directly to the call site. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/6f29639ebc3ca0722272e6c644ca910096469413.1700503644.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
642d6a20 |
|
20-Nov-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Drop unnecessary writes from mlxsw_reg_sfmr_pack() The MLXSW_REG_ZERO at the beginning of the function wipes the whole payload. There's no need to set vtfp and vv to false explicitly. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/04a51ea7cf31eea0ef7707311d8e864e2d9ef307.1700503644.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
7eb90295 |
|
20-Nov-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Mark SFGC & some SFMR fields as reserved in CFF mode Some existing fields and the whole register of SFGC are reserved in CFF mode. Backport the reservation note to these fields. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/e1d5977a8cb778227e4ea2fd1515529957ce5de7.1700503643.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
e1e4ce6c |
|
20-Nov-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Add Switch FID Flooding Profiles Register The SFFP register populates the fid flooding profile tables used for the NVE flooding and Compressed-FID Flooding (CFF). Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/ca42eb67763bd0c7cf035afc62ef73632f3f61a6.1700503643.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
f257c73e |
|
15-Nov-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: pci: Add support for new reset flow The driver resets the device during probe and during a devlink reload. The current reset method reloads the current firmware version or a pending one, if one was previously flashed using devlink. However, the current reset method does not result in a PCI hot reset, preventing the PCI firmware from being upgraded, unless the system is rebooted. To solve this problem, a new reset command (6) was implemented in the firmware. Unlike the current command (1), after issuing the new command the device will not start the reset immediately, but only after a PCI hot reset. Implement the new reset method by first verifying that it is supported by the current firmware version by querying the Management Capabilities Mask (MCAM) register. If supported, issue the new reset command (6) via MRSR register followed by a PCI reset by calling __pci_reset_function_locked(). Once the PCI firmware is operational, go back to the regular reset flow and wait for the entire device to become ready. That is, repeatedly read the "system_status" register from the BAR until a value of "FW_READY" (0x5E) appears. Tested: # for i in $(seq 1 10); do devlink dev reload pci/0000:01:00.0; done Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e6dbab40 |
|
15-Nov-2023 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Extend MRSR pack() function to support new commands Currently mlxsw_reg_mrsr_pack() always sets 'command=1'. As preparation for support of new reset flow, pass the command as an argument to the function and add an enum for this field. For now, always pass 'command=1' to the pack() function. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
cf0a86e8 |
|
18-Oct-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Add SGCR.lag_lookup_pgt_base Add SGCR.lag_lookup_pgt_base, which is used for configuring the base address of the LAG table within the PGT table for cases when the driver is responsible for the table placement. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
66eaaa85 |
|
18-Oct-2023 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Drop SGCR.llb SGCR, Switch General Configuration Register, has not been used since commit b0d80c013b04 ("mlxsw: Remove Mellanox SwitchX-2 ASIC support"). We will need the register again shortly, so instead of dropping it and reintroducing again, just drop the sole unused field. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c755655c |
|
22-Sep-2023 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Limit MTBR register payload to a single data record The MTBR register is used to read temperatures from multiple sensors in one transaction, but the driver only reads from a single sensor in each transaction. Rrestrict the payload size of the MTBR register to prevent the transmission of redundant data to the firmware. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1f4aea1f |
|
25-Jul-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: core_env: Read transceiver module EEPROM in 128 bytes chunks Old firmware versions could only read up to 48 bytes from a transceiver module's EEPROM in one go. Newer versions can read up to 128 bytes, resulting in fewer transactions. Query support for the new capability during driver initialization and if supported, read up to 128 bytes in one go. This is going to be especially useful for upcoming transceiver module firmware flashing support. Before: # perf stat -e devlink:devlink_hwmsg -- ethtool -m swp11 page 0x1 offset 128 length 128 i2c 0x50 [...] Performance counter stats for 'ethtool -m swp11 page 0x1 offset 128 length 128 i2c 0x50': 3 devlink:devlink_hwmsg After: # perf stat -e devlink:devlink_hwmsg -- ethtool -m swp11 page 0x1 offset 128 length 128 i2c 0x50 [...] Performance counter stats for 'ethtool -m swp11 page 0x1 offset 128 length 128 i2c 0x50': 1 devlink:devlink_hwmsg Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/99d1618e8cd5acefb2f795dfde1a5b41caa07dcb.1690281940.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
c8dbf678 |
|
25-Jul-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Increase Management Cable Info Access Register length The layout of the register always supported 128 bytes payloads, but the driver defined the register with a shorter length because it uses a maximum payload size of 48 bytes. Increase the register's length in preparation for using 128 bytes payloads. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/ba5c0f631e2cfd61bd21218d0cbfe03fbfe521f9.1690281940.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
3930dcc5 |
|
25-Jul-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Remove unused function argument The 'lock' argument is always set to the default value of '0'. Remove it from the arguments list. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/fb5dd22830622ceeda1c2d6431c27fccd0687aca.1690281940.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
7447eda4 |
|
25-Jul-2023 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Management Capabilities Mask Register MCAM register reports the device supported management features. Querying this register exposes if features are supported with the current firmware version in the current ASIC. Then, the driver can separate between different implementations dynamically. MCAM register supports querying whether the MCIA register supports 128 bytes payloads or only 48 bytes. Add support for the register as preparation for allowing larger MCIA transactions. Note that the access to the bits in the field 'mng_feature_cap_mask' is not same to other mask fields in other registers. In most of the cases bit #0 is the first one in the last dword, in MCAM register, bits #0-#31 are in the first dword and so on. Declare the mask field using bits arrays per dword to simplify the access. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/1427a3f57ba93db1c5dd4f982bfb31dd5c82356e.1690281940.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
68bf5100 |
|
25-Jul-2023 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Move 'mpsc' definition in 'mlxsw_reg_infos' The array 'mlxsw_reg_infos' is ordered by registers' IDs. The ID of MPSC register is 0x9080, so it should be after MCDA (register ID 0x9063) and not after MTUTC (register ID 0x9055). Note that the register's fields are defined in the correct place in the file, only the definition in 'mlxsw_reg_infos' is wrong. This issue was found while adding new register which supposed to be before mpsc. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/c5e270cd5769f301fe81235622215143506e1b48.1690281940.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
f3b8bec7 |
|
11-Jul-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add Policy-Engine Port Range Register Add the Policy-Engine Port Range Register that is used for configuring port range identification. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Link: https://lore.kernel.org/r/d1a1f53d758f7452cf5abfe006b23496076ec3e6.1689092769.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
0dc63b9c |
|
17-Aug-2023 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Fix SSPR register layout The two most significant bits of the "local_port" field in the SSPR register are always cleared since they are overwritten by the deprecated and overlapping "sub_port" field. On systems with more than 255 local ports (e.g., Spectrum-4), this results in the firmware maintaining invalid mappings between system port and local port. Specifically, two different systems ports (0x1 and 0x101) point to the same local port (0x1), which eventually leads to firmware errors. Fix by removing the deprecated "sub_port" field. Fixes: fd24b29a1b74 ("mlxsw: reg: Align existing registers to use extended local_port field") Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/9b909a3033c8d3d6f67f237306bef4411c5e6ae4.1692268427.git.petrm@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
42b4f757 |
|
19-Jan-2023 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add TLV related fields to MGIR register MGIR (Management General Information Register) allows software to query the hardware and firmware general information. As part of firmware information, the driver can query if string TLV and latency TLV are supported. These TLVs are part of EMAD's header and are used to provide information per EMAD packet to software. Currently, string TLV is already used by the driver, but it does not query if this TLV is supported from MGIR. The next patches will add support of latency TLV. Add the relevant fields to MGIR, so then the driver will query them to know if the TLVs are supported before using them. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
0b31fb9b |
|
08-Nov-2022 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add Switch Port FDB Security Register Add the Switch Port FDB Security Register (SPFSR) that allows enabling and disabling security checks on a given local port. In Linux terms, it allows locking / unlocking a port. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
d85be0f5 |
|
08-Nov-2022 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum_trap: Register 802.1X packet traps with devlink Register the previously added packet traps with devlink. This allows user space to tune their policers and in the case of the locked port trap, user space can set its action to "trap" in order to gain visibility into packets that were discarded by the device due to the locked port check failure. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
cceef209 |
|
20-Oct-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Add support for 800Gbps link modes Add support for 800Gbps speed, link modes of 100Gbps per lane. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a9c3abf4 |
|
22-Sep-2022 |
Gaosheng Cui <cuigaosheng1@huawei.com> |
mlxsw: reg: Remove deprecated code about SFTR-V2 Register Remove all the code about SFTR-V2 Register which have been deprecated since commit 77b7f83d5c25 ("mlxsw: Enable unified bridge model"). Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
3471ac9b |
|
24-Aug-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: Remove unused IB stuff There are some IB leftovers that are no longer used in the code. So remove them. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
8f9b0513 |
|
25-Jul-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Management DownStream Device Tunneling Register The MDDT register allows to deliver query and request messages (PRM registers, commands) to a DownStream device. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
4ea07cf6 |
|
25-Jul-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Extend MDDQ by device_info Extend existing MDDQ register by possibility to query information about devices residing on a line card. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
731416e9 |
|
24-Jul-2022 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: reg: Add Monitoring Time Precision Correction Port Configuration Register In Spectrum-2, all the packets are time stamped, the MTPCPC register is used to configure the types of packets that will adjust the correction field and which port will trap PTP packets. If ingress correction is set on a port for a given packet type, then when such a packet is received via the port, the current time stamp is subtracted from the correction field. If egress correction is set on a port for a given packet type, then when such a packet is transmitted via the port, the current time stamp is added to the correction field. Assuming the systems is configured correctly, the above means that the correction field will contain the transient delay between the ports. Add this register for a future use in order to support PTP in Spectrum-2. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
97b05cfb |
|
24-Jul-2022 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: reg: Add MTUTC register's fields for supporting PTP in Spectrum-2 The MTUTC register configures the HW UTC counter. Add the relevant fields and operations to support PTP in Spectrum-2 and update mlxsw_reg_mtutc_pack() with the new fields for a future use. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1c358fed |
|
24-Jul-2022 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: Rename mlxsw_reg_mtptptp_pack() to mlxsw_reg_mtptpt_pack() The right name of the register is MTPTPT, which refers to Monitoring Precision Time Protocol Trap Register. Therefore, rename the function mlxsw_reg_mtptptp_pack() to mlxsw_reg_mtptpt_pack(). Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d4324e31 |
|
04-Jul-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Add new FID families for unified bridge model In the unified bridge model, mlxsw will no longer emulate 802.1Q FIDs using 802.1D FIDs. The new FID table will look as follows: +---------------+ | 802.1q FIDs | 4K entries | [1..4094] | +---------------+ | 802.1d FIDs | 1K entries | [4095..5118] | +---------------+ | Dummy FIDs | 1 entry | [5119..5119] | +---------------+ | rFIDs | 11K entries | [5120..16383] | +---------------+ In order to make the change easier to review, four new temporary FID families will be added (e.g., MLXSW_SP_FID_TYPE_8021D_UB) and will not be registered with the FID core until mlxsw is flipped to use the unified bridge model. Add .1d, rfid and dummy FID families for unified bridge, the next patch will add .1q family separately as it requires more changes. The following changes are required: 1. Add 'smpe_index_valid' field to 'struct mlxsw_sp_fid_family' and set SFMR.smpe accordingly. SMPE index is reserved for rFIDs, as their flooding is handled by firmware, and always reserved in Spectrum-1, as it is configured as part of PGT table. 2. Add 'ubridge' field to 'struct mlxsw_sp_fid_family'. This field will be removed later, use it in mlxsw_sp_fid_family_{register,unregister}() to skip the registration / unregistration of the new families when the legacy model is used. 3. Indexes - the start and end indexes of each FID family will need to be changed according to the above diagram. 4. Add flood tables for unified bridge model, use 'fid_offset' as table type, as in the new model the access to flood tables will be using 'fid_offset' calculation. 5. FID family operation changes: a. rFID supposed to be created using SFMR, as it is not created by firmware using unified bridge model. b. port_vid_map() should perform SVFA for rFID, as the mapping is not created by firmware using unified bridge model. c. flood_index() is not aligned to the new model, as this function will be removed later. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
058de325 |
|
04-Jul-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Configure egress FID classification after routing After routing, a packet needs to perform an L2 lookup using the DMAC it got from the routing and a FID. In unified bridge model, the egress FID configuration needs to be performed by software. It is configured by RITR for both sub-port RIFs and FID RIFs. Currently FID RIFs already configure eFID. Add eFID configuration for sub-port RIFs. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
fea20547 |
|
04-Jul-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Configure ingress RIF classification Before layer 2 forwarding, the device classifies an incoming packet to a FID. The classification is done based on one of the following keys: 1. FID 2. VNI (after decapsulation) 3. VID / {Port, VID} After classification, the FID is known, but also all the attributes of the FID, such as the router interface (RIF) via which a packet that needs to be routed will ingress the router block. In the legacy model, when a RIF was created / destroyed, it was firmware's responsibility to update it in the previously mentioned FID classification records. In the unified bridge model, this responsibility moved to software. The third classification requires to iterate over the FID's {Port, VID} list and issue SVFA write with the correct mapping table according to the port's mode (virtual or not). We never map multiple VLANs to the same FID using VID->FID mapping, so such a mapping needs to be performed once. When a new FID classification entry is configured and the FID already has a RIF, set the RIF as part of SVFA configuration. The reverse needs to be done when clearing a RIF from a FID. Currently, clearing is done by issuing mlxsw_sp_fid_rif_set() with a NULL RIF pointer. Instead, introduce mlxsw_sp_fid_rif_unset(). Note that mlxsw_sp_fid_rif_set() is called after the RIF is fully operational, so it conforms to the internal requirement regarding SVFA.irif_v: "Must not be set for a non-enabled RIF". Do not set the ingress RIF for rFIDs, as the {Port, VID}->rFID entry is configured by firmware when legacy model is used, a next patch will handle this configuration for rFIDs and unified bridge model. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
53d7ae53 |
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04-Jul-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Configure egress VID for unicast FDB entries Using unified bridge model, firmware no longer configures the egress VID "under the hood" and moves this responsibility to software. For layer 2, this means that software needs to determine the egress VID for both unicast (i.e., FDB) and multicast (i.e., MDB and flooding) flows. Unicast FDB records and unicast LAG FDB records have new fields - "set_vid" and "vid", set them. For records which point to router port, do not set these fields. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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9f6f467a |
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27-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_fid: Set 'mid_base' as part of flood tables initialization The PGT (Port Group Table) table maps an index to a bitmap of local ports to which a packet needs to be replicated. This table is used for layer 2 multicast and flooding. The index to PGT table which is called 'mid_index', is a result of 'mid_base' + 'fid_offset'. Using the legacy bridge model, firmware configures 'mid_base'. However, using the new model, software is responsible to configure it via SFGC register. The first 15K entries will be used for flooding and the rest for multicast. The table will look as follows: +----------------------------+ | | | 802.1q, unicast flooding | 4K entries | | +----------------------------+ | | | 802.1q, multicast flooding | 4K entries | | +----------------------------+ | | | 802.1q, broadcast flooding | 4K entries | | +----------------------------+ | 802.1d, unicast flooding | 1K entries +----------------------------+ | 802.1d, multicast flooding | 1K entries +----------------------------+ | 802.1d, broadcast flooding | 1K entries +----------------------------+ | | | | | Multicast entries | The rest of the table | | | | +----------------------------+ Add 'pgt_base' to 'struct mlxsw_sp_fid_family' and use it to calculate MID base, set 'SFGC.mid_base' as part of flood tables initialization. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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#
aa845e36 |
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27-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Set flood bridge type for FIDs In the unified bridge model, the bridge type FID attribute is no longer configured by the firmware, but instead by software when creating and editing a FID via SFMR register. Set this field as part of FID creation and edition flow. Default to 0 (reserved) as long as the driver operates in the legacy bridge model. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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#
fad8e1b6 |
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27-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Prepare 'bridge_type' field for SFMR usage Under the legacy bridge model, the field 'bridge_type' is used only in SFGC register, to determine the type of flood table (FID/FID offset). Under the unified bridge model, it will be used also in SFMR register. When a BUM packet needs to be flooded, SFGC is used to provide the 'mid_base' for PGT table. The access to SFGC is by {packet type, bridge type}. Under the unified bridge model, software is responsible for configuring 'bridge_type' as part of SFMR. As preparation for the new required configuration, rename 'enum mlxsw_reg_sfgc_bridge_type' to 'enum mlxsw_reg_bridge_type'. Then it can be used also in SFMR. In addition, align the names of the values to internal documentation. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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93303ff8 |
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27-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum_fid: Configure flooding table type for rFID Using unified bridge model, RITR register no longer configures the rFID used for sub-port RIFs. It needs to be created by software via SFMR. Such FIDs need to be created with a special flood indication using 'SFMR.flood_rsp=1'. It means that for such FIDs, router sub-port flooding table will be used, this table is configured by firmware. Set the above mentioned field as part of FID initialization and FID edition, so then when other fields will be updated in SFMR, this field will store the correct value and will not be overwritten. Add 'flood_rsp' variable to 'struct mlxsw_sp_fid_family', set it to true for rFID and to false for the rest. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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7dd19648 |
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23-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum: Change mlxsw_sp_rif_vlan_fid_op() to be dedicated for FID RIFs The function was designed to configure both VLAN and FID RIFs, but currently the driver does not use VLAN RIFs. Instead, it emulates VLAN RIFs using FID RIFs. As part of the conversion to the unified bridge model, the driver will need to use VLAN RIFs, but they will be configured differently from FID RIFs. As a preparation for this change, rename the function to reflect the fact that it is specific to FID RIFs and do not pass the RIF type as an argument. This leaves mlxsw_reg_ritr_fid_set() unused, so remove it. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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b3820922 |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add support for VLAN RIF as part of RITR register Router interfaces (RIFs) constructed on top of VLAN-aware bridges are of "VLAN" type, whereas RIFs constructed on top of VLAN-unaware bridges of "FID" type. In other words, the RIF type is derived from the underlying FID type. VLAN RIFs are used on top of 802.1Q FIDs, whereas FID RIFs are used on top of 802.1D FIDs. Currently 802.1Q FIDs are emulated using 802.1D FIDs, and therefore VLAN RIFs are emulated using FID RIFs. As part of converting the driver to use unified bridge, 802.1Q FIDs and VLAN RIFs will be used. Add the relevant fields to RITR register, add pack() function for VLAN RIF and rename one field to fit the internal name. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1b1c198c |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Add support for egress FID classification after decapsulation As preparation for unified bridge model, add support for VNI->FID mapping via SVFA register. When performing VXLAN encapsulation, the VXLAN header needs to contain a VNI. This VNI is derived from the FID classification performed on ingress, through which the ingress RIF is also determined. Similarly, when performing VXLAN decapsulation, the FID of the packet needs to be determined. This FID is derived from VNI classification performed during decapsulation. In the old model, both entries (i.e., FID->VNI and VNI->FID) were configured via SFMR.vni. In the new model, where ingress is separated from egress, ingress configuration (VNI->FID) is performed via SVFA, while SFMR only configures egress (FID->VNI). Add 'vni' field to SVFA, add new mapping table - VNI to FID, add new pack() function for VNI mapping and edit the comment in SFMR. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ad9592c0 |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add egress FID field to RITR register RITR configures the router interface table. As preparation for unified bridge model, add egress FID field to RITR. After routing, a packet has to perform a layer-2 lookup using the destination MAC it got from the routing and a FID. In the new model, the egress FID is configured by RITR for both sub-port and FID RIFs. Add 'efid' field to sub-port router interface and update FID router interface related comment. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
27f0b6ce |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Router Egress Interface to VID Register The REIV maps {egress router interface (eRIF), egress_port} -> {vlan ID}. As preparation for unified bridge model, add REIV register for future use. In the past, firmware would take care of the above mentioned mapping, but in the new model this should be done by software using REIV register. REIV register supports a simultaneous update of 256 ports using 'port_page' field. When 'port_page'=0 the records represent ports 0-255, when 'port_page'=1 the records represent ports 256-511 and so on. The register is reserved while using the legacy model. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
48bca94f |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Replace MID related fields in SFGC register SFGC register maps {packet type, bridge type} -> {MID base, table type}. As preparation for unified bridge model, remove 'mid' field and add 'mid_base' field. The MID index (index to PGT table which maps MID to local port list and SMPE index) is a result of 'mid_base' + 'fid_offset'. Using the legacy bridge model, firmware configures 'mid_base'. However, using the new model, software is responsible to configure it via SFGC register. The 'mid_base' is configured per {packet type, bridge type}, for example, for {Unicast, .1Q}, {Broadcast, .1D}. Add the field 'mid_base' to SFGC register and increase the length of the register accordingly. Remove the field 'mid' as currently it is ignored by the device, its use is an old leftover. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
94536249 |
|
19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add flood related field to SFMR register SFMR register creates and configures FIDs. As preparation for unified bridge model, add a required field for future use. The PGT (Port Group) table maps multicast ID (MID) to {local port list, SMPE index} on Spectrum-1 and to {local port list} on the other ASICs. In the legacy model, software did not interact with this table directly. Instead, it was accessed by firmware in response to registers such as SFTR and SMID. In the new model, the SFTR register is deprecated and software has full control over the PGT table using the SMID register. The configuration of MDB entries (using SFD) is unchanged, but flooding configuration is completely different. SFGC register maps {packet type, bridge type} -> {MID base, table type}, then with FID and FID-offset which are configured via SFMR, the MID index is obtained. Add the field 'flood_bridge_type' to SFMR, software can separate between 802.1q FIDs and vFIDs using two types which are supported. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
485c281c |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add VID related fields to SFD register SFD register configures FDB table. As preparation for unified bridge model, add some required fields for future use. In the new model, firmware no longer configures the egress VID, this responsibility is moved to software. For layer 2 this means that software needs to determine the egress VID for both unicast and multicast. For unicast FDB records and unicast LAG FDB records, the VID needs to be set via new fields in SFD - 'set_vid' and 'vid'. Add the two mentioned fields for future use. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
92e4e543 |
|
19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add SMPE related fields to SFMR register SFMR register creates and configures FIDs. As preparation unified bridge model, add some required fields for future use. The device includes two main tables to support layer 2 multicast (i.e., MDB and flooding). These are the PGT (Port Group Table) and the MPE (Multicast Port Egress) table. - PGT is {MID -> (bitmap of local_port, SPME index)} - MPE is {(Local port, SMPE index) -> eVID} In Spectrum-2 and later ASICs, the SMPE index is an attribute of the FID and programmed via new fields in SFMR register - 'smpe_valid' and 'smpe'. Add the two mentioned fields for future use and increase the length of the register accordingly. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
894b98d5 |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Add SMPE related fields to SMID2 register SMID register maps multicast ID (MID) into a list of local ports. As preparation for unified bridge model, add some required fields for future use. The device includes two main tables to support layer 2 multicast (i.e., MDB and flooding). These are the PGT (Port Group Table) and the MPE (Multicast Port Egress) table. - PGT is {MID -> (bitmap of local_port, SPME index)} - MPE is {(Local port, SMPE index) -> eVID} In Spectrum-1, both indexes into the MPE table (local port and SMPE) are derived from the PGT table. Therefore, the SMPE index needs to be programmed as part of the PGT entry via new fields in SMID - 'smpe_valid' and 'smpe'. Add the two mentioned fields for future use and align the callers of mlxsw_reg_smid2_pack() to pass zeros for SMPE fields. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e0f071c5 |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Switch Multicast Port to Egress VID Register The SMPE register maps {egress_port, SMPE index} -> VID. The device includes two main tables to support layer 2 multicast (i.e., MDB and flooding). These are the PGT (Port Group Table) and the MPE (Multicast Port Egress) table. - PGT is {MID -> (bitmap of local_port, SPME index)} - MPE is {(Local port, SMPE index) -> eVID} In Spectrum-1, the index into the MPE table - called switch multicast to port egress VID (SMPE) - is derived from the PGT entry, whereas in Spectrum-2 and later ASICs it is derived from the FID. In the legacy model, software did not interact with this table as it was completely hidden in firmware. In the new model, software needs to populate the table itself in order to map from {Local port, SMPE index} to an egress VID. This is done using the SMPE register. Add the register for future use. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
dd326565 |
|
19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add ingress RIF related fields to SVFA register SVFA register controls the VID to FID mapping and {Port, VID} to FID mapping for virtualized ports. As preparation for unified bridge model, add some required fields for future use. On ingress, after ingress ACL, a packet needs to be classified to a FID. The key for this lookup can be one of: 1. VID. When port is not in virtual mode. 2. {RQ, VID}. When port is in virtual mode. 3. FID. When FID was set by ingress ACL. Since RITR no longer performs ingress configuration, the ingress RIF for the first two entry types needs to be set via new fields in SVFA - 'irif_v' and 'irif'. Add the two mentioned fields for future use and increase the length of the register accordingly. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e459466a |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add ingress RIF related fields to SFMR register SFMR register creates and configures FIDs. As preparation for unified bridge model, add some required fields for future use. On ingress, after ingress ACL, a packet needs to be classified to a FID. The key for this lookup can be one of: 1. VID. When port is not in virtual mode. 2. {RQ, VID}. When port is in virtual mode. 3. FID. When FID was set by ingress ACL. For example, via VR_AND_FID_ACTION. Since RITR no longer performs ingress configuration, the ingress RIF for the last entry type needs to be set via new fields in SFMR - 'irif_v' and 'irif'. Add the two mentioned fields for future use. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
02d23c95 |
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19-Jun-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add 'flood_rsp' field to SFMR register SFMR register creates and configures FIDs. As preparation for unified bridge model, add a field for future use. In the new model, RITR no longer configures the rFID used for sub-port RIFs and it has to be created by software via SFMR. Such FIDs need to be created with special flood indication using 'flood_rsp' field. When set, this bit instructs the device to manage the flooding entries for this FID in a reserved part of the port group table (PGT). Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
87c0a3c6 |
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13-Jun-2022 |
Petr Machata <petrm@nvidia.com> |
mlxsw: Revert "Prepare for XM implementation - LPM trees" This reverts commit 923ba95ea22d ("Merge branch 'mlxsw-spectrum-prepare-for-xm-implementation-lpm-trees'"). Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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725ff532 |
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13-Jun-2022 |
Petr Machata <petrm@nvidia.com> |
mlxsw: Revert "Prepare for XM implementation - prefix insertion and removal" This reverts commit e7086213f7b4 ("Merge branch 'mlxsw-spectrum-prepare-for-xm-implementation-prefix-insertion-and-removal'"). Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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6a4b02b8 |
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13-Jun-2022 |
Petr Machata <petrm@nvidia.com> |
mlxsw: Revert "Introduce initial XM router support" This reverts commit 75c2a8fe8e39 ("Merge branch 'mlxsw-introduce-initial-xm-router-support'"). Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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c4a67a21 |
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04-May-2022 |
Jakub Kicinski <kuba@kernel.org> |
Revert "Merge branch 'mlxsw-line-card-model'" This reverts commit 5e927a9f4b9f29d78a7c7d66ea717bb5c8bbad8e, reversing changes made to cfc1d91a7d78cf9de25b043d81efcc16966d55b3. The discussion is still ongoing so let's remove the uAPI until the discussion settles. Link: https://lore.kernel.org/all/20220425090021.32e9a98f@kernel.org/ Reviewed-by: Ido Schimmel <idosch@nvidia.com> Link: https://lore.kernel.org/r/20220504154037.539442-1-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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135433b3 |
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02-May-2022 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Add "desc" field to SBPR SBPR, or Shared Buffer Pools Register, configures and retrieves the shared buffer pools and configuration. The desc field determines whether the configuration relates to the byte pool or the descriptor pool. Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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c38e9bf3 |
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24-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Extend MDDQ device_info by FW version fields Add FW version fields to MDDQ device_info. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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798e2df5 |
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24-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Extend MDDQ by device_info Extend existing MDDQ register by possibility to query information about devices residing on a line card. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6445eef0 |
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18-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: spectrum: Add port to linecard mapping For each port get slot_index using PMLP register. For ports residing on a linecard, identify it with the linecard by setting mapping using devlink_port_linecard_set() helper. Use linecard slot index for PMTDB register queries. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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5bade5aa |
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18-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Management Binary Code Transfer Register The MBCT register allows to transfer binary INI codes from the host to the management FW by transferring it by chunks of maximum 1KB. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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5290a8ff |
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18-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Management DownStream Device Control Register The MDDC register allows to control downstream devices and line cards. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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505f524d |
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18-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Management DownStream Device Query Register The MDDQ register allows to query the DownStream device properties. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ebf0c534 |
|
18-Apr-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Ports Mapping Event Configuration Register The PMECR register is used to enable/disable event triggering in case of local port mapping change. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e94295e0 |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Add new field to Management General Peripheral Information Register Add new field 'max_modules_per_slot' to provide maximum number of modules that can be connected per slot. This field will always be zero, if 'slot_index' in query request is set to non-zero value, otherwise value in this field will provide maximum modules number, which can be equipped on device inserted at any slot. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
64e65a54 |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: core_env: Pass slot index during PMAOS register write call Pass the slot index down to PMAOS pack helper alongside with the module. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
b691602c |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Extend MGPIR register with new slot fields Extend MGPIR (Management General Peripheral Information Register) with new fields specifying the slot number and number of the slots available on system. The purpose of these fields is: - to support access to MPGIR register on modular system for getting the number of cages, equipped on the line card, inserted at specified slot. In case slot number is set zero, MGPIR will provide the information for the main board. For Top of the Rack (non-modular) system it will provide the same as before. - to provide the number of slots supported by system. This data is relevant only in case slot number is set zero. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
7cb85d3c |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Extend PMMP register with new slot number field Extend PMMP (Port Module Memory Map Properties Register) with new field specifying the slot number. The purpose of this field is to enable overriding the cable/module memory map advertisement. For non-modular systems the 'module' number uniquely identifies the transceiver location. For modular systems the transceivers are identified by two indexes: - 'slot_index', specifying the slot number, where line card is located; - 'module', specifying cage transceiver within the line card. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
655cbb1d |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Extend MCION register with new slot number field Extend MCION (Management Cable IO and Notifications Register) with new field specifying the slot number. The purpose of this field is to support access to MCION register for query cage transceiver on modular system. For non-modular systems the 'module' number uniquely identifies the transceiver location. For modular systems the transceivers are identified by two indexes: - 'slot_index', specifying the slot number, where line card is located; - 'module', specifying cage transceiver within the line card. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
89dd6fcd |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Extend MCIA register with new slot number field Extend MCIA (Management Cable Info Access Register) with new field specifying the slot number. The purpose of this field is to support access to MCIA register for reading cage cable information on modular system. For non-modular systems the 'module' number uniquely identifies the transceiver location. For modular systems the transceivers are identified by two indexes: - 'slot_index', specifying the slot number, where line card is located; - 'module', specifying cage transceiver within the line card. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
c6e6ad70 |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Extend MTBR register with new slot number field Extend MTBR (Management Temperature Bulk Register) with new field specifying the slot number. The purpose of this field is to support access to MTBR register for reading temperature sensors on modular system. For non-modular systems the 'sensor_index' uniquely identifies the cage sensors. For modular systems the sensors are identified by two indexes: - 'slot_index', specifying the slot number, where line card is located; - 'sensor_index', specifying cage sensor within the line card. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
d30bed29 |
|
11-Apr-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Extend MTMP register with new slot number field Extend MTMP (Management Temperature Register) with new field specifying the slot index. The purpose of this field is to support access to MTMP register for reading temperature sensors on modular systems. For non-modular systems the 'sensor_index' uniquely identifies the cage sensors, while 'slot_index' is always 0. For modular systems the sensors are identified by: - 'slot_index', specifying the slot index, where line card is located; - 'sensor_index', specifying cage sensor within the line card. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
8fe96f58 |
|
02-Mar-2022 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Fix packing of router interface counters The function mlxsw_reg_ritr_counter_pack() formats a register to configure a router interface (RIF) counter. The parameter `egress' determines whether an ingress or egress counter is to be configured. RITR, the register in question, has two sets of counter-related fields: one for ingress, one for egress. When setting values of the fields, the function sets the proper counter index field, but when setting the counter type, it always sets the egress field. Thus configuration of ingress counters is broken, and in fact an attempt to configure an ingress counter mangles a previously configured egress counter. This was never discovered, because there is currently no way to enable ingress counters on a router interface, only the egress one. Fix in an obvious way. Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f881c4ab |
|
22-Feb-2022 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: core: Add support for OSFP transceiver modules The driver can already dump the EEPROM contents of QSFP-DD transceiver modules via its ethtool_ops::get_module_info() and ethtool_ops::get_module_eeprom() callbacks. Add support for OSFP transceiver modules by adding their SFF-8024 Identifier Value (0x19). This is required for future NVIDIA Spectrum-4 based systems that will be equipped with OSFP transceivers. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
719fc066 |
|
22-Feb-2022 |
Vadim Pasternak <vadimp@nvidia.com> |
mlxsw: reg: Add "mgpir_" prefix to MGPIR fields comments Do the same as for other registers and have "mgpir_" prefix for the MGPIR fields. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
636d3ad2 |
|
27-Jan-2022 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: core: Consolidate trap groups to a single event group For event traps which are used in core, avoid having a separate trap group for each event. Instead of that introduce a single core event trap group and use it for all event traps. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
0d31441e |
|
25-Jan-2022 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: reg: Add Port Module Type Mapping register Add the Port Module Type Mapping (PMTP) register. It will be used by subsequent patches to query port module types and forbid certain configurations based on the port module's type. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
78cf4b92 |
|
25-Jan-2022 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: spectrum_ethtool: Add support for two new link modes As part of a process for supporting a new system with RJ45 connectors, 100BaseT and 1000BaseT link modes need to be supported. Add support for these two link modes by adding the two corresponding bits in PTYS (Port Type and Speed) register. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
47354021 |
|
06-Jan-2022 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: spectrum: Extend to support Spectrum-4 ASIC Extend existing driver for Spectrum, Spectrum-2 and Spectrum-3 ASICs to support Spectrum-4 ASIC as well. Currently there is no released firmware version for Spectrum-4, so the driver is not enforcing a minimum version. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
e25c060c |
|
19-Dec-2021 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: reg: Extend MFDE register with new events and parameters Extend the Monitoring Firmware Debug (MFDE) register with new events and their related parameters. These events will be utilized by devlink-health in the next patch. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
cbbd5fff |
|
19-Dec-2021 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: Fix naming convention of MFDE fields Currently, the MFDE register field names are using the convention: reg_mfde_<NAME_OF_FIELD>, and do not consider the name of the MFDE event. Fix the field names so they fit the more accurate convention: reg_mfde_<NAME_OF_EVENT>_<NAME_OF_FIELD>. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4b08c3e6 |
|
14-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add a function to fill IPv6 unicast FDB entries Add a function to fill IPv6 unicast FDB entries. Use the common function for common fields. Unlike IPv4 entries, the underlay IP address is not filled in the register payload, but instead a pointer to KVDL is used. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1fd85416 |
|
14-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Split handling of FDB tunnel entries between address families Currently, the function which adds/removes unicast tunnel FDB entries is shared between IPv4 and IPv6, while for IPv6 it warns because there is no support for it. The code for IPv6 will be more complicated because it needs to allocate/release a KVDL pointer for the underlay IPv6 address. As a preparation for IPv6 underlay support, split the code according to address family. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
51ef6b00 |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Use Switch Multicast ID Register Version 2 The SMID-V2 register maps Multicast ID (MID) into a list of local ports. It is a new version of SMID in order to support 1024 bits of local_port. Add SMID-V2 register and use it instead of SMID. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e86ad8ce |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Use Switch Flooding Table Register Version 2 The SFTR-V2 register is used for flooding packet replication. It is a new version of SFTR in order to support 1024 bits of local_port. Add SFTR-V2 register and use it instead of SFTR. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f8538aec |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Add support for more than 256 ports in SBSR register Add 'port_page' field in SBSR to be able to query occupancy of more than 256 ports. The field determines the range of the ports specified in the 'ingress_port_mask' and 'egress_port_mask' bit masks: >From '256 * port_page' to '256 * port_page + 255'. For each local port, the appropriate port page is used. A query is never performed for a port range that spans multiple port pages. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c934757d |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Use u16 for local_port field instead of u8 Currently, local_port field is saved as u8, which means that maximum 256 ports can be used. As preparation for Spectrum-4, which will support more than 256 ports, local_port field should be extended. Save local_port as u16 to allow use of additional ports. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
242e696e |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Adjust PPCNT register to support local port 255 Local port 255 has a special meaning in PPCNT register, it is used to refer to all local ports. This wild card ability is not currently used by the driver. Special casing local port 255 in Spectrum-4 systems where it is a valid port is going to be a problem. Work around this issue by adding and always setting the 'lp_gl' bit which instructs the device's firmware to treat this local port like an ordinary port. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
da56f1a0 |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Increase 'port_num' field in PMTDB register 'port_num' field is used to indicate the local port value which can be assigned to a module. Increase the field from 8 bits to 10 bits in order to support more than 255 ports. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
fd24b29a |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Align existing registers to use extended local_port field Add support for 10-bit local ports in device registers by making use of the MLXSW_ITEM32_LP() macro that was added in the previous patch. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b25dea48 |
|
01-Dec-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Remove unused functions The functions mlxsw_reg_sfd_uc_unpack() and mlxsw_reg_sfd_uc_lag_unpack() are not used. Remove them. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d25d7fc3 |
|
25-Oct-2021 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: reg: Add MAC profile ID field to RITR register Add MAC profile ID field to RITR register so that it could be used for associating a RIF with a MAC profile ID by a later patch. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
6242b0a9 |
|
13-Oct-2021 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Add ecn_marked_tc to Per-TC Congestion Counters The PPCNT register retrieves per port performance counters. The ecn_marked_tc field in per-TC Congestion counter group contains a count of packets marked as ECN or potentially marked as ECN. Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
fc372cc0 |
|
13-Oct-2021 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Rename MLXSW_REG_PPCNT_TC_CONG_TC to _CNT The name does not make sense as it is. Clearly there is a typo and the suffix should have been _CNT, like the other enumerators. Fix accordingly. Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
b063e065 |
|
13-Oct-2021 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Fix a typo in a group heading There is no such thing as "traffic group". The group that this is a heading of is "per traffic class counters". Fix the heading. Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
fc53f5fb |
|
06-Oct-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add Management Cable IO and Notifications register Add the Management Cable IO and Notifications register. It will be used to retrieve the power mode status of a module in subsequent patches and whether a module is present in a cage or not. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
f10ba086 |
|
06-Oct-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add Port Module Memory Map Properties register Add the Port Module Memory Map Properties register. It will be used to set the power mode of a module in subsequent patches. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
36c2ab89 |
|
23-Sep-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add support for ritr_loopback_ipip6_pack() The RITR register is used to configure the router interface table. For IP-in-IP, it stores the underlay source IP address for encapsulation and also the ingress RIF for the underlay lookup. Add support for IPv6 IP-in-IP configuration. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c729ae8d |
|
23-Sep-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add support for ratr_ipip6_entry_pack() The RATR register is used to configure the Router Adjacency (next-hop) Table. For IP-in-IP entry, underlay destination IPv4 is saved as part of this register and underlay destination IPv6 is saved by RIPS register and RATR saves pointer to it. Add function for setting IPv6 IP-in-IP configuration. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a917bb27 |
|
23-Sep-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add support for rtdp_ipip6_pack() The RTDP register is used for configuring the tunnel decapsulation properties of NVE and IP-in-IP. Linux tunnels verify packets before decapsulation based on the packet's source IP, which must match tunnel remote IP. RTDP is used to configure decapsulation so that it filters out packets that are not IPv6 or have the wrong source IP or wrong GRE key. For IP-in-IP entry, source IPv4 is saved as part of this register and source IPv6 is saved by RIPS register and RTDP saves pointer to it. Create common function for configuring both IPv4 and IPv6 and add dedicated functions for each protocol. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
dd8a9552 |
|
23-Sep-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Router IP version Six Register The RIPS register is used to store IPv6 addresses for use by the NVE and IP-in-IP. For IPv6 underlay support, RATR register needs to hold a pointer to the remote IPv6 address for encapsulation and RTDP register needs to hold a pointer to the local IPv6 address for decapsulation check. Add the required register for saving IPv6 addresses. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8f4ebdb0 |
|
15-Sep-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: Make PMAOS pack function more generic The PMAOS register has enable bits (e.g., PMAOS.ee) that allow changing only a subset of the fields, which is exactly what subsequent patches will need to do. Instead of passing multiple arguments to its pack function, only pass the module index and let the rest be set by the different callers. No functional changes intended. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ef23841b |
|
15-Sep-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add fields to PMAOS register The Ports Module Administrative and Operational Status (PMAOS) register configures and retrieves the per-module status. Extend it with fields required to support various module settings such as reset and power mode. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
cd92d79d |
|
14-Sep-2021 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Remove PMTM register It is not used anymore, remove it. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
78f824b3 |
|
14-Sep-2021 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Port Module To local DataBase Register The PMTDB register allows to query the possible module<->local port mapping than can be used in PMLP. It does not represent the actual/current mapping of the local to module. Actual mapping is only defined by PMLP. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ed403777 |
|
14-Sep-2021 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Port Local port to Label Port mapping Register The PLLP register returns the mapping from Local Port into Label Port. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
cecefb3a |
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21-Jun-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Document possible MCIA status values Will be used to emit meaningful messages to user space via extack in a subsequent patch. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d51ea60e |
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21-Jun-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add bank number to MCIA register Add bank number to MCIA (Management Cable Info Access) register in order to allow access to banked pages on EEPROMs using CMIS (Common Management Interface Specification) memory map. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
314dbb19 |
|
08-Jun-2021 |
Mykola Kostenok <c_mykolak@nvidia.com> |
mlxsw: reg: Extend MTMP register with new threshold field Extend Management Temperature (MTMP) register with new field specifying the maximum temperature threshold. Extend mlxsw_reg_mtmp_unpack() function with two extra arguments, providing high and maximum temperature thresholds. For modules, these thresholds correspond to critical and emergency thresholds that are read from the module's EEPROM. Signed-off-by: Mykola Kostenok <c_mykolak@nvidia.com> Acked-by: Vadim Pasternak <vadimp@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
28bc8248 |
|
19-May-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add inner packet fields to RECRv2 register The RECRv2 register is used for setting up the router's ECMP hash configuration. Extend it with inner packet fields to allow the ECMP hash to be calculated based on inner flow information. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9d23d3eb |
|
19-May-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: spectrum_router: Move multipath hash configuration to a bitmap Currently, the multipath hash configuration is written directly to the register payload. While this is OK for the two currently supported policies, it is going to be hard to follow when more policies and more packet fields are added. Instead, set the required headers and fields in a bitmap and then dump it to the register payload. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
306b9228 |
|
06-Jun-2021 |
Petr Machata <petrm@nvidia.com> |
mlxsw: reg: Spectrum-3: Enforce lowest max-shaper burst size of 11 A max-shaper is the HW component responsible for delaying egress traffic above a configured transmission rate. Burst size is the amount of traffic that is allowed to pass without accounting. The burst size value needs to be such that it can be expressed as 2^BS * 512 bits, where BS lies in a certain ASIC-dependent range. mlxsw enforces that this holds before attempting to configure the shaper. The assumption for Spectrum-3 was that the lower limit of BS would be 5, like for Spectrum-1. But as of now, the limit is still 11. Therefore fix the driver accordingly, so that incorrect values are rejected early with a proper message. Fixes: 23effa2479ba ("mlxsw: reg: Add max_shaper_bs to QoS ETS Element Configuration") Reported-by: Maksym Yaremchuk <maksymy@nvidia.com> Signed-off-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
75d495b0 |
|
24-Mar-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Add Router Adjacency Table Activity Dump Register The RATRAD register is used to dump and optionally clear activity bits of router adjacency table entries. Will be used by the next patch to query and clear the activity of nexthop buckets in a resilient nexthop group. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d8f4da73 |
|
16-Mar-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Switch Port Egress VLAN EtherType Register SPEVET configures which EtherType to push at egress for packets incoming through a local port for which 'SPVID.egr_et_set' is set. The next patches will use SPEVET to configure EtherType 0x88A8 and 0x8100 for local ports member in 802.1ad and 802.1q bridges, respectively. This allows using dual VxLAN bridges (802.1d and 802.1ad at the same time). Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1b35293b |
|
16-Mar-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add egr_et_set field to SPVID SPVID.egr_et_set=1 means that when VLAN is pushed at ingress (for untagged packets or for QinQ push mode) then the EtherType is decided at the egress port. The next patches will use this field for VxLAN devices (tunnel port) in order to allow using dual VxLAN bridges (802.1d and 802.1ad at the same time). Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fa3faeb7 |
|
11-Mar-2021 |
Ido Schimmel <idosch@nvidia.com> |
mlxsw: reg: Extend mirroring registers with probability rate field The MPAR and MPAGR registers are used to configure the binding between the mirroring trigger (e.g., received packet) and the SPAN agent. Add probability rate field, which will allow us to support sampling by mirroring to the CPU. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4734a750 |
|
10-Mar-2021 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: Adjust some MFDE fields shift and size to fw implementation MFDE.irisc_id and MFDE.event_id were adjusted according to what is actually implemented in firmware. Adjust the shift and size of these fields in mlxsw as well. Note that the displacement of the first field is not a regression. It was always incorrect and therefore reported "0". Signed-off-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ff12ba3a |
|
10-Mar-2021 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: reg: Extend MFDE register with new log_ip field Extend MFDE (Monitoring FW Debug) register with new field specifying the instruction pointer that triggered the CR space timeout. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
675e5a1e |
|
10-Mar-2021 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Fix comment about slot_index field in PMAOS register The comment did not include the register name. Add `pmaos` to align the comment with other comments. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ae9b24dd |
|
25-Feb-2021 |
Danielle Ratson <danieller@nvidia.com> |
mlxsw: spectrum_ethtool: Add an external speed to PTYS register Currently, only external bits are added to the PTYS register, whereas there is one external bit that is wrongly marked as internal, and so was recently removed from the register. Add that bit to the PTYS register again, as this bit is no longer internal. Its removal resulted in '100000baseLR4_ER4/Full' link mode no longer being supported, causing a regression on some setups. Fixes: 5bf01b571cf4 ("mlxsw: spectrum_ethtool: Remove internal speeds from PTYS register") Signed-off-by: Danielle Ratson <danieller@nvidia.com> Reported-by: Eddie Shklaer <eddies@nvidia.com> Tested-by: Eddie Shklaer <eddies@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
06925466 |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Router LPM Cache Enable Register The RLPMCE allows disabling the LPM cache. Can be changed on the fly. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
edb47f3d |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Router LPM Cache ML Delete Register The RLCMLD register is used to bulk delete the XLT-LPM cache ML entries. This can be used by SW when L is increased or decreased, thus need to remove entries with old ML values. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
e35e8046 |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add XM Router M Table Register The XRMT configures the M-Table for the XLT-LPM. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
ec54677e |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add XM Lookup Table Query Register The XLTQ is used to query HW for XM-related info. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
087489dc |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Router XLT M select Register The RXLTM configures and selects the M for the XM lookups. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
6100fbf1 |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Router XLT Enable Register The RXLTE enables XLT (eXtended Lookup Table) LPM lookups if a capable XM is present on the system. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
be6ba3b6 |
|
14-Dec-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add XM Direct Register The XMDR allows direct access to the XM device via the switch. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
598874c8 |
|
08-Dec-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add support for tunnel port in SPVID register Add spvid_tport field which indicates if the port is tunnel port. When spvid_tport is true, local_port field supposed to be tunnel port type. It will be used to configure which Ethertype will be used when VLAN is pushed at ingress for tunnel port. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c1c32a79 |
|
08-Dec-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Switch Port VLAN Stacking Register SPVTR register configures the VLAN mode of the port to enable VLAN stacking. It will be used to configure VxLAN to push VLAN to the decapsulated packet. Without this setting, Spectrum-2 overtakes the VLAN tag of decapsulated packet for bridging. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
02c3b5c5 |
|
08-Dec-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Use one enum for all registers that contain tunnel_port field Currently SFN, TNUMT and TNPC registers use separate enums for tunnel_port. Create one enum with a neutral name and use it. Remove the enums that are not currently required. The next patches add two more registers that contain tunnel_port field, the new enum can be used for them also. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
3ae7a65b |
|
29-Nov-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Make EtherType configurable when pushing VLAN at ingress Currently, when pushing a PVID at ingress, mlxsw always uses 802.1q EtherType. Make this EtherType configurable by extending mlxsw_sp_port_pvid_set() with an EtherType argument. This is a preparation for QinQ support, that needs to push a PVID with 802.1ad EtherType. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
2a5a290d |
|
29-Nov-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add et_vlan field to SPVID register et_vlan field is used to configure which EtherType is used when VLAN is pushed at ingress (for untagged packets or for QinQ push mode). It will be used to configure tagging with ether_type1 (i.e., 0x88A8) for QinQ mode. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
7e9a6620 |
|
29-Nov-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Switch Port VLAN Classification Register SPVC configures the port to identify packets as untagged / single tagged / double tagged packets based on the packet EtherTypes. It will be used to classify 802.1q packets as untagged and 802.1ad packets as tagged when received by ports member in a 802.1ad bridge. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
1a7fcdf7 |
|
10-Nov-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Allow to pass NULL pointer to mlxsw_reg_ralue_pack4/6() In preparation for the change that is going to be done in the next patch, allow to pass NULL pointer to mlxsw_reg_ralue_pack4() and mlxsw_reg_ralue_pack6() helpers. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
0c1d6b26 |
|
10-Nov-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: spectrum_router: Pass destination IP as a pointer to mlxsw_reg_ralue_pack4() Instead of passing destination IP as a u32 value, pass it as pointer to u32. Avoid using local variable for the pointer store. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
#
fb281f24 |
|
01-Nov-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add XRALXX Registers Add a couple of registers used to manipulate LPM trees on XM: The XRALTA is used to allocate the XLT LPM trees. The XRALST is used to set and query the structure of an XLT LPM tree. The XRALTB register is used to bind virtual router and protocol to an allocated LPM tree. Since the XM registers are identical to the legacy router registers with a fixed offset, re-use their pack functions. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
05cf5828 |
|
27-Sep-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Update module's settings when module is plugged in Module temperature warning events are enabled for modules that have a temperature sensor and configured according to the temperature thresholds queried from the module. When a module is unplugged we are guaranteed not to get temperature warning events. However, when a module is plugged in we need to potentially update its current settings (i.e., event enablement and thresholds). Register to port module plug/unplug events and update module's settings upon plug in events. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f21b1a64 |
|
27-Sep-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Enable temperature event for all supported port module sensors MTWE (Management Temperature Warning Event) is triggered for sensors whose temperature event enable bit is enabled in the MTMP register. Enable events for all the modules that have a temperature sensor. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
943585c9 |
|
27-Sep-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: Update transceiver_overheat counter according to MTWE MTWE (Management Temperature Warning Event) is triggered when module's temperature is higher than its threshold. Register for MTWE events and increase the module's overheat counter when its corresponding sensor goes above the configured threshold. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
02d33b45 |
|
27-Sep-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Ports Module Administrative and Operational Status Register PMAOS register configures and retrieves the per module status. The register is used also for enabling event for status change. It will be used to enable PMPE (Port Module Plug/Unplug) event. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e7d62a3c |
|
27-Sep-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Port Module Plug/Unplug Event Register PMPE register reports any operational status change of a module. It will be used for enabling temperature warning event when a module is plugged in. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
946bd435 |
|
27-Sep-2020 |
Amit Cohen <amcohen@nvidia.com> |
mlxsw: reg: Add Management Temperature Warning Event Register Add MTWE (Management Temperature Warning Event) register, which is used for over temperature warning. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7d83ee11 |
|
15-Sep-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: core: Introduce fw_fatal health reporter Introduce devlink health reporter to report FW fatal events. Implement the event listener using MFDE trap and enable the events to be propagated using MFGD register configuration. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
191c0c22 |
|
15-Sep-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Monitoring FW General Debug Register Introduce MFGD register that is used to configure firmware debugging. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
6ddac9dc |
|
15-Sep-2020 |
Jiri Pirko <jiri@nvidia.com> |
mlxsw: reg: Add Monitoring FW Debug Register Introduce MFDE register that is passed through MFDE trap in case of fatal FW event. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5bf01b57 |
|
23-Aug-2020 |
Danielle Ratson <danieller@mellanox.com> |
mlxsw: spectrum_ethtool: Remove internal speeds from PTYS register The PTYS register is used to report and configure the port type and speed. Currently, internal bits in the register are used the same way other bits are used. Using the internal bits can cause bad parameter firmware errors. For example, trying to write to internal bit 25 returns: EMAD reg access failed (tid=53e2bffa00004310,reg_id=5004(ptys),type=write,status=7(bad parameter)) Remove the internal bits from the PTYS register, so that it is no longer possible to pass them to firmware. Signed-off-by: Danielle Ratson <danieller@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
6687e953 |
|
03-Aug-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_trap: Add early_drop trap As previously explained, packets that are dropped due to buffer related reasons (e.g., tail drop, early drop) can be mirrored to the CPU port. These packets are then trapped with one of the "mirror session" traps and their CQE includes the reason for which the packet was mirrored. Register with devlink a new trap, early_drop, and initialize the corresponding Rx listener with the appropriate mirror reason. Return an error in case user tries to change the traps' action, as this is not supported. Since Spectrum-1 does not support these traps, the above is only done for Spectrum-2 onwards. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ec4f5b36 |
|
28-Jul-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use different trap group for externally routed packets Cited commit mistakenly removed the trap group for externally routed packets (e.g., via the management interface) and grouped locally routed and externally routed packet traps under the same group, thereby subjecting them to the same policer. This can result in problems, for example, when FRR is restarted and suddenly all transient traffic is trapped to the CPU because of a default route through the management interface. Locally routed packets required to re-establish a BGP connection will never reach the CPU and the routing tables will not be re-populated. Fix this by using a different trap group for externally routed packets. Fixes: 8110668ecd9a ("mlxsw: spectrum_trap: Register layer 3 control traps") Reported-by: Alex Veber <alexve@mellanox.com> Tested-by: Alex Veber <alexve@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f152b41b |
|
28-Jul-2020 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: core: Add support for temperature thresholds reading for QSFP-DD transceivers Allow QSFP-DD transceivers temperature thresholds reading for hardware monitoring and thermal control. For this type, the thresholds are located in page 02h according to the "Module and Lane Thresholds" description from Common Management Interface Specification. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6af496ad |
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28-Jul-2020 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: core: Add ethtool support for QSFP-DD transceivers The Quad Small Form Factor Pluggable Double Density (QSFP-DD) hardware specification defines a form factor that supports up to 400 Gbps in aggregate over an 8x50-Gbps electrical interface. The QSFP-DD supports both optical and copper interfaces. Implementation is based on Common Management Interface Specification; Rev 4.0 May 8, 2019. Table 8-2 "Identifier and Status Summary (Lower Page)" from this spec defines "Id and Status" fields located at offsets 00h - 02h. Bit 2 at offset 02h ("Flat_mem") specifies QSFP EEPROM memory mode, which could be "upper memory flat" or "paged". Flat memory mode is coded "1", and indicates that only page 00h is implemented in EEPROM. Paged memory is coded "0" and indicates that pages 00h, 01h, 02h, 10h and 11h are implemented. Pages 10h and 11h are currently not supported by the driver. "Flat" memory mode is used for the passive copper transceivers. For this type only page 00h (256 bytes) is available. "Paged" memory is used for the optical transceivers. For this type pages 00h (256 bytes), 01h (128 bytes) and 02h (128 bytes) are available. Upper page 01h contains static advertising field, while upper page 02h contains the module-defined thresholds and lane-specific monitors. Extend enumerator 'mlxsw_reg_mcia_eeprom_module_info_id' with additional field 'MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID'. This field is used to indicate for QSFP-DD transceiver type which memory mode is to be used. Expose 256 bytes buffer for QSFP-DD passive copper transceiver and 512 bytes buffer for optical. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fbf0f5d1 |
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15-Jul-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add policer bandwidth limits Add policer bandwidth limits for both rate and burst size so that they could be enforced by a later patch. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
47e4b162 |
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14-Jul-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Increase trap identifier to 10 bits The trap identifier was increased to 10 bits in new versions of the Programmer's Reference Manual (PRM). Increase it accordingly in the Host PacKet Trap (HPKT) register and in the Completion Queue Element (CQE). This is significant for subsequent patches that will introduce trap identifiers which utilize the extended range. Signed-off-by: Amit Cohen <amitc@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
95c68833 |
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14-Jul-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: add mirroring_pid_base to MOGCR register Allow setting mirroring_pid_base using MOGCR register. Signed-off-by: Amit Cohen <amitc@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ef8d57e6 |
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14-Jul-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Add session_id and pid to MPAT register Allow setting session_id and pid as part of port analyzer configurations. Signed-off-by: Amit Cohen <amitc@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c0e3969b |
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10-Jul-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Add Monitoring Port Analyzer Global Register This register is used for global port analyzer configurations. Signed-off-by: Amit Cohen <amitc@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
951b84d4 |
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10-Jul-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Add Monitoring Mirror Trigger Enable Register This register is used to configure the mirror enable for different mirror reasons. Signed-off-by: Amit Cohen <amitc@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1bd06938 |
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29-Jun-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Port Diagnostics Database Register The PDDR register enables to read the Phy debug database. Signed-off-by: Amit Cohen <amitc@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8110668e |
|
29-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_trap: Register layer 3 control traps In a similar fashion to layer 2 control traps, register layer 3 control traps with devlink. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1e292f5c |
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29-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_trap: Move layer 3 exceptions to exceptions trap group The layer 3 exceptions are still subject to the same trap policer, so nothing changes, but user space can choose to assign a different one. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9785b92b |
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25-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Add packet traps for BFD packets Bidirectional Forwarding Detection (BFD) provides "low-overhead, short-duration detection of failures in the path between adjacent forwarding engines" (RFC 5880). This is accomplished by exchanging BFD packets between the two forwarding engines. Up until now these packets were trapped via the general local delivery (i.e., IP2ME) trap which also traps a lot of other packets that are not as time-sensitive as BFD packets. Expose dedicated traps for BFD packets so that user space could configure a dedicated policer for them. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
500769be |
|
25-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Move all trap groups under the same enum After the previous patch the split is no longer necessary and all the trap groups can be moved under the same enum. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
03cb0ce0 |
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25-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: switchx2: Move SwitchX-2 trap groups out of main enum The number of Spectrum trap groups is not infinite, but two identifiers are occupied by SwitchX-2 specific trap groups. Free these identifiers by moving them out of the main enum. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d322309d |
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25-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use separate trap group for FID miss When a packet enters the device it is classified to a filtering identifier (FID) based on the ingress port and VLAN. The FID miss trap is used to trap packets for which a FID could not be found. In mlxsw this trap should only be triggered when a port is enslaved to an OVS bridge and a matching ACL rule could not be found, so as to trigger learning. These packets are therefore completely unrelated to packets hitting local routes and should be in a different group. Move them. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
412df3d1 |
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25-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Rename IPv6 ND trap group The IPv6 Neighbour Discovery (ND) group will be used for various IPv6 packets, not all of which fall under the definition of ND, so rename it to "IPV6" which is more appropriate. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
3c2d8a04 |
|
25-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use dedicated trap group for ACL trap Packets that are trapped via tc's trap action are currently subject to the same policer as packets hitting local routes. The latter are critical to the correct functioning of the control plane, while the former are mainly used for traffic inspection. Split the ACL trap to a separate group with its own policer. Use a higher priority for these traps than for traps using mirror action (e.g., ARP, IGMP). Otherwise, packets matching both traps will not be forwarded in hardware (because of trap action) and also not forwarded in software because they will be marked with 'offload_fwd_mark'. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ce3c3bf0 |
|
24-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use dedicated trap group for sampled packets The rate with which packets are sampled is determined by user space, so there is no need to associate such packets with a policer. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
32446438 |
|
24-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Rename ARP trap group The ARP trap group will be used for IPv6 ND traps in the next patch, so rename it to "NEIGH_DISCOVERY" which is more appropriate. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
99129069 |
|
24-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use same trap group for MLD and IGMP packets Both packet types are needed for the same reason (multicast snooping), so associate them with the same trap group. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
debb7af6 |
|
24-May-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Rename IGMP trap group The IGMP trap group will be used for MLD traps in the next patch, so rename it to "MC_SNOOPING" which is more appropriate. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b7f03b0b |
|
19-Apr-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Increase register field length to 13 bits The Infrastructure Entry Delete Register (IEDR) is used to delete entries stored in the KVD linear database. Currently, it is only possible to delete entries of size up to 2048. Future firmware versions will support deletion of entries of size up to 4096. Increase the size of the field so that the driver will be able to perform such deletions in the future, when required. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d12d8468 |
|
30-Mar-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_trap: Switch to use correct packet trap group Some packet traps are currently exposed to user space as being member of "l3_drops" trap group, but internally they are member of a different group. Switch these traps to use the correct group so that they are all subject to the same policer, as exposed to user space. Set the trap priority of packets trapped due to loopback error during routing to the lowest priority. Such packets are not routed again by the kernel and therefore should not mask other traps (e.g., host miss) that should be routed. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
2b84d7c3 |
|
30-Mar-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Extend QPCR register The QoS Policer Configuration Register (QPCR) is used to configure hardware policers. Extend this register with following fields and defines which will be used by subsequent patches: 1. Violate counter: reads number of packets dropped by the policer 2. Clear counter: to ensure we start counting from 0 3. Rate and burst size limits Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
cb851c01 |
|
15-Mar-2020 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Increase register field length to 31 bits The cited commit set a value of 2^31-1 in order to "disable" the shaper on a given a port. However, the length of the maximum shaper rate field was not updated from 28 bits to 31 bits, which means ports are still limited to ~268Gbps despite supporting speeds of 400Gbps. Fix this by increasing the field's length. Fixes: 92afbfedb77d ("mlxsw: reg: Increase MLXSW_REG_QEEC_MAS_DIS") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ec4a514a |
|
27-Feb-2020 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Update module_type values in PMTM register and map them to width There are couple new values that PMTM register can return in module_type field. Add them and map them to module width in mlxsw_core_module_max_width(). Fix the existing names on the way. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
648e53ca |
|
26-Feb-2020 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum_switchdev: Optimize SFN records processing Currently, only one SFN query is done from repetitive work at a time, processing 64 entries. Another work iteration is scheduled in 100ms, that means that the max rate of learned FDB entries is limited to 6400/s. That is slow. Fix this by doing 2 optimizations: 1) Run 10 SFN queries at a time. 2) In case the SFN is not drained, schedule work with 0 delay to allow to continue processing rest of the records. On a testing setup with 500K entries the time to process decreased from 870secs to 10secs. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Tested-by: Alex Kushnarov <alexanderk@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
45dbee09 |
|
24-Feb-2020 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum_trap: Add ACL devlink-trap support Add the trap group used to report ACL drops. Setup the trap IDs for ingress/egress flow action drop. Register the two packet traps associated with ACL trap group with devlink during driver initialization. As these are "source traps", set the disabled trap group to be the dummy, discarding as many packets in HW as possible. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e6125230 |
|
24-Feb-2020 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum_trap: Introduce dummy group with thin policer For "source traps" it is not possible to change HPKT action to discard. But there is still need to disallow packets arriving to CPU as much as possible. Handle this by introduction of a "dummy group". It has a "thin" policer, which passes as less packets to CPU as possible. The rest is going to be discarded there. The "dummy group" is to be used later on by ACL trap (which is a "source trap"). Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
92afbfed |
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24-Jan-2020 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Increase MLXSW_REG_QEEC_MAS_DIS As the port speeds grow, the current value of "unlimited shaper", 200000000Kbps, might become lower than the actually supported speeds. Bump it to the maximum value that fits in the corresponding QEEC field, which is about 2.1Tbps. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
23effa24 |
|
24-Jan-2020 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add max_shaper_bs to QoS ETS Element Configuration The QEEC register configures scheduling elements. One of the bits of configuration is the burst size to use for the shaper installed on the element. Add the necessary fields to support this configuration. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a318bf62 |
|
19-Jan-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: Add tunnel devlink-trap support Add the trap IDs and trap group used to report tunnel drops. Register tunnel packet traps and associated tunnel trap group with devlink during driver initialization. Signed-off-by: Amit Cohen <amitc@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
839607e2 |
|
19-Jan-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Add Tunneling IPinIP Decapsulation ECN Mapping Register This register configures the actions that are done during IPinIP decapsulation based on the ECN bits. Signed-off-by: Amit Cohen <amitc@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
20174900 |
|
19-Jan-2020 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: reg: Add Tunneling IPinIP Encapsulation ECN Mapping Register This register performs mapping from overlay ECN to underlay ECN during IPinIP encapsulation. Signed-off-by: Amit Cohen <amitc@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d8446884 |
|
29-Dec-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add QoS Port DSCP to Priority Mapping Register Add QPDP. This register controls the port default Switch Priority and Color. The default Switch Priority and Color are used for frames where the trust state uses default values. Currently there are two cases where this applies: a port is in trust-PCP state, but a packet arrives untagged; and a port is in trust-DSCP state, but a non-IP packet arrives. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
acca789a |
|
29-Dec-2019 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use dedicated policer for VRRP packets Currently, VRRP packets and packets that hit exceptions during routing (e.g., MTU error) are policed using the same policer towards the CPU. This means, for example, that misconfiguration of the MTU on a routed interface can prevent VRRP packets from reaching the CPU, which in turn can cause the VRRP daemon to assume it is the Master router. Fix this by using a dedicated policer for VRRP packets. Fixes: 11566d34f895 ("mlxsw: spectrum: Add VRRP traps") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reported-by: Alex Veber <alexve@mellanox.com> Tested-by: Alex Veber <alexve@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9cf9b925 |
|
18-Dec-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: spectrum: Rename MLXSW_REG_QEEC_HIERARCY_* enumerators These enums want to be named MLXSW_REG_QEEC_HIERARCHY_, but due to a typo lack the second H. That is confusing and complicates searching. But actually the enumerators should be named _HR_, because that is how their enum type is called. So rename them as appropriate. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
dbc684f1 |
|
07-Nov-2019 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: Add layer 3 devlink-trap support Add the trap IDs and trap group used to report layer 3 drops. Register layer 3 packet traps and associated layer 3 trap group with devlink during driver initialization. Signed-off-by: Amit Cohen <amitc@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a513b1a5 |
|
31-Oct-2019 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Port Module Type Mapping Register The PMTM allows query or configuration of module types. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Shalom Toledo <shalomt@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
94e76837 |
|
31-Oct-2019 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Extend PMLP tx/rx lane value size to 4 bits The tx/rx lane fields got extended to 4 bits, update the reg field description accordingly. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Shalom Toledo <shalomt@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5075066a |
|
30-Oct-2019 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Increase size of MPAR register In new firmware versions this register is extended with a sampling rate for Spectrum-2 and future ASICs. Increase the size of the register to ensure the field is initialized to 0 which means every packet is mirrored. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f366cd2a |
|
21-Oct-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: reg: Add macro for getting QSFP module EEPROM page number Provide a macro for getting QSFP module EEPROM page number from the optional upper page number row offset, specified in request. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
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#
5bd29b9b |
|
12-Oct-2019 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum: Add support for 400Gbps (50Gbps per lane) link modes Extend speed support with 400Gbps Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5cfa030a |
|
06-Oct-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: reg: Extend MGPIR register with new field exposing the number of QSFP modules Extend MGPIR - Management General Peripheral Information Register with new field "num_of_modules" exposing the number of modules supported by specific system. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b97cd891 |
|
28-Aug-2019 |
Amit Cohen <amitc@mellanox.com> |
mlxsw: Remove 56G speed support Commit 275e928f1911 ("mlxsw: spectrum: Prevent force of 56G") prevented the driver from setting a speed of 56G when auto-negotiation is off. This is the only speed supported by mlxsw that cannot be set when auto-negotiation is off, which makes it difficult to write generic tests. Further, the speed is not supported by newer ASICs such as Spectrum-2 and to the best of our knowledge it is not used by current users. Therefore, remove 56G support from mlxsw. Signed-off-by: Amit Cohen <amitc@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9e6290c7 |
|
21-Aug-2019 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Add trap group for layer 2 discards Discard trap groups are defined in a different enum so that they could all share the same policer ID: MLXSW_REG_HTGT_TRAP_GROUP_MAX + 1. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6a44bae3 |
|
21-Aug-2019 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add new trap actions Subsequent patches will add discard traps support in mlxsw. The driver cannot configure such traps with a normal trap action, but needs to use exception trap action, which also increments an error counter. On the other hand, when these traps are initialized or set to drop action, they should use the default drop action set by the firmware. This guarantees that when the feature is disabled we get the exact same behavior as before the feature was introduced. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
71147506 |
|
04-Jul-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Add QoS PTP Shaper Configuration Register The QPSC allows advanced configuration of the PTP shapers. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
12f0e2e9 |
|
04-Jul-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Add ptps field in QoS ETS Element Configuration Register The PTP Shaper field is used for enabling and disabling of port-rate based shaper which is slightly lower than port rate. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
aed4b572 |
|
30-Jun-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: spectrum: PTP: Hook into packet receive path When configured, the Spectrum hardware can recognize PTP packets and trap them to the CPU using dedicated traps, PTP0 and PTP1. One reason to get PTP packets under dedicated traps is to have a separate policer suitable for the amount of PTP traffic expected when switch is operated as a boundary clock. For this, add two new trap groups, MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0 and _PTP1, and associate the two PTP traps with these two groups. In the driver, specifically for Spectrum-1, event PTP packets will need to be paired up with their timestamps. Those arrive through a different set of traps, added later in the patch set. To support this future use, introduce a new PTP op, ptp_receive. It is possible to configure which PTP messages should be trapped under which PTP trap. On Spectrum systems, we will use PTP0 for event packets (which need timestamping), and PTP1 for control packets (which do not). Thus configure PTP0 trap with a custom callback that defers to the ptp_receive op. Additionally, L2 PTP packets are actually trapped through the LLDP trap, not through any of the PTP traps. So treat the LLDP trap the same way as the PTP0 trap. Unlike PTP traps, which are currently still disabled, LLDP trap is active. Correspondingly, have all the implementations of the ptp_receive op return true, which the handler treats as a signal to forward the packet immediately. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
41ce78b9 |
|
30-Jun-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add Monitoring Global Configuration Register This register serves to configure global parameters of certain monitoring operations. The following patches will use it to configure that when PTP timestamps are delivered through the PTP FIFO traps, the FIFO in question is cleared as well. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
98b9028e |
|
30-Jun-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add Time Precision Packet Timestamping Reading The MTPPTR is used for reading the per port PTP timestamp FIFO. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4dfecb65 |
|
30-Jun-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add Monitoring Precision Time Protocol Trap Register This register is used for configuring under which trap to deliver PTP packets depending on type of the packet. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
da28e878 |
|
30-Jun-2019 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add Monitoring Time Precision Packet Port Configuration Register This register serves for configuration of which PTP messages should be timestamped. This is a global configuration, despite the register name. Signed-off-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f485cc36 |
|
24-Jun-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: core: Add support for negative temperature readout Extend macros MLXSW_REG_MTMP_TEMP_TO_MC() to allow support of negative temperature readout, since chip and others thermal components are capable of operating within the negative temperature. With no such support negative temperature will be consider as very high temperature and it will cause wrong readout and thermal shutdown. For negative values 2`s complement is used. Tested in chamber. Example of chip ambient temperature readout with chamber temperature: -10 Celsius: temp1: -6.0C (highest = -5.0C) -5 Celsius: temp1: -1.0C (highest = -1.0C) v2 (Andrew Lunn): * Replace '%u' with '%d' in mlxsw_hwmon_module_temp_show() Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1078645a |
|
11-Jun-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Add Management Pulse Per Second Register The MTPPS register provides the device PPS capabilities, configure the PPS in and out modules and holds the PPS in time stamp. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
55a8b001 |
|
11-Jun-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Add Management UTC Register The MTUTC register configures the HW UTC counter. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4b14cc31 |
|
11-Jun-2019 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Disallow prio-tagged packets when PVID is removed When PVID is removed from a bridge port, the Linux bridge drops both untagged and prio-tagged packets. Align mlxsw with this behavior. Fixes: 148f472da5db ("mlxsw: reg: Add the Switch Port Acceptable Frame Types register") Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
984aec75 |
|
29-May-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: core: Extend the index size for temperature sensors readout Extend sensor index size for Management Temperature Bulk Register (MTBR) and Management Temperature Register (MTMP) upto 12 bits in order to align registers description with new version of PRM document. Add define for base sensor index for SFP modules temperature reading for MTMP register. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7e9561ed |
|
29-May-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: reg: Add Management General Peripheral Information Register Add MGPIR - Management General Peripheral Information Register, which allows software to query the hardware and firmware general information of peripheral entities as Gearboxes etc. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ae574678 |
|
29-May-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: reg: Extend sensor index field size of Management Temperature Register Extend the size of sensor_index field of MTMP (Management Temperature Register), from 8 to 12 bits due to hardware change. Add define for sensor index for Gear Box (inter-connects) temperature reading. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a0c25387 |
|
05-May-2019 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Port Physical Loopback Register The PPLR register allows configuration of the port's loopback mode. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8d77d4bf |
|
08-Apr-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Add MGIR register Add MGIR register. MGIR, Management General Information Register, allows software to query the hardware and firmware general information. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9ce84397 |
|
22-Feb-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Add new port type-speed fields for PTYS register PTYS register introduces a new layout for port type-speed fields. These fields extend the existing ones in order to handle more types and speeds. For example, the new 200Gbps speed. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1dc3c0a2 |
|
22-Feb-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: 80 columns wrapping change 80 columns wrapping change in mlxsw_reg_ptys_eth_unpack function. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e6f66f50 |
|
22-Feb-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: reg: Rename p_eth_proto_adm to full name p_eth_proto_admin Rename p_eth_proto_adm to p_eth_proto_admin in mlxsw_reg_ptys_eth_unpack function. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1e2f66ec |
|
22-Feb-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: spectrum: Query port connector type from firmware Instead of deriving the port connector type from port admin state, query it from firmware. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
475b33cb |
|
22-Feb-2019 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: spectrum: Remove unsupported eth_proto_lp_advertise field in PTYS Remove eth_proto_lp_advertise field in PTYS register since it is not supported by the firmware. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3760c2b9 |
|
13-Feb-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: reg: Add Fan Out of Range Event Register Add FORE (Fan Out of Range Event Register), which is used for fan fault reading. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5f28ef71 |
|
13-Feb-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: reg: Add Management Temperature Bulk Register Add MTBR (Management Temperature Bulk Register), which is used for port temperature reading in a bulk mode. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d517ee7c |
|
13-Feb-2019 |
Vadim Pasternak <vadimp@mellanox.com> |
mlxsw: spectrum: Move QSFP EEPROM definitions to common location Move QSFP EEPROM definitions to common location from the spectrum driver in order to make them available for other mlxsw modules. They are common for all kind of chips and have relation to SFF specifications 8024, 8436, 8472, 8636, rather than to chip type. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5c661f14 |
|
07-Feb-2019 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add multi field to PAGT register For Spectrum-2 this allows parallel lookups in multiple regions. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c9417498 |
|
19-Jan-2019 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add underlay egress RIF field in RTDP register In Spectrum-2 we need to specify the underlay egress router interface when performing IP-in-IP and NVE packet decapsulation in the underlay router. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
afba3e10 |
|
19-Jan-2019 |
Nir Dotan <nird@mellanox.com> |
mlxsw: reg: Add fields to RITR - Router Interface Table Register Add fields relevant for Spectrum-2 Loopback IPinIP router interface creation. Add additional Loopback RIF protocol value - Generic, used for creation of an explicit underlay RIF, and also add a field named underlay_rif used for specifying the underlay RIF of a tunnel. Signed-off-by: Nir Dotan <nird@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
03ce5bd1 |
|
16-Dec-2018 |
Nir Dotan <nird@mellanox.com> |
mlxsw: reg: Activate Bloom filter Now that mlxsw driver handles all aspects of updating the Bloom filter mechanism, set bf_bypass value to false and allow HW to use Bloom filter. Signed-off-by: Nir Dotan <nird@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
418089a8 |
|
16-Dec-2018 |
Nir Dotan <nird@mellanox.com> |
mlxsw: reg: Add Policy Engine Algorithmic Bloom Filter Entries Register Bloom filter is a bit vector which allows the HW a fast lookup on a small size bit vector, that may reduce the number of lookups on the A-TCAM memory. PEABFE register allows setting values to the bits of the bit vector mentioned above. Add the register to be later used in A-TCAM optimizations. Signed-off-by: Nir Dotan <nird@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a75e41d3 |
|
10-Dec-2018 |
Nir Dotan <nird@mellanox.com> |
mlxsw: reg: Add Policy Engine Multicast Router Binding Table Register In Spectrum-2, multicast routing is implemented explicitly using policy engine (ACL) block. PEMRBT register is used to bind a dedicated ACL group to a specific IP protocol. Add the register to be later used in multicast router implementation. Signed-off-by: Nir Dotan <nird@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
2f4f4494 |
|
04-Dec-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Mirror loopbacked packets instead of trapping them When the ASIC detects that a unicast packet is routed through the same router interface (RIF) from which it ingressed (iRIF == eRIF), it raises a trap called loopback error (LBERROR). Thus far, this trap was configured to send a sole copy of the packet to the CPU so that ICMP redirect packets could be potentially generated by the kernel. This is problematic as the CPU cannot forward packets at 3.2Tb/s and there are scenarios (e.g., "one-armed router") where iRIF == eRIF is not an exception. Solve this by changing the trap to send a copy of the packet to the CPU. To prevent the kernel from forwarding the packet again, it is marked with 'offload_l3_fwd_mark'. The trap is configured in a trap group of its own with a dedicated policer in order not to prevent packets trapped by other traps from reaching the CPU. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
933b1ecd |
|
21-Nov-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add definition of unicast tunnel record for SFN register Will be used to process learned FDB records from an NVE tunnel. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
bae4e109 |
|
18-Nov-2018 |
Shalom Toledo <shalomt@mellanox.com> |
mlxsw: spectrum: Expose discard counters via ethtool Expose packets discard counters via ethtool to help with debugging. Signed-off-by: Shalom Toledo <shalomt@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c22291f7 |
|
14-Nov-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum: acl: Implement delta for ERP Allow ERP sharing for multiple mask. Do it by properly implementing delta_create() objagg object. Use the computed delta info for inserting rules in A-TCAM. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8b931821 |
|
31-Oct-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: QEEC: Add minimum shaper fields Add QEEC.mise (minimum shaper enable) and QEEC.min_shaper_rate to enable configuration of minimum shaper. Increase the QEEC length to 0x20 as well: that's the length that the register has had for a long time now, but with the configurations that mlxsw typically exercises, the firmware tolerated 0x1C-sized packets. With mise=true however, FW rejects packets unless they have the full required length. Fixes: b9b7cee40579 ("mlxsw: reg: Add QoS ETS Element Configuration register") Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
27f68c08 |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Monitoring Parsing State Register This register is used for setting up the parsing for hash, policy-engine and routing. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
0933781f |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add definition of unicast tunnel record for SFD register Will be used to program the device with FDB records pointing to a NVE tunnel. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8efcf6bb |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunneling NVE QoS Default Register The TNQDR register configures the default QoS settings for NVE encapsulation. It will be used to set the default DSCP of each port to 0, so that when DSCP is set to inherit and the overlay packet does not have an IP header the outer DSCP will be set to 0, in accordance with the software data path. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fd6db27c |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunneling NVE QoS Configuration Register The register configures how QoS is set in Encapsulation into the underlay network. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a77d5f0b |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunneling NVE Decapsulation ECN Mapping Register This register configures the actions that are done during NVE decapsulation based on the ECN bits. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4a8d1860 |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunneling NVE Encapsulation ECN Mapping Register This register performs mapping from overlay ECN to underlay ECN during NVE encapsulation. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c723d19f |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunneling NVE Underlay Multicast Table Register This register builds the linked list of underlay destination IPs used for BUM traffic on the overlay. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
50e6eb2a |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunnel Port Configuration Register This register enables / disables learning on different types of tunnel ports (e.g., NVE, VPLS). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
710dd1a0 |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Tunneling NVE General Configuration Register This register configures global NVE configuration such as source IP of the NVE tunnel and UDP source port calculation. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
beda7f72 |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Seed LAG hash function Currently, the seed of the LAG hash function is always set to 0, which means it is identical across all switches. Instead, use a random number. This is especially important now that VxLAN is supported, as the LAG hash function is used to calculate the UDP source port of the encapsulated packet. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a682a302 |
|
11-Oct-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Extend FDB flush types for NVE The device has the ability to flush all the FDB records that perform NVE encapsulation or only a subset of these with a specific filtering identifier (FID). Expose these types so that they could be used by subsequent patches where we need to flush the FDB records when an NVE device is unlinked from a bridge (FID). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d144e3a2 |
|
20-Sep-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: spectrum_buffers: Allow an infinite maximum for per-TC pool limit The SBCM register configures the shared buffer configuration according to port and TC. So far all pools have had a dynamic size, where the infinite size is easy to express by using max_buff of 0xff. However the MC pool should be configured with static size, and the infinite size thus needs to be set using the field SBCM.infi_max. Therefore add the field infi_max to the SBCM register and to mlxsw_reg_sbcm_pack(). Extend mlxsw_sp_sb_cm_write() to handle infinite sizes as well. Report infinite pool limits as if the limit actually were the total shared buffer size. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f0024f0d |
|
20-Sep-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: spectrum_buffers: Allow pools of infinite size The MC pool should have an infinite size (i.e. no quota). To that end, add infi_size to the SBPR register and extend mlxsw_reg_sbpr_pack(). Also add MLXSW_SP_SB_INFI to denote buffers that should have an infinite size. Change mlxsw_sp_sb_pr_write() to take as parameter byte size, instead of cell size, and add the special handling of infinite buffers. Report pools with infinite size as if they actually take the full shared buffer size. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9948a064 |
|
09-Aug-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: Replace license text with SPDX identifiers and adjust copyrights Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
671ae8af |
|
05-Aug-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add QoS Switch Traffic Class Table is Multicast-Aware Register This register configures if the Switch Priority to Traffic Class mapping is based on Multicast packet indication. If so, then multicast packets will get a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by QTCT. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
55fb71f4 |
|
27-Jul-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add QoS Priority to DSCP Mapping Register This register controls mapping from Priority to DSCP for purposes of rewrite. Note that rewrite happens as the packet is transmitted provided that the DSCP rewrite bit is enabled for the packet. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e67131d9 |
|
27-Jul-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add QoS ReWrite Enable Register This register configures the rewrite enable (whether PCP or DSCP value in packet should be updated according to packet priority) per receive port. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
746da42a |
|
27-Jul-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add QoS Priority Trust State Register The QPTS register controls the port policy to calculate the switch priority and packet color based on incoming packet fields. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
02837d72 |
|
27-Jul-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add QoS Port DSCP to Priority Mapping Register The QPDPM register controls the mapping from DSCP field to Switch Priority for IP packets. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a0a777b9 |
|
25-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_acl: Start using A-TCAM Now that all the pieces are in place we can start using the A-TCAM instead of only using the C-TCAM. This allows for much higher scale and better performance (to be improved further by follow-up patch sets). Perform the integration with the A-TCAM and the eRP core by reverting the changes introduced by "mlxsw: spectrum_acl: Enable C-TCAM only mode in eRP core" and add calls from the C-TCAM code into the eRP core. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8c0d1cdd |
|
25-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Policy-Engine eRP Table Register The register is used to add and delete eRPs from the eRP table. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
aecefac9 |
|
25-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Policy-Engine TCAM Entry Register Version 3 The register is used to configure rules in the A-TCAM. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
91329e27 |
|
25-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Prepare PERERP register for A-TCAM usage Before introducing A-TCAM support we need to make sure all the necessary fields are configurable and not hard coded to values that worked for the C-TCAM only use case. This includes - for example - the ability to configure the eRP table used by the TCAM region. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7050f439 |
|
18-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Policy-Engine General Configuration Register The PGCR register configures general Policy-Engine settings. Specifically, we are going to use it in order to set the default action base pointer, which determines where the default action (when there is no hit) is located for each region. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f1c7d9cc |
|
18-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Policy-Engine Region eRP Register The PERERP register configures the region eRPs. It can be used, for example, to enable lookup in the C-TCAM in addition to the A-TCAM. To be able to perform a lookup in the C-TCAM we need to "use" the eRP table. This is done by marking the pointer as valid, but zeroing the eRP table vector. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
481662a8 |
|
18-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Policy-Engine Region Configuration Register The PERCR register configures the region parameters such as whether to consult the bloom filter before performing a lookup using a specific eRP. For C-TCAM only usage we don't need to accurately set the master mask. Instead, we can set all of its bits to make sure all the extracted keys are actually used. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
3390787b |
|
18-Jul-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine Region Association Register The PERAR register is used to associate a hw region for region_id's. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
2d186ed4 |
|
18-Jul-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add support for activity information from PEFA register In Spectrum-2, the PEFA register is extend to report if the action set was hit during processing of packets. Introduce this extension and adjust the code around this accordingly. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c33d0cb1 |
|
18-Jul-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Infrastructure Entry Delete Register The IEDR register is used for deleting entries from the entry tables. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1222d15a |
|
15-Jul-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum: Expose counters for various packet sizes Expose counters ASIC has in the group of RFC 2819 counters that count number of packets within specific size range. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c3a49540 |
|
14-Jul-2018 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_router: Optimize processing of VRRP MACs Hosts using a VRRP router send their packets with a destination MAC of the VRRP router which is of the following form [1]: IPv4 - 00-00-5E-00-01-{VRID} IPv6 - 00-00-5E-00-02-{VRID} Where VRID is the ID of the virtual router. Such packets are directed to the router block in the ASIC by an FDB entry that was added in the previous patch. However, in certain cases it is possible to skip this FDB lookup and send such packets directly to the router. This is accomplished by adding these special MAC addresses to the RIF cache. If the cache is hit, the packet will skip the L2 lookup and ingress the router with the RIF specified in the cache entry. 1. https://tools.ietf.org/html/rfc5798#section-7.3 Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
42df8358 |
|
08-Jul-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add priority field for PTCEV2 register This is going to be needed for Spectrum-2 C-TCAM implementation. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
45e0620d |
|
08-Jul-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Introduce Flex2 key type for PTAR register Introduce Flex2 key type for PTAR register which is used in Spectrum-2. Also, extend mlxsw_reg_ptar_pack() to set the value according to the caller. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
12b003b2 |
|
27-May-2018 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Management Reset and Shutdown Register Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
41947662 |
|
10-May-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH Add MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH to support VLAN-encapsulated port mirroring. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a82b1b8f |
|
26-Mar-2018 |
Yuval Mintz <yuvalm@mellanox.com> |
mlxsw: reg: Add register settings for IPv6 multicast routing Add new fields for the rmft register necessary for setting the IPv6 multicast FIB table. Add a matching wrapper function for filling the register in the IPv6 scenario. Signed-off-by: Yuval Mintz <yuvalm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9a3d183a |
|
26-Mar-2018 |
Yuval Mintz <yuvalm@mellanox.com> |
mlxsw: reg: Configure RIF to forward IPv6 multicast packets Similarly to what was done in commit 4af5964e5888 ("mlxsw: reg: Configure RIF to forward IPv4 multicast packets by default") we now set two additional bits to allow IPv6 multicast forwarding. Signed-off-by: Yuval Mintz <yuvalm@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8e1ed739 |
|
21-Mar-2018 |
Tal Bar <talb@mellanox.com> |
mlxsw: spectrum: Add support for auto-negotiation disable mode In 'auto-neg off' the device have sent AN (auto-negotiation) frames with the forced speed. Thus, fix it using an_disable_admin field in Port type and speed (PTYS) register. This field indicates if speed negotiation frames would be send by the port or not. Add the field and enable/disable it for 'auto-neg on/off', make the port to start/stop sending AN (auto-negotiation) frames. Note that for SwitchX2 the behavior doesn't change (i.e support only AN enabled with forced speed). Signed-off-by: Tal Bar <talb@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1da93eb4 |
|
27-Feb-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Extend mlxsw_reg_mpat_pack() To support encapsulated SPAN, extend mlxsw_reg_mpat_pack() with a field to set the SPAN type. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0d6cd3fc |
|
27-Feb-2018 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add SPAN encapsulation to MPAT register MPAT Register is used to query and configure the Switch Port Analyzer Table. To configure Port Analyzer to encapsulate mirrored packets, additional fields need to be specified for the MPAT register. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ddb362ce |
|
13-Jan-2018 |
Yuval Mintz <yuvalm@mellanox.com> |
mlxsw: reg: add rdpm register Add rdpm definition - router DSCP to priority mapping register. This register will be utilized later to align the default mapping between packet DSCP and switch-priority to the kernel's mapping between packet priority and skb priority. This is the first non-bit indexed register where the entries are arranged in descending order, i.e., entry at offset 0 matches configuration for dscp[63]. As a result, the item's step is converted into a signed variable to support descending arrays [where step would be negative]. Signed-off-by: Yuval Mintz <yuvalm@mellanox.com> Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0afc1221 |
|
05-Nov-2017 |
Yuval Mintz <yuvalm@mellanox.com> |
mlxsw: reg: Add ext and tc-cong counter groups This adds the counter group definitions for 2 new counter groups which are necessary for gaining ECN & wred counters. Signed-off-by: Yuval Mintz <yuvalm@mellanox.com> Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
ad53fa06 |
|
05-Nov-2017 |
Nogah Frankel <nogahf@mellanox.com> |
mlxsw: reg: Add cwtp & cwtpm registers This patch adds 2 new registers: - Congestion WRED ECN TClass Profile Register [CWTP] - Congestion WRED ECN TClass and Pool Mapping Register [CWTPM] These registers would later be needed to offload RED-related functionality to the HW. Signed-off-by: Yuval Mintz <yuvalm@mellanox.com> Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e471859b |
|
02-Nov-2017 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Router ECMP Configuration Register Version 2 The RECRv2 register is used for setting up the router's ECMP hash configuration. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
62b0e924 |
|
30-Oct-2017 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add high and low temperature thresholds The ASIC has the ability to generate events whenever a sensor indicates the temperature goes above or below its high or low thresholds, respectively. In new firmware versions the firmware enforces a minimum of 5 degrees Celsius difference between both thresholds. Make the driver conform to this requirement. Note that this is required even when the events are disabled, as in certain systems interrupts are generated via GPIO based on these thresholds. Fixes: 85926f877040 ("mlxsw: reg: Add definition of temperature management registers") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
3e8c1fd3 |
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26-Oct-2017 |
Nogah Frankel <nogahf@mellanox.com> |
mlxsw: reg: Avoid magic number in PPCNT Replace recurring magic number in PPCNT register with a define. Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
14aefd90 |
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20-Oct-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add Tunneling IPinIP General Configuration Register The TIGCR register is used for setting up the IPinIP Tunnel configuration. Fixes: ee954d1a91b2 ("mlxsw: spectrum_router: Support GRE tunnels") Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f4de25fb |
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25-Sep-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Add support for counters on RATR In order to add the ability for setting counters on nexthops the RATR register should be extended. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b48cfc80 |
|
19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: spectrum: Add multicast router traps and trap groups Add three new traps needed for multicast routing: - PIM: Trap for PIM protocol control packets. - RPF: Trap for packets that fail the RPF check on a specific hardware route entry. - MULTICAST: Generic trap for multicast. It is used for routes that trap the packets to the CPU. The RPF and MULTICAST traps have rate limiters as these traps may have line-rate of packets trapped. The PIM trap has a rate limiter similarly to other L3 control protocols. The rate limiters are implemented by adding three new trap groups for the newly introduced traps. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4af5964e |
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19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Configure RIF to forward IPv4 multicast packets by default Turn on two bits on the Spectrum RIF configuration: - IPv4 multicast: when a multicast packet arrives on a RIF, send it to go through multicast routes lookup. - IPv4 multicast forwarding enable: when multicast packet arrives on a RIF, allow it to be forwarded by multicast routes. If this bit is not set, multicast packets will go through multicast routing lookup but will be dropped at the egress of the ports. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4fc92846 |
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19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Router Rules Copy Register The RRCR register is used for copying and moving TCAM multicast routes from different offsets. It will be used to allow routes relocation for parman ops as part of the multicast router offloading logic. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
2e654e33 |
|
19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add the Router Multicast Forwarding Table Version 2 register The RMFT-V2 register is used to configure and query the multicast table and will be used by the multicast router offloading logic. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5080c7e9 |
|
19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add the Router Interface Group Version 2 register The RIGR-V2 register is used to add, remove and query egress interface list of a multicast forwarding entry and it will be used by the multicast router offloading logic. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
46a7054e |
|
19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add The Router TCAM Allocation register This register is used for allocation of regions in the TCAM table and it will be used by the multicast router offloading logic. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
58726565 |
|
19-Sep-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Rename the flexible action set length field The MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN is relevant for the multicast router registers too, so rename it to have a general name which is not bound to a specific register. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
89e41982 |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Give mlxsw_reg_ratr_pack a type parameter To support IPIP, the driver needs to be able to construct an IPIP adjacency. Change mlxsw_reg_ratr_pack to take an adjacency type as an argument. Adjust the one existing caller. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
9571e828 |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Extract mlxsw_reg_ritr_mac_pack() Unlike other interface types, loopback RIFs do not have MAC address. So drop the corresponding argument from mlxsw_reg_ritr_pack() and move it to a new function. Call that from callers of mlxsw_reg_ritr_pack. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1e659ebf |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add Routing Tunnel Decap Properties Register The RTDP register is used for configuring the tunnel decap properties of NVE and IPinIP. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
a43da820 |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Add mlxsw_reg_ralue_act_ip2me_tun_pack() To implement IP-in-IP decapsulation, Spectrum uses LPM entries of type IP2ME with tunnel validity bit and tunnel pointer set. The necessary register fields are already available, so add a function to pack the RALUE as appropriate. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6c4153b1 |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Move enum mlxsw_reg_ratr_trap_id This enum is used with reg_ratr_trap_id, so move it next to the register definition. While at it, drop the enumerator initializers. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7c819de4 |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Update RATR to support IP-in-IP tunnels So far, adjacencies have always been of type Ethernet (with value of 0), and thus there was no need to explicitly support RATR type. However to support IP-in-IP adjacencies, this type and a suite of IP-in-IP-specific attributes need to be added. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
99ae8e3e |
|
02-Sep-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg: Update RITR to support loopback device Update the register so that loopback RIFs can be created and loopback properties specified. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7cfcbc75 |
|
24-Aug-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: spectrum_router: Add support for setting counters on neighbors Add support for setting counters on neighbors based on dpipe's host table counter status. This patch also adds the ability for getting the counter value, which will be used by the dpipe host table implementation in the next patches. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6bba7e20 |
|
24-Aug-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Make flow counter set type enum to be shared This is done as a preparation before introducing support for neighbor counters. The flow counter's type enum is used by many registers, yet, until now it was used only by mgpc and thus it was private. This patch updates the namespace for more generic usage. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
83930cd7 |
|
31-Jul-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg.h: Namespace IP2ME registers This renames IP2ME-specific registers reg_ralue_v and reg_ralue_tunnel_ptr to reg_ralue_ip2me_*. Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
78676ad4 |
|
31-Jul-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: Update specification of reg_ritr_type The comments really belong to the individual enumerators. The comment at the register should instead reference the enum. Signed-off-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
806a1c1a |
|
31-Jul-2017 |
Petr Machata <petrm@mellanox.com> |
mlxsw: reg.h: Fix a typo Signed-off-by: Petr Machata <petrm@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
62547f40 |
|
18-Jul-2017 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Update RALUE register with IPv6 support Update the register so that IPv6 LPM entries could be programmed to the device's table. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
72e8ebe1 |
|
18-Jul-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Update RAUHTD register with IPv6 support Update the register so that the active IPv6 neighbours could be dumped from the device's neighbour table. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6929e507 |
|
18-Jul-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Update RAUHT register with IPv6 support Update the register, so the IPv6 neighbours could be programmed to the device's neighbour table. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8d54814e |
|
18-Jul-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: spectrum: Add support for IPv6 traps Before we can start using IPv6, we need to trap certain control packets to the CPU. Among others, these include Neighbour Discovery, DHCP and neighbour misses. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e717e011 |
|
18-Jul-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Enable IPv6 on router interfaces Enable IPv6 and IPv6 forwarding on router interfaces (RIFs), so that they will be able to receive and forward IPv6 traffic. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e29237e7 |
|
18-Jul-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: spectrum_router: Enable IPv6 router Before we add IPv6 constructs like traps and router interfaces, we first need to enable IPv6 routing in the device. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
588823f9 |
|
17-Jul-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: spectrum: Add support for IPv6 MLDv1/2 traps Add support for IPv6 MLDv1/2 packet trapping. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7ca36994 |
|
14-Jun-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Add MCIA register for cable info access The MCIA register is used to access the SFP+ and QSFP connector's EPROM. It will be used to query the cable info. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
da0abcf9 |
|
04-Jun-2017 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Fix typo inside enumeration Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4625d59d |
|
23-May-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Management Component Data Access register The MCDA register allows reading and writing a firmware component. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
191839de |
|
23-May-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Management Component Control register The MCC register allows controlling and querying the firmware flash state machine (FSM). Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4f2402d4 |
|
23-May-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Management Component Query Information register The MCQI register queries information about firmware components. It will be needed by the mlxfw module to query various options about the components, such as their max size, alignment and max write size. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ba73e97a |
|
28-Mar-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Add Router Interface Counter Register The RICNT register retrieves per port performance counter. It will be used to query the router interfaces statistics. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
0f630fcb |
|
28-Mar-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Add counter fields to RITR register Update RITR for counter support. This allows adding counters for ASIC's router ports. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e9093b11 |
|
14-Mar-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix SPVMLR max record count The num_rec field is 8 bit, so the maximal count number is 255. This fixes vlans learning not being enabled for wider ranges than 255. Fixes: a4feea74cd7a ("mlxsw: reg: Add Switch Port VLAN MAC Learning register definition") Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f004ec06 |
|
14-Mar-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix SPVM max record count The num_rec field is 8 bit, so the maximal count number is 255. This fixes vlans not being enabled for wider ranges than 255. Fixes: b2e345f9a454 ("mlxsw: reg: Add Switch Port VID and Switch Port VLAN Membership registers definitions") Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
5766532a |
|
11-Mar-2017 |
Arkadi Sharshevsky <arkadis@mellanox.com> |
mlxsw: reg: Add Monitoring General Purpose Counter Set register The MGPC register retrieves generic flow counter value. It will be used to query ACL counters. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
6913229e |
|
10-Mar-2017 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum_router: Explicitly Associate RIFs with VRs Up until now we implicitly associated all the router interfaces (RIFs) with the first virtual router (VR). This must be changed in order to enable VRF offload. Otherwise, a packet received via a VRF slave would do a FIB lookup in the same table used by other VRFs. Instead, bind the RIF to a VR according to the table where FIB lookup should be performed for packets received via the RIF. Currently, we only care about the MAIN and LOCAL tables (which we squash together). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e158e5ef |
|
06-Feb-2017 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Fix HTGT register length HTGT register length is limited to 32 bytes and not 256 bytes. Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
e3426e12 |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine Extended Flexible Action Register PEFA register is used for accessing an extended flexible action entry in the central KVD Linear Database. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d120649d |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine Policy Based Switching Register The PPBS register retrieves and sets Policy Based Switching Table entries. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
937b682c |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine Rules Copy Register The PRCR register is used for accessing rules within a TCAM region. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
af7170ee |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine Port Binding Table The PPBT is used for configuration of the Port Binding Table. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0171cdec |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine TCAM Entry Register Version 2 The PTCE-V2 register is used for accessing rules within a TCAM region. It is a new version of PTCE in order to support wider key, mask and action within a TCAM region. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d9c2661e |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine TCAM Allocation Register The PTAR register is used for allocation of regions in the TCAM. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
10fabef5 |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine ACL Group Table register The PAGT register is used for configuration of the ACL Group Table. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3279da4c |
|
03-Feb-2017 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Policy-Engine ACL Register The PACL register is used for configuration of the ACL. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0677d682 |
|
23-Jan-2017 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: add the Monitoring Packet Sampling Configuration Register The MPSC register allows to configure ingress packet sampling on specific port of the mlxsw device. The sampled packets are then trapped via PKT_SAMPLE trap. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
76a4c7d3 |
|
25-Nov-2016 |
Nogah Frankel <nogahf@mellanox.com> |
mlxsw: reg: Add QoS Policer Configuration Register The QPCR register is used to create and control policers. A policer can discard or change the color of packets that are trapped by a specific trap. Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
117b0dad |
|
25-Nov-2016 |
Nogah Frankel <nogahf@mellanox.com> |
mlxsw: Create a different trap group list for each device Trap groups can be used to control traps priority, both in terms of which trap "wins" if a packet matches two traps (priority) and in terms of packets from which trap group will be scheduled to the cpu first (tc). They can also be used to set rate limiters (policers) on them (will be added in the next patches). Currently, we support two trap groups. In Spectrum we want a better resolution, so every protocol / flow will have a different trap group, so we can control its parameters separately. Once the policers will be implemented, it will also allow us limit the rate of each protocol by itself. This patch change the trap group list to include: * the emad trap group, which is shared for all the devices. * Switchx2's trap groups, which are a copy of the current trap groups. * Spectrum's new trap groups, in order to match the above guidelines. (Switchib is using only the emad trap group, so it require no changes). This patch also includes new configuration for Spectrum's trap groups, with primary priority order within them. Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
579c82e4 |
|
25-Nov-2016 |
Nogah Frankel <nogahf@mellanox.com> |
mlxsw: Change trap groups setting Trap groups have many options which we currently set to default values. In the next patches we will use many of them with non-default values. Some of these options have no default value, so this patch sets them as params for the trap group set function. Others almost always use the same values, so the set function will use this default values. In the rare cases when they will need to be with other values, these values can be set directly (using the macros for fields in registers). Parameters without default value: TC - the traffic class for packets that hit this trap group. (old default is the max tc) priority - if one packet hits multiple trap groups, the group with the higher priority will "catch" it. (old default is 0) policer - limit rate policer (old default is disabled) Default parameters: swid - switch id, relevant for the emad trap only, ignored on Spectrum. (new default is 0) rdq - CPU receive descriptor queue (new default is identical to trap group id) Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d570b7ee |
|
25-Nov-2016 |
Nogah Frankel <nogahf@mellanox.com> |
mlxsw: Change trap set function Change trap setting function so instead of determining the trap group by trap id, it gets it as a parameter (so later we can have different trap groups for Spectrum and Switchx2). Add "is_ctrl" parameter to the trap setting function. It control whether the trapped packets wait in a designated control buffer or in their default one. This parameter is ignored by Switchx2 and Switchib. Add these parameters to the traps array in Spectrum, Switchx2 and Switchib. Signed-off-by: Nogah Frankel <nogahf@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
55c63aaa |
|
22-Nov-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Management Fan Speed Limit register The MFSL register is used to configure the fan speed event / interrupt notification mechanism. Fan speed threshold are defined for both under-speed and over-speed. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
f7ad3d4b |
|
11-Nov-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix pwm_frequency field size in MFCR register The field is 7bit long. Fix it. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7136793e |
|
28-Oct-2016 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Add local-port to Infiniband port mapping In order to change a port type to Infiniband port we should change his mapping from local-port to Infiniband. Adding the PLIB (Port Local to InfiniBand) allows this mapping. Signed-off-by: Elad Raz <eladr@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
79417702 |
|
28-Oct-2016 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Add Infiniband support to PTYS In order to support Infiniband fabric, we need to introduce IB speeds and capabilities to PTYS emads. Signed-off-by: Elad Raz <eladr@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
401c8b4e |
|
28-Oct-2016 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Add eth prefix to PTYS pack and unpack We want to add Infiniband support to PTYS. In order to maintain proper conventions, we will change pack and unpack prefix to eth. Signed-off-by: Elad Raz <eladr@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
8e9658d5 |
|
21-Oct-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Generare register names automatically Extend the MLXSW_REG_DEFINE macro to store register name in string form. Use this string later on instead of hard coded string values. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Acked-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
21978dcf |
|
21-Oct-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Use helper macro to define registers Save some code and also prepare to easily carry name in string form. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Acked-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
18c2d2c1 |
|
19-Sep-2016 |
Elad Raz <eladr@mellanox.com> |
mlxsw: Change the RX LAG hash function from XOR to CRC Change the RX hash function from XOR to CRC in order to have better distribution of the traffic. Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
b9d66a36 |
|
12-Sep-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Add support for new ethtool API Remove the deprecated {get,set}_settings callbacks and instead add {get,set}_link_ksettings along with support for newly available speeds. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4149b97f |
|
12-Sep-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Report link partner's advertised speeds If autonegotiation was performed successfully, then we should report the link partner's advertised speeds instead of the operational speed of the port. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
1803e0fb |
|
23-Aug-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Limit number of FDB records per learning session Up until now a learning session ended whenever the number of queried records was zero. This turned out to be problematic in situations where a large number of MACs (48K) had to be processed by the switch driver, as RTNL mutex is held during the learning session. Instead, limit the number of FDB records that can be processed in a session to 64. This means that every time the device is queried for learning notifications (currently, every 100ms), up to 64 records will be processed by the switch driver. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
0e7df1a2 |
|
17-Aug-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix missing op field fill-up Ralue pack function needs to set op, otherwise it is 0 for add always. Fixes: d5a1c749d22 ("mlxsw: reg: Add Router Algorithmic LPM Unicast Entry Register definition") Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a94a614f |
|
17-Aug-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Trap loop-backed packets One of the conditions to generate an ICMP Redirect Message is that "the packet is being forwarded out the same physical interface that it was received from" (RFC 1812). Therefore, we need to be able to trap such packets and let the kernel decide what to do with them. For each RIF, enable the loop-back filter, which will raise the LBERROR trap whenever the ingress RIF equals the egress RIF. Fixes: 99724c18fc66 ("mlxsw: spectrum: Introduce support for router interfaces") Reported-by: Ilan Tayari <ilant@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
23019054 |
|
20-Jul-2016 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add the Monitoring Port Analyzer register The MPAR register is used to bind ports to a SPAN entry (which was created using MPAT register) and thus mirror their traffic (ingress / egress) to a different port. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
43a46856 |
|
20-Jul-2016 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Monitoring Port Analyzer Table register The MPAT register is used to query and configure the Switch Port Analyzer (SPAN) table. This register is used to configure a port as a mirror output port, while after that a mirrored input port can be bound using MPAR register. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
51ae8cc6 |
|
20-Jul-2016 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Shared Buffer Internal Buffer register The SBIB register configures per port buffer for internal use. This register is used to configure an egress mirror buffer on the egress port which does the mirroring. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
df4750e8 |
|
19-Jul-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Expose per-tc counters via ethtool Expose the transmit queue length of each traffic class and the amount of unicast packets discarded due to insufficient room in the shared buffer. The first counter allows us to debug user priority to traffic class mapping, whereas the drop counter is useful when determining shared buffer configuration. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
11719a58 |
|
15-Jul-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Prevent invalid ingress buffer mapping Packets entering the switch are mapped to a Switch Priority (SP) according to their PCP value (untagged frames are mapped to SP 0). The packets are classified to a priority group (PG) buffer in the port's headroom according to their SP. The switch maintains another mapping (SP to IEEE priority), which is used to generate PFC frames for lossless PGs. This mapping is initialized to IEEE = SP % 8. Therefore, when mapping SP 'x' to PG 'y' we create a situation in which an IEEE priority is mapped to two different PGs: IEEE 'x' ---> SP 'x' ---> PG 'y' IEEE 'x' ---> SP 'x + 8' ---> PG '0' (default) Which is invalid, as a flow can use only one PG buffer. Fix this by mapping both SP 'x' and 'x + 8' to the same PG buffer. Fixes: 8e8dfe9fdf06 ("mlxsw: spectrum: Add IEEE 802.1Qaz ETS support") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a59f0b31 |
|
05-Jul-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM ECMP Update Register The RALEU register is used to mass update remote action adjacency index and ecmp size. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
089f9816 |
|
05-Jul-2016 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Router Adjacency Table register The RATR register is used to configure the Router Adjacency (next-hop) Table. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
7cf2c205 |
|
05-Jul-2016 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM Unicast Host Table Dump register The RAUHTD register allows dumping entries from the Router Unicast Host Table. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
4457b3df |
|
05-Jul-2016 |
Yotam Gigi <yotamg@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM Unicast Host Table register The RAUHT register is used to configure and query the Unicast Host Table in devices that implement the Algorithmic LPM. In other words, it is used to configure neighbour entries in the device. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d5a1c749 |
|
04-Jul-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM Unicast Entry Register definition Serves for adding, updating and removing fib entries. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
20ae4053 |
|
04-Jul-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM Tree Binding Register definition This register is used to bind virtual router and protocol to an allocated LPM tree. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
a9823359 |
|
04-Jul-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM Structure Tree Register definition Serves to build LPM tree structure. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
6f9fc3ce |
|
04-Jul-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Router Algorithmic LPM Tree Allocation Register definition Register serves for allocation and deallocation of LPM search tree. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
3dc26689 |
|
02-Jul-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Router Interface Table Register Add the Router Interface Table Register (RITR), which allows us to create and configure router interfaces (RIFs). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d82d8c06 |
|
02-Jul-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add FDB action to forward to router Incoming packets are directed to the router when they match an FDB entry with action forward to IP router. Add this action, which was mistakenly named "TRAP". Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
69c407aa |
|
02-Jul-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Router General Configuration Register Add the Router General Configuration Register (RGCR), which allows us to enable the router in the device and configure its various parameters. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
42a7f1d7 |
|
14-Apr-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Extend SBPM register for occupancy control Since it is not possible to get and clear Port-Pool occupancy data using SBSR register, there's a need to implement that using SBPM. Extend pack helper and add unpack helper to get occupancy values. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
26176def |
|
14-Apr-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Shared Buffer Status register definition This register allows to query HW for current and maximal buffer usage. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
c30a53c7 |
|
14-Apr-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: spectrum_buffers: Get max_buff defaults into limits exposed to user Although the device supports max_buff magic values 0 and 0xff, these are not exposed to the user via devlink. Therefore, adjust the default values to be within configurable range. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
9efc8f65 |
|
08-Apr-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix SBPM register name Fix copy&paste error and state the name of SBPM register correctly. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
497e8592 |
|
08-Apr-2016 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Share direction enum between SBPR, SBCM, SBPM Same field, same values, so share the same enum. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
|
#
d81a6bdb |
|
06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Add IEEE 802.1Qbb PFC support Implement the appropriate DCB ops and allow a user to configure certain traffic classes as lossless. The operation configures PFC for both the egress (respecting PFC frames) and ingress (sending PFC frames) parts of the port. At egress, when a PFC frame is received for a PFC enabled priority, then all the priorities mapped to the same TC are stopped. At ingress, the priority group (PG) buffers to which the enabled PFC priorities are mapped are configured to be lossless. PFC frames will be transmitted when the Xoff threshold is crossed. The user-supplied delay parameter is used to determine the PG's size according to the following formula: PG_SIZE = PG_SIZE_LOSSY + delay * CELL_FACTOR + MTU In the worst case scenario the delay will be made up of packets that are all of size CELL_SIZE + 1, which means each packet will require almost twice its true size when buffered in the switch. We therefore multiply this value by the "cell factor", which is close to 2. Another MTU is added in case the transmitting host already started transmitting a maximum length frame when the PFC packet was received. As with PAUSE enabled ports, when the port's MTU is changed both the PGs' size and threshold are adjusted accordingly. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
34dba0a5 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Introduce per priority counters We are going to add support for PFC as part of DCB ops, which requires us to report the number of PFC frames sent and received per priority. Add per priority counters in order to report number of PFC frames sent and received per priority. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
155f9de2 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add lossless settings for PBMC register When configuring PAUSE frames and PFC we'll need to configure the Xon/Xoff threshold for the priority group (PG) buffers. Add the Xon/Xoff threshold fields to the PBMC register so that we can configure these when needed. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6f253d83 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Port Flow Control Configuration register Add the Port Flow Control Configuration (PFCC) register, which configures both flow control and Priority-based Flow Control (PFC). Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
2c63a555 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add QoS Switch Traffic Class Table register As part of DCB ops we'll have to configure the priority to traffic class mapping of a port. Add the QoS Switch Traffic Class Table (QTCT) register, which configures the mapping between the packet switch priority and traffic class on the transmit port. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b9b7cee4 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add QoS ETS Element Configuration register We are going to introduce support for DCB, so we need to be able to configure the traffic selection algorithm (TSA) used by each traffic class (TC), as well as the bandwidth percentage allocated to each TC in case of ETS. Add the QoS ETS Element Configuration register, which controls the above parameters. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d6b7c13b |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Set port's shared buffer size to 0 In addition to the priority group (PG) buffers in the headroom, the device enables the allocation of headroom shared buffer, which can be shared between different PGs. However, we are not going to use the headroom shared buffer and instead allow the user to use its size for PGs or the switch's shared buffer. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
7ad7cd61 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Use correct PBMC register length The last field of the PBMC register is at offset 0x64 and its size is 0x8, so the correct register's length is 0x6C bytes. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b98ff151 |
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06-Apr-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Port Prio To Buffer register When packets ingress the switch they are assigned a switch priority number that dictates the packet's priority group (PG) buffer in the port's headroom buffer. Add the Port Prio To Buffer (PPTB) register, which configures the switch priority to PG mapping. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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148f472d |
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18-Feb-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add the Switch Port Acceptable Frame Types register When VLAN filtering is enabled on a bridge and PVID is deleted from a bridge port, then untagged frames are not allowed to ingress into the bridge from this port. Add the Switch Port Acceptable Frame Types (SPAFT) register, which configures the frame admittance of the port. Fixes: 56ade8fe3fe1 ("mlxsw: spectrum: Add initial support for Spectrum ASIC") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
bbeeda27 |
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27-Jan-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Use correct offset in field definiton The rx_lane, tx_lane and module fields in the PMLP register don't have an additional offset besides the base one (0x04), so set it to 0x00. Fixes: 4ec14b7634b2 ("mlxsw: Add interface to access registers and process events") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
41933271 |
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27-Jan-2016 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add the Switch Filtering DB Flush register When removing a net device from a bridge we should flush the FDB entries associated with this net device. Up until now, we relied upon bridge code to do that for us, but it is possible for user to prevent hardware from syncing with the software bridge (learning_sync=0), so we need to flush overselves. Add the Switch Filtering DB Flush (SFDF) register that is used to flush FDB entries according to different parameters (per-port, per-FID etc). Fixes: 56ade8fe3fe1 ("mlxsw: spectrum: Add initial support for Spectrum ASIC") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fabe5483 |
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10-Jan-2016 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Adding SMID register Adding back SMID register definition and packing. For each MC group a new SMID entry will be generated. Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5230b25f |
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10-Jan-2016 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Add definition of multicast record for SFD register Multicast-related records have specific format in SFD register. Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
afd7f979 |
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15-Dec-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add lag_vid field to SFD register Unicast LAG records in the Switch Filtering Database (SFD) register have a lag_vid field indicating the VLAN ID in case of vFIDs. This field is no longer reserved since we are going to add support for VLAN devices on top of LAG. Add the lag_vid field to be used by VLAN devies on top of LAG. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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9de6a80e |
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15-Dec-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: spectrum: Use FID instead of VID when accessing FDB In the Spectrum ASIC - unlike SwitchX-2 - FDB access is done by specifying FID as parameter and not VID. Change the relevant variables and parameters names to reflect that. Note that this was OK up until now, since FID was always equal to VID, but with the introduction of VLAN interfaces this is no longer the case. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
acf35a4e |
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11-Dec-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix max temperature getting Fix copy & paste error in MTPM unpack helper. Fixes: 85926f877040 ("mlxsw: reg: Add definition of temperature management registers") Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3b71571c |
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02-Dec-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add definition of LAG unicast record for SFN register LAG-related records have specific format in SFN register. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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e4bfbae2 |
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02-Dec-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add definition of LAG unicast record for SFD register LAG-related records have specific format in SFD register. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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d1d40be0 |
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02-Dec-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add link aggregation configuration registers definitions Add definitions of SLDR, SLCR2, SLCOR registers that are used to configure LAG. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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5246f2e2 |
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27-Nov-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add definition of fan management registers Add definition of MFCR, MFSC and MFSM which provide possibility to control and monitor fans. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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85926f87 |
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27-Nov-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add definition of temperature management registers Add definition of MTCAP and MTMP registers which provide access to temperature sensors. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3161c159 |
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27-Nov-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Management LED Control register definition Add the MLCR register, which controls physical port identification LEDs. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
75c09280 |
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28-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Avoid unnecessary line wrap for mlxsw_reg_sfd_uc_unpack Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
8316f087 |
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28-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix desription typos of couple of SFN items Fix copy-paste errors. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4e9ec083 |
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28-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Fix description for reg_sfd_uc_sub_port The original description was for LAG, so fix it. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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a4feea74 |
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16-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Switch Port VLAN MAC Learning register definition Since we currently do not support the offloading of 802.1D bridges, we need to be able to let the device know it should not learn MAC addresses on specific {Port, VID} pairs. Add the SPVMLR register, which controls the learning enablement of {Port, VID} pairs. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e534a56a |
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16-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Switch Filtering Database Aging Time register definition Add SFDAT which is used to control switch ageing time. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1f65da74 |
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16-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Switch Virtual-Port Enabling register definition In order for a port to support {Port, VID} to FID mapping it needs to be configured to a virtual port mode (as opposed to VLAN mode). Add the SVPE register, which enables port virtualization. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
64790239 |
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16-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Switch VID to FID Allocation register definition An incoming packet can be classified into a filtering identifer (FID) based on its VID or incoming port and VID ({Port, VID}). Add the SVFA register, which controls this mapping. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f1fb693a |
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16-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Add Switch FID Management register definition Filtering identifiers (FIDs) are unique identifers of bridge instances in the hardware. Add the SFMR register, which is responsible for the creation and configuration of these FIDs. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e0594369 |
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16-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add shared buffer configuration registers definitions Add definitions of SBPR, SBCM, SBPM, SBMM and PBMC registers that are used to configure shared buffers. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b2e345f9 |
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16-Oct-2015 |
Elad Raz <eladr@mellanox.com> |
mlxsw: reg: Add Switch Port VID and Switch Port VLAN Membership registers definitions Add SPVID and SPVM registers responsible for default port VID configuration and VLAN membership of a port. Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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f5d88f58 |
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16-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Switch FDB Notification register definition Add SFN register which is used to poll for newly added and aged-out FDB entries. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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236033b3 |
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16-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Add Switch Filtering Database register definition Add the SFD register which is responsible for filtering database manipulation, including static and dynamic FDB entries. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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bc2055f8 |
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16-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Enable configuration of flooding domains As part of the introduction of L2 offloads, allow different ports to join/leave the flooding domain, according to user configuration. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
801bd3de |
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15-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Add trap group for control packets Previously, we trapped flooded and control packets using the same trap group. This can cause flooded packets to overflow the PCI bus and prevent control packets (e.g. STP, LACP) from getting to the CPU. Solve this by splitting the RX trap group to RX and control, which allows us to configure a policer on the first, thereby preventing it from overflowing the PCI bus. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f24af330 |
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15-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Simplify traps creation The Host Trap Group Table (HTGT) register configures trap groups, which are populated with trap IDs using the Host PacKet Trap (HPKT) register. However, a trap ID can only be present inside one trap group (the last configured). Instead of passing both the trap group and ID for the function that packs HPKT, pass only the trap ID and derive from it the trap group. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ebb7963f |
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15-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: Introduce mlxsw_reg_spms_vid_pack helper and use it Introduce separate helper for packing SPMS VIDs, as it can be used for multiple VIDs and not only for one as previous SPMS pack function provided. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
fa6ad058 |
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15-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: reg: Adjust definition of enum mlxsw_reg_sfgc_type Define max which would be needed later on. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
36b78e8a |
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15-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Remove extra space in SFGC ID define Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
3f0effd1 |
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15-Oct-2015 |
Jiri Pirko <jiri@mellanox.com> |
mlxsw: reg: Uppercase letters in register IDs Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
33a704a5 |
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15-Oct-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Remove multicast ID configuration With respect to a firmware change, the Switch Multicast ID (SMID) register is no longer needed, so the related configuration code can be removed. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e61011b5 |
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06-Aug-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Make system port to local port mapping explicit System ports are unique identifiers in a multi-ASIC environment that represent all the available ports in the system. Local ports on the other hand, are unique only within the local ASIC. Since system port to local port mapping is not part of the HW-SW contract and since only single-ASIC configurations are currently supported, set an explicit 1:1 mapping by configuring the Switch System Port Record (SSPR) register. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4ec14b76 |
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29-Jul-2015 |
Ido Schimmel <idosch@mellanox.com> |
mlxsw: Add interface to access registers and process events Ethernet Management Datagrams (EMADs) are Ethernet packets sent between the host and the device in order to configure the available device registers. Another use case is notifications sent from the device to the host, letting it know about certain events, such as port up / down. Add the ability to construct EMADs with provisions to construct and parse the registers' payloads. Implement EMAD transaction layer which is responsible for the reliable transmission of EMADs. Also, add an infrastructure used by the switch driver to register for particular events generated by the device. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Elad Raz <eladr@mellanox.com> Reviewed-by: Scott Feldman <sfeldma@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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