| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_transform.c | 32 #define REG(reg) \ macro
224 if (REG(DCFE_MEM_PWR_CTRL)) {
258 if (REG(DCFE_MEM_PWR_CTRL))
1418 if (REG(DCFE_MEM_PWR_CTRL))
1426 if (REG(DCFE_MEM_PWR_STATUS)) {
1472 if (REG(DCFE_MEM_PWR_CTRL))
1576 if (REG(DCFE_MEM_PWR_CTRL))
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| H A D | dce_mem_input.c | 32 #define REG(reg)\ macro
236 if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {
249 if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {
286 if (REG(DPG_PIPE_STUTTER_CONTROL2))
304 if (REG(DPG_PIPE_STUTTER_CONTROL2))
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| H A D | dce_opp.c | 33 #define REG(reg)\ macro
332 if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {
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| H A D | dce_abm.c | 40 #define REG(reg) \ macro
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| H A D | dce_panel_cntl.c | 42 #define REG(reg)\ macro
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| /linux-master/arch/sparc/net/ |
| H A D | bpf_jit_comp_64.c | 136 #define SETHI(K, REG) \
137 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
138 #define OR_LO(K, REG) \
139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
643 #define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX)
644 #define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX)
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_hubp.c | 38 #define REG(reg)\ macro
395 if (REG(NOM_PARAMETERS_0))
398 if (REG(NOM_PARAMETERS_1))
413 if (REG(NOM_PARAMETERS_2))
416 if (REG(NOM_PARAMETERS_3))
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dccg.c | 34 #define REG(reg) \ macro
384 if (REG(DSCCLK3_DTO_PARAM)) {
428 if (REG(DSCCLK3_DTO_PARAM)) {
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| /linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 30 #define REG(reg)\ macro
213 if (REG(OPTC_MEMORY_CONFIG))
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_mmhubbub.c | 33 #define REG(reg)\ macro
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| H A D | dcn32_dccg.c | 33 #define REG(reg) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mmhubbub.c | 33 #define REG(reg)\ macro
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| H A D | dcn30_dio_link_encoder.c | 40 #define REG(reg)\ macro
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| H A D | dcn30_dwb.c | 33 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_mmhubbub.c | 33 #define REG(reg)\ macro
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| H A D | dcn20_opp.c | 30 #define REG(reg) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| H A D | dcn314_optc.c | 35 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 53 #define REG(reg_name) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn32/ |
| H A D | dcn32_optc.c | 35 #define REG(reg)\ macro
|
| /linux-master/drivers/hwmon/ |
| H A D | asb100.c | 100 * REG: 16mV/bit
134 * REG: 1C/bit, two's complement
150 * REG: (6.25% duty cycle per bit)
167 * REG: 0, 1, 2, or 3 (respectively) (defaults to 1)
247 #define set_in_reg(REG, reg) \
260 asb100_write_value(client, ASB100_REG_IN_##REG(nr), \
429 #define set_temp_reg(REG, reg) \
449 asb100_write_value(client, ASB100_REG_TEMP_##REG(nr+1), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.c | 32 #define REG(reg)\ macro
263 if (REG(OTG_INTERLACE_CONTROL)) {
303 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
369 if (REG(OTG_INTERLACE_CONTROL)) {
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| /linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 34 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dio_link_encoder.c | 36 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr_smu_msg.c | 37 #define REG(reg_name) \ macro
|