1/* 2* Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include "dcn10/dcn10_hubp.h" 27#include "dcn21_hubp.h" 28 29#include "dm_services.h" 30#include "reg_helper.h" 31 32#include "dc_dmub_srv.h" 33 34#define DC_LOGGER \ 35 ctx->logger 36#define DC_LOGGER_INIT(logger) 37 38#define REG(reg)\ 39 hubp21->hubp_regs->reg 40 41#define CTX \ 42 hubp21->base.ctx 43 44#undef FN 45#define FN(reg_name, field_name) \ 46 hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name 47 48/* 49 * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. 50 * As a result, if S/W updates any of these registers during a mode change, 51 * the current frame before the mode change will use the new value right away 52 * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. 53 * 54 * REFCYC_PER_VM_GROUP_FLIP[22:0] 55 * REFCYC_PER_VM_GROUP_VBLANK[22:0] 56 * REFCYC_PER_VM_REQ_FLIP[22:0] 57 * REFCYC_PER_VM_REQ_VBLANK[22:0] 58 * 59 * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated 60 * when flipping to a new surface 61 * 62 * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated 63 * during prefetch period of a frame. The prefetch starts at a pre-determined 64 * number of lines before the display active per frame 65 * 66 * DCN may underflow due to incorrectly programming these registers 67 * during VM stage of prefetch/iflip. First lines of display active 68 * or a sub-region of active using a new surface will be corrupted 69 * until the VM data returns at flip/mode change transitions 70 * 71 * Work around: 72 * workaround is always opt to use the more aggressive settings. 73 * On any mode switch, if the new reg values are smaller than the current values, 74 * then update the regs with the new values. 75 * 76 * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 77 * 78 */ 79void apply_DEDCN21_142_wa_for_hostvm_deadline( 80 struct hubp *hubp, 81 struct _vcs_dpi_display_dlg_regs_st *dlg_attr) 82{ 83 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 84 uint32_t refcyc_per_vm_group_vblank; 85 uint32_t refcyc_per_vm_req_vblank; 86 uint32_t refcyc_per_vm_group_flip; 87 uint32_t refcyc_per_vm_req_flip; 88 const uint32_t uninitialized_hw_default = 0; 89 90 REG_GET(VBLANK_PARAMETERS_5, 91 REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank); 92 93 if (refcyc_per_vm_group_vblank == uninitialized_hw_default || 94 refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank) 95 REG_SET(VBLANK_PARAMETERS_5, 0, 96 REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); 97 98 REG_GET(VBLANK_PARAMETERS_6, 99 REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank); 100 101 if (refcyc_per_vm_req_vblank == uninitialized_hw_default || 102 refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank) 103 REG_SET(VBLANK_PARAMETERS_6, 0, 104 REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); 105 106 REG_GET(FLIP_PARAMETERS_3, 107 REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip); 108 109 if (refcyc_per_vm_group_flip == uninitialized_hw_default || 110 refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip) 111 REG_SET(FLIP_PARAMETERS_3, 0, 112 REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); 113 114 REG_GET(FLIP_PARAMETERS_4, 115 REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip); 116 117 if (refcyc_per_vm_req_flip == uninitialized_hw_default || 118 refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip) 119 REG_SET(FLIP_PARAMETERS_4, 0, 120 REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); 121 122 REG_SET(FLIP_PARAMETERS_5, 0, 123 REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); 124 125 REG_SET(FLIP_PARAMETERS_6, 0, 126 REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); 127} 128 129void hubp21_program_deadline( 130 struct hubp *hubp, 131 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 132 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 133{ 134 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 135 136 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); 137} 138 139void hubp21_program_requestor( 140 struct hubp *hubp, 141 struct _vcs_dpi_display_rq_regs_st *rq_regs) 142{ 143 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 144 145 REG_UPDATE(HUBPRET_CONTROL, 146 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 147 REG_SET_4(DCN_EXPANSION_MODE, 0, 148 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 149 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 150 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 151 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 152 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 153 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 154 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 155 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 156 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 157 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 158 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 159 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 160 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 161 REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, 162 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 163 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 164 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 165 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 166 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 167 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 168 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 169} 170 171static void hubp21_setup( 172 struct hubp *hubp, 173 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 174 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 175 struct _vcs_dpi_display_rq_regs_st *rq_regs, 176 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 177{ 178 /* otg is locked when this func is called. Register are double buffered. 179 * disable the requestors is not needed 180 */ 181 182 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 183 hubp21_program_requestor(hubp, rq_regs); 184 hubp21_program_deadline(hubp, dlg_attr, ttu_attr); 185 186} 187 188static void hubp21_set_viewport( 189 struct hubp *hubp, 190 const struct rect *viewport, 191 const struct rect *viewport_c) 192{ 193 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 194 195 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 196 PRI_VIEWPORT_WIDTH, viewport->width, 197 PRI_VIEWPORT_HEIGHT, viewport->height); 198 199 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 200 PRI_VIEWPORT_X_START, viewport->x, 201 PRI_VIEWPORT_Y_START, viewport->y); 202 203 /*for stereo*/ 204 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 205 SEC_VIEWPORT_WIDTH, viewport->width, 206 SEC_VIEWPORT_HEIGHT, viewport->height); 207 208 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 209 SEC_VIEWPORT_X_START, viewport->x, 210 SEC_VIEWPORT_Y_START, viewport->y); 211 212 /* DC supports NV12 only at the moment */ 213 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 214 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 215 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 216 217 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 218 PRI_VIEWPORT_X_START_C, viewport_c->x, 219 PRI_VIEWPORT_Y_START_C, viewport_c->y); 220 221 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 222 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 223 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 224 225 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 226 SEC_VIEWPORT_X_START_C, viewport_c->x, 227 SEC_VIEWPORT_Y_START_C, viewport_c->y); 228} 229 230static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, 231 struct vm_system_aperture_param *apt) 232{ 233 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 234 235 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 236 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 237 238 // The format of high/low are 48:18 of the 48 bit addr 239 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 240 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 241 242 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 243 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 244 245 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 246 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 247 248 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 249 ENABLE_L1_TLB, 1, 250 SYSTEM_ACCESS_MODE, 0x3); 251} 252 253static void hubp21_validate_dml_output(struct hubp *hubp, 254 struct dc_context *ctx, 255 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 256 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 257 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 258{ 259 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 260 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 261 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 262 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 263 DC_LOGGER_INIT(ctx->logger); 264 DC_LOG_DEBUG("DML Validation | Running Validation"); 265 266 /* Requester - Per hubp */ 267 REG_GET(HUBPRET_CONTROL, 268 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 269 REG_GET_4(DCN_EXPANSION_MODE, 270 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 271 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 272 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 273 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 274 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 275 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 276 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 277 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 278 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 279 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 280 VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 281 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 282 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 283 REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, 284 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 285 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 286 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 287 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 288 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 289 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 290 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 291 292 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 293 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 294 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 295 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 296 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 297 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 298 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 299 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 300 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 301 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 302 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 303 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 304 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 305 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 306 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 307 308 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 309 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 310 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 311 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 312 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 313 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 314 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 315 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 316 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 317 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 318 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 319 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 320 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 321 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 322 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 323 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 324 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", 325 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 326 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 327 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 328 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 329 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 330 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 331 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 332 333 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 334 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 335 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 336 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 337 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 338 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 339 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 340 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 341 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 342 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 343 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 344 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 345 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 346 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 347 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 348 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 349 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 350 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 351 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 352 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 353 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 354 355 356 /* DLG - Per hubp */ 357 REG_GET_2(BLANK_OFFSET_0, 358 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 359 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 360 REG_GET(BLANK_OFFSET_1, 361 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 362 REG_GET(DST_DIMENSIONS, 363 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 364 REG_GET_2(DST_AFTER_SCALER, 365 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 366 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 367 REG_GET(REF_FREQ_TO_PIX_FREQ, 368 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 369 370 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 371 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 372 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 373 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 374 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 375 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 376 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 377 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 378 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 379 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 380 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 381 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 382 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 383 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 384 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 385 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 386 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 387 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 388 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 389 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 390 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 391 392 /* DLG - Per luma/chroma */ 393 REG_GET(VBLANK_PARAMETERS_1, 394 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 395 if (REG(NOM_PARAMETERS_0)) 396 REG_GET(NOM_PARAMETERS_0, 397 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 398 if (REG(NOM_PARAMETERS_1)) 399 REG_GET(NOM_PARAMETERS_1, 400 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 401 REG_GET(NOM_PARAMETERS_4, 402 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 403 REG_GET(NOM_PARAMETERS_5, 404 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 405 REG_GET_2(PER_LINE_DELIVERY, 406 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 407 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 408 REG_GET_2(PER_LINE_DELIVERY_PRE, 409 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 410 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 411 REG_GET(VBLANK_PARAMETERS_2, 412 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 413 if (REG(NOM_PARAMETERS_2)) 414 REG_GET(NOM_PARAMETERS_2, 415 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 416 if (REG(NOM_PARAMETERS_3)) 417 REG_GET(NOM_PARAMETERS_3, 418 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 419 REG_GET(NOM_PARAMETERS_6, 420 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 421 REG_GET(NOM_PARAMETERS_7, 422 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 423 REG_GET(VBLANK_PARAMETERS_3, 424 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 425 REG_GET(VBLANK_PARAMETERS_4, 426 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 427 428 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 429 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 430 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 431 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 432 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 433 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 434 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 435 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 436 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 437 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 438 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 439 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 440 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 441 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 442 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 443 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 444 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 445 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 446 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 447 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 448 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 449 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 450 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 451 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 452 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 453 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 454 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 455 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 456 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 457 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 458 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 459 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 460 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 461 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 462 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 463 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 464 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 465 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 466 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 467 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 468 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 469 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 470 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 471 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 472 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 473 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 474 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 475 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 476 477 /* TTU - per hubp */ 478 REG_GET_2(DCN_TTU_QOS_WM, 479 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 480 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 481 482 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 483 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 484 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 485 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 486 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 487 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 488 489 /* TTU - per luma/chroma */ 490 /* Assumed surf0 is luma and 1 is chroma */ 491 REG_GET_3(DCN_SURF0_TTU_CNTL0, 492 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 493 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 494 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 495 REG_GET_3(DCN_SURF1_TTU_CNTL0, 496 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 497 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 498 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 499 REG_GET_3(DCN_CUR0_TTU_CNTL0, 500 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 501 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 502 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 503 REG_GET(FLIP_PARAMETERS_1, 504 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 505 REG_GET(DCN_CUR0_TTU_CNTL1, 506 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 507 REG_GET(DCN_CUR1_TTU_CNTL1, 508 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 509 REG_GET(DCN_SURF0_TTU_CNTL1, 510 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 511 REG_GET(DCN_SURF1_TTU_CNTL1, 512 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 513 514 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 515 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 516 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 517 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 518 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 519 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 520 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 521 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 522 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 523 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 524 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 525 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 526 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 527 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 528 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 529 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 530 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 531 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 532 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 533 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 534 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 535 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 536 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 537 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 538 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 539 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 540 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 541 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 542 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 543 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 544 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 545 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 546 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 547 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 548 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 549 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 550 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 551 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 552 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 553 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 554 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 555 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 556 557 /* Host VM deadline regs */ 558 REG_GET(VBLANK_PARAMETERS_5, 559 REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); 560 REG_GET(VBLANK_PARAMETERS_6, 561 REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); 562 REG_GET(FLIP_PARAMETERS_3, 563 REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); 564 REG_GET(FLIP_PARAMETERS_4, 565 REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); 566 REG_GET(FLIP_PARAMETERS_5, 567 REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); 568 REG_GET(FLIP_PARAMETERS_6, 569 REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); 570 REG_GET(FLIP_PARAMETERS_2, 571 REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); 572 573 if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) 574 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", 575 dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); 576 if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) 577 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", 578 dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); 579 if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) 580 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", 581 dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); 582 if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) 583 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", 584 dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); 585 if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) 586 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", 587 dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); 588 if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) 589 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", 590 dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); 591 if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) 592 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", 593 dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); 594} 595 596static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs) 597{ 598 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 599 600 REG_UPDATE_3(DCSURF_FLIP_CONTROL, 601 SURFACE_FLIP_TYPE, flip_regs->immediate, 602 SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo, 603 SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo); 604 605 REG_UPDATE(VMID_SETTINGS_0, 606 VMID, flip_regs->vmid); 607 608 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 609 PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface, 610 PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 611 PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 612 PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface, 613 SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface, 614 SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface, 615 SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface, 616 SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface); 617 618 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 619 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 620 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); 621 622 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 623 PRIMARY_META_SURFACE_ADDRESS_C, 624 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); 625 626 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 627 PRIMARY_META_SURFACE_ADDRESS_HIGH, 628 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); 629 630 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 631 PRIMARY_META_SURFACE_ADDRESS, 632 flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS); 633 634 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 635 SECONDARY_META_SURFACE_ADDRESS_HIGH, 636 flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); 637 638 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 639 SECONDARY_META_SURFACE_ADDRESS, 640 flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS); 641 642 643 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 644 SECONDARY_SURFACE_ADDRESS_HIGH, 645 flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); 646 647 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 648 SECONDARY_SURFACE_ADDRESS, 649 flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS); 650 651 652 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 653 PRIMARY_SURFACE_ADDRESS_HIGH_C, 654 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); 655 656 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 657 PRIMARY_SURFACE_ADDRESS_C, 658 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C); 659 660 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 661 PRIMARY_SURFACE_ADDRESS_HIGH, 662 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); 663 664 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 665 PRIMARY_SURFACE_ADDRESS, 666 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS); 667} 668 669static void dmcub_PLAT_54186_wa(struct hubp *hubp, 670 struct surface_flip_registers *flip_regs) 671{ 672 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 673 union dmub_rb_cmd cmd; 674 675 memset(&cmd, 0, sizeof(cmd)); 676 677 cmd.PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA; 678 cmd.PLAT_54186_wa.header.payload_bytes = sizeof(cmd.PLAT_54186_wa.flip); 679 cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = 680 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS; 681 cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 682 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C; 683 cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 684 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 685 cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 686 flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 687 cmd.PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo; 688 cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst; 689 cmd.PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate; 690 cmd.PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface; 691 cmd.PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid; 692 693 PERF_TRACE(); // TODO: remove after performance is stable. 694 dc_wake_and_execute_dmub_cmd(hubp->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 695 PERF_TRACE(); // TODO: remove after performance is stable. 696} 697 698static bool hubp21_program_surface_flip_and_addr( 699 struct hubp *hubp, 700 const struct dc_plane_address *address, 701 bool flip_immediate) 702{ 703 struct surface_flip_registers flip_regs = { 0 }; 704 705 flip_regs.vmid = address->vmid; 706 707 switch (address->type) { 708 case PLN_ADDR_TYPE_GRAPHICS: 709 if (address->grph.addr.quad_part == 0) { 710 BREAK_TO_DEBUGGER(); 711 break; 712 } 713 714 if (address->grph.meta_addr.quad_part != 0) { 715 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 716 address->grph.meta_addr.low_part; 717 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 718 address->grph.meta_addr.high_part; 719 } 720 721 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 722 address->grph.addr.low_part; 723 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 724 address->grph.addr.high_part; 725 break; 726 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 727 if (address->video_progressive.luma_addr.quad_part == 0 728 || address->video_progressive.chroma_addr.quad_part == 0) 729 break; 730 731 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 732 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 733 address->video_progressive.luma_meta_addr.low_part; 734 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 735 address->video_progressive.luma_meta_addr.high_part; 736 737 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 738 address->video_progressive.chroma_meta_addr.low_part; 739 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 740 address->video_progressive.chroma_meta_addr.high_part; 741 } 742 743 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 744 address->video_progressive.luma_addr.low_part; 745 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 746 address->video_progressive.luma_addr.high_part; 747 748 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = 749 address->video_progressive.chroma_addr.low_part; 750 751 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 752 address->video_progressive.chroma_addr.high_part; 753 754 break; 755 case PLN_ADDR_TYPE_GRPH_STEREO: 756 if (address->grph_stereo.left_addr.quad_part == 0) 757 break; 758 if (address->grph_stereo.right_addr.quad_part == 0) 759 break; 760 761 flip_regs.grph_stereo = true; 762 763 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 764 flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS = 765 address->grph_stereo.right_meta_addr.low_part; 766 flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 767 address->grph_stereo.right_meta_addr.high_part; 768 } 769 770 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 771 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = 772 address->grph_stereo.left_meta_addr.low_part; 773 flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 774 address->grph_stereo.left_meta_addr.high_part; 775 } 776 777 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = 778 address->grph_stereo.left_addr.low_part; 779 flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 780 address->grph_stereo.left_addr.high_part; 781 782 flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS = 783 address->grph_stereo.right_addr.low_part; 784 flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 785 address->grph_stereo.right_addr.high_part; 786 787 break; 788 default: 789 BREAK_TO_DEBUGGER(); 790 break; 791 } 792 793 flip_regs.tmz_surface = address->tmz_surface; 794 flip_regs.immediate = flip_immediate; 795 796 if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 797 dmcub_PLAT_54186_wa(hubp, &flip_regs); 798 else 799 program_surface_flip_and_addr(hubp, &flip_regs); 800 801 hubp->request_address = *address; 802 803 return true; 804} 805 806static void hubp21_init(struct hubp *hubp) 807{ 808 // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta 809 // This is a chicken bit to enable the ECO fix. 810 811 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); 812 //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; 813 REG_WRITE(HUBPREQ_DEBUG, 1 << 26); 814} 815static struct hubp_funcs dcn21_hubp_funcs = { 816 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 817 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 818 .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr, 819 .hubp_program_surface_config = hubp1_program_surface_config, 820 .hubp_is_flip_pending = hubp1_is_flip_pending, 821 .hubp_setup = hubp21_setup, 822 .hubp_setup_interdependent = hubp2_setup_interdependent, 823 .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, 824 .set_blank = hubp1_set_blank, 825 .dcc_control = hubp1_dcc_control, 826 .mem_program_viewport = hubp21_set_viewport, 827 .set_cursor_attributes = hubp2_cursor_set_attributes, 828 .set_cursor_position = hubp1_cursor_set_position, 829 .hubp_clk_cntl = hubp1_clk_cntl, 830 .hubp_vtg_sel = hubp1_vtg_sel, 831 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 832 .dmdata_load = hubp2_dmdata_load, 833 .dmdata_status_done = hubp2_dmdata_status_done, 834 .hubp_read_state = hubp2_read_state, 835 .hubp_clear_underflow = hubp1_clear_underflow, 836 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 837 .hubp_init = hubp21_init, 838 .validate_dml_output = hubp21_validate_dml_output, 839 .hubp_set_flip_int = hubp1_set_flip_int, 840}; 841 842bool hubp21_construct( 843 struct dcn21_hubp *hubp21, 844 struct dc_context *ctx, 845 uint32_t inst, 846 const struct dcn_hubp2_registers *hubp_regs, 847 const struct dcn_hubp2_shift *hubp_shift, 848 const struct dcn_hubp2_mask *hubp_mask) 849{ 850 hubp21->base.funcs = &dcn21_hubp_funcs; 851 hubp21->base.ctx = ctx; 852 hubp21->hubp_regs = hubp_regs; 853 hubp21->hubp_shift = hubp_shift; 854 hubp21->hubp_mask = hubp_mask; 855 hubp21->base.inst = inst; 856 hubp21->base.opp_id = OPP_ID_INVALID; 857 hubp21->base.mpcc_id = 0xf; 858 859 return true; 860} 861