#
7222f584 |
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01-Nov-2022 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Use DC_LOG_DC in the trasform pixel function [Why & How] DC now uses a new commit sequence which is more robust since it addresses cases where we need to reorganize pipes based on planes and other parameters. As a result, this new commit sequence reset the DC state by cleaning plane states and re-creating them accordingly with the need. For this reason, the dce_transform_set_pixel_storage_depth can be invoked after a plane state is destroyed and before its re-creation. In this situation and on DCE devices, DC will hit a condition that will trigger a dmesg log that looks like this: Console: switching to colour frame buffer device 240x67 ------------[ cut here ]------------ [..] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 5603 07/28/2020 RIP: 0010:dce_transform_set_pixel_storage_depth+0x3f8/0x480 [amdgpu] [..] RSP: 0018:ffffc9000202b850 EFLAGS: 00010293 RAX: ffffffffa081d100 RBX: ffff888110790000 RCX: 000000000000000c RDX: ffff888100bedbf8 RSI: 0000000000001a50 RDI: ffff88810463c900 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000007 R10: 0000000000000001 R11: 0000000000000f00 R12: ffff88810f500010 R13: ffff888100bedbf8 R14: ffff88810f515688 R15: 0000000000000000 FS: 00007ff0159249c0(0000) GS:ffff88840e940000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ff01528e550 CR3: 0000000002a10000 CR4: 00000000003506e0 Call Trace: <TASK> ? dm_write_reg_func+0x21/0x80 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] dc_stream_set_dither_option+0xfb/0x130 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_crtc_configure_crc_source+0x10b/0x190 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_atomic_commit_tail+0x20a8/0x2a90 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] ? free_unref_page_commit+0x98/0x170 ? free_unref_page+0xcc/0x150 commit_tail+0x94/0x120 drm_atomic_helper_commit+0x10f/0x140 drm_atomic_commit+0x94/0xc0 ? drm_plane_get_damage_clips.cold+0x1c/0x1c drm_client_modeset_commit_atomic+0x203/0x250 drm_client_modeset_commit_locked+0x56/0x150 drm_client_modeset_commit+0x21/0x40 drm_fb_helper_lastclose+0x42/0x70 amdgpu_driver_lastclose_kms+0xa/0x10 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] drm_release+0xda/0x110 __fput+0x89/0x240 task_work_run+0x5c/0x90 do_exit+0x333/0xae0 do_group_exit+0x2d/0x90 __x64_sys_exit_group+0x14/0x20 do_syscall_64+0x5b/0x80 ? exit_to_user_mode_prepare+0x1e/0x140 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7ff016ceaca1 Code: Unable to access opcode bytes at RIP 0x7ff016ceac77. RSP: 002b:00007ffe7a2357e8 EFLAGS: 00000246 ORIG_RAX: 00000000000000e7 RAX: ffffffffffffffda RBX: 00007ff016e15a00 RCX: 00007ff016ceaca1 RDX: 000000000000003c RSI: 00000000000000e7 RDI: 0000000000000000 RBP: 0000000000000000 R08: ffffffffffffff78 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007ff016e15a00 R13: 0000000000000000 R14: 00007ff016e1aee8 R15: 00007ff016e1af00 </TASK> Since this issue only happens in a transition state on DC, this commit replace BREAK_TO_DEBUGGER with DC_LOG_DC. Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
92e2b820 |
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19-Mar-2021 |
Mario Kleiner <mario.kleiner.de@gmail.com> |
drm/amd/display: Make assert in DCE's program_bit_depth_reduction more lenient. This is needed to avoid warnings with linebuffer depth 36 bpp. Testing on a Polaris11, DCE-11.2 on a 10 bit HDR-10 monitor showed no obvious problems, and this 12 bpc limit is consistent with what other function in the DCE bit depth reduction path use. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a316db72 |
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19-Mar-2021 |
Mario Kleiner <mario.kleiner.de@gmail.com> |
drm/amd/display: Increase linebuffer pixel depth to 36bpp. Testing with the photometer shows that at least Raven Ridge DCN-1.0 does not achieve more than 10 bpc effective output precision with a 16 bpc unorm surface of type SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, unless linebuffer depth is increased from LB_PIXEL_DEPTH_30BPP to LB_PIXEL_DEPTH_36BPP. Otherwise precision gets truncated somewhere to 10 bpc effective depth. Strangely this increase was not needed on Polaris11 DCE-11.2 during testing to get 12 bpc effective precision. It also is not needed for fp16 framebuffers. Tested on DCN-1.0 and DCE-11.2. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1916866d |
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20-Jan-2021 |
Mario Kleiner <mario.kleiner.de@gmail.com> |
drm/amd/display: Fix 10/12 bpc setup in DCE output bit depth reduction. In set_clamp(), the comments and definitions for the COLOR_DEPTH_101010 and COLOR_DEPTH_121212 cases directly contradict the code comment which explains how this should work, whereas the COLOR_DEPTH_888 case is consistent with the code comments. Comment says the bitmask should be chosen to align to the top-most 10 or 12 MSB's on a 14 bit bus, but the implementation contradicts that: 10 bit case sets a mask for 12 bpc clamping, whereas 12 bit case sets a mask for 14 bpc clamping. Note that during my limited testing on DCE-8.3 (HDMI deep color) and DCE-11.2 (DP deep color), this didn't have any obvious ill effects, neither did fixing it change anything obvious for the better, so this fix may be inconsequential on DCE, and just reduce the confusion of innocent bystanders when reading the code and trying to investigate problems with 10 bpc+ output. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9a9fba5b |
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11-Jan-2021 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/display/dc/dce/dce_transform: Demote kernel-doc abuse The header doesn't provide any additional parameter descriptions. Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1104: warning: Cannot understand ***************************************************************************** Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Mauro Rossi <issor.oruam@gmail.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b5ffcb48 |
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08-Jan-2021 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/display/dc/dce/dce_transform: Remove 3 unused/legacy variables Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c: In function ‘dce60_transform_set_scaler’: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:496:7: warning: variable ‘filter_updated’ set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c: In function ‘dce60_transform_set_pixel_storage_depth’: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1040:19: warning: variable ‘expan_mode’ set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1040:6: warning: variable ‘pixel_depth’ set but not used [-Wunused-but-set-variable] Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Mauro Rossi <issor.oruam@gmail.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8d96a590 |
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19-Oct-2020 |
Tom Rix <trix@redhat.com> |
drm/amdgpu: remove unneeded break A break is not needed if it is preceded by a return or break Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
102b2f58 |
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15-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2) [Why] DCE6 has specific SCL_HORZ_FILTER_INIT_{LUMA_RGB,CHROMA} registers In DCE6 h_init_luma and h_init_chroma initialization is required Some DCE6 specific SCL_{HORZ,VERT}_FILTER_CONTROL masks were not listed [How] Add the registers and masks in dce_transform.h Add DCE6 specific struct sclh_ratios_inits in dce_transform.h Add dce60_calculate_inits() function Add dce60_program_scl_ratios_inits() function Fix dce60_transform_set_scaler() function v2: remove unused variable (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b70aaf55 |
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10-Jul-2020 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amd/display: dce_transform: add DCE6 specific macros,functions [Why] DCE6 has no SCL_MODE and no SCL_{HORZ,VERT}_FILTER_INIT registers DCE6 has no SCL_BOUNDARY_MODE bit in SCL_CONTROL register DCE6 has Line Buffer programming registers (DC_LB_MEMORY_SPLIT,DC_LB_MEM_SIZE) DCE6 DATA_FORMAT register has only INTERLEAVE_EN bit DCE6 has no Out Clamp Control programming registers (OUT_CLAMP_CONTROL_*) [How] Add DCE6 specific macros definitions for XFM registers and masks Add DCE6 specific registers to dce_transform_registers struct Add DCE6 specific masks to dce_transform_mask struct DCE6 XFM macros/structs changes will avoid buiding errors when using DCE6 headers Add dce60_setup_scaling_configuration() w/o missing Scaling registers/bit programming Add dce60_transform_set_scaler() using DCE6 Line Buffer programming registers Add dce60_program_bit_depth_reduction() w/o Out Clamp Control programming Add dce60_transform_set_pixel_storage_depth() use dce60_program_bit_depth_reduction() Use dce60_transform_set_scaler() in dce60_transform_funcs Use dce60_transform_set_pixel_storage_depth() in dce60_transform_funcs Add DCE6 specific dce60_transform_construct Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf53769d |
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03-Jul-2018 |
Gloria Li <geling.li@amd.com> |
drm/amd/display: add HDR visual confirm [Why] Testing team wants a way to tell if HDR is on or not [How] Program the overscan color to visually indicate the HDR state of the top-most plane Signed-off-by: Gloria Li <geling.li@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
eb0e5154 |
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18-Apr-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: get rid of 32.32 unsigned fixed point 32.32 is redundant, 31.32 does everything we use 32.32 for Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1296423b |
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20-Feb-2018 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: define DC_LOGGER for logger Created a DC_LOGGER define. This is used to pass the logger into the macros. Anywhere we need to use the logger we need to define DC_LOGGER Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f3fd67a |
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16-Feb-2018 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Use MACROS instead of dm_logger Created MACROS for all log levels. Also Replaced usage of dm_logger_write to the defined MACROS Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
60c118c6 |
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06-Feb-2018 |
Leo (Sunpeng) Li <sunpeng.li@amd.com> |
drm/amd/display: Rework DCE transform bit depth reduction programming. Clear up the logic, and enable programming truncation as a bit reduction mode. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
71d0a898 |
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07-Feb-2018 |
Matthias Kaehlcke <mka@chromium.org> |
amdgpu/dc: Fix enum mismatch in calls to program_color_matrix() The driver passes GRAPHICS_CSC_ADJUST_TYPE_SW of type enum graphics_csc_adjust_type to program_color_matrix(), however the function expects a parameter of type enum grph_color_adjust_option. Supposedly the intention was to pass GRPH_COLOR_MATRIX_SW, which has the same value as GRAPHICS_CSC_ADJUST_TYPE_SW, so the mismatch didn't cause any trouble. Pass GRPH_COLOR_MATRIX_SW to program_color_matrix() instead of GRAPHICS_CSC_ADJUST_TYPE_SW, this also fixes the following warning when building the kernel with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1129:24: error: implicit conversion from enumeration type 'enum graphics_csc_adjust_type' to different enumeration type 'enum grph_color_adjust_option' [-Werror,-Wenum-conversion] xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
146a9f63 |
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15-Dec-2017 |
Krunoslav Kovac <Krunoslav.Kovac@amd.com> |
drm/amd/display: Pass full 3x4 remap matrix for color transform Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bd1be8e8 |
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01-Nov-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: A few more color indentation changes Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a696dc20 |
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31-Oct-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Remove unused register read in program_pwl Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b310b081 |
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31-Oct-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Bunch more color indentation cleanups Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
97110c98 |
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31-Oct-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Remove extra arr_points element arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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efd52204 |
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31-Oct-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Bunch of indentation cleanups in color stuff Trying to align with kernel coding style and make it a bit more readable. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4dec2aa9 |
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28-Sep-2017 |
Dave Airlie <airlied@redhat.com> |
amdgpu/dc: make program_regamma_pwl return void The return value was unused. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5fb005c4 |
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28-Sep-2017 |
Dave Airlie <airlied@redhat.com> |
amdgpu/dc: make dce transform constructor void This never returns anything but true. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c0dc2b9 |
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27-Sep-2017 |
Dave Airlie <airlied@redhat.com> |
amdgpu/dc: move filter taps to being static const data (v2) This just adds two accessor methods, and moves all the data to static const. v2: fix dcn build. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7a09f5be |
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28-Jul-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: move regamma from opp to dpp for dce Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bdf9a1a0 |
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25-Jul-2017 |
Yue Hin Lau <Yuehin.Lau@amd.com> |
drm/amd/display: move ocsc programming from opp to dpp for dce Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ce9c0880 |
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22-Feb-2017 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: move visual confirm recout adjustment to scaler Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
beed42b5 |
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14-Feb-2017 |
Jordan Lazare <Jordan.Lazare@amd.com> |
drm/amd/display: Don't attempt to program missing register fields on DCE8 When moving to a common dce/ infrastructure for all asics, some register fields do not exist in DCE8, and cause ASSERTS and debug spam. Instead, check to see whether a register field mask is valid before attempting to program the register field Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
30018e9f |
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12-Dec-2016 |
Zeyu Fan <Zeyu.Fan@amd.com> |
drm/amd/display: Fix HDMI scaling corruption issue. Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a33fa99d |
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06-Dec-2016 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Fix bunch of warnings in DC Some of those are potential bugs Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4562236b |
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12-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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