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c005a44f |
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11-Jul-2023 |
George Shen <george.shen@amd.com> |
drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family [Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3a87e25a |
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27-Jun-2023 |
Daniel Miess <daniel.miess@amd.com> |
drm/amd/display: Fix DP2 link training failure with RCO [Why] When RCO is enabled for symclk32_le we get failures during DP2 link traing compliance tests. [How] Break out symclk32_le RCO into a separate function that is called for hpo when link is enabled/disabled. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25b054c3 |
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11-Jul-2023 |
George Shen <george.shen@amd.com> |
drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family [Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
30f90f3c |
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28-Apr-2023 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Skip DPP DTO update if root clock is gated [Why] Hardware implements root clock gating by utilizing the DPP DTO registers with a special case of DTO enabled, phase = 0, modulo = 1. This conflicts with our policy to always update the DPPDTO for cases where it's expected to be disabled. The pipes unexpectedly enter a higher power state than expected because of this programming flow. [How] Guard the upper layers of HWSS against this hardware quirk with programming the register with an internal state flag in DCCG. While technically acting as global state for the DCCG, HWSS shouldn't be expected to understand the hardware quirk for having DTO disabled causing more power than DTO enabled with this specific setting. This also prevents sequencing errors from occuring in the future if we have to program DPP DTO in multiple locations. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a2a0bdf1 |
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23-Mar-2023 |
Charlene Liu <Charlene.Liu@amd.com> |
drm/amd/display: add dscclk instance offset check [why] based on dscclk instance offset check conditiona program dscclk Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf224e00 |
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13-Mar-2023 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Fix 4to1 MPC black screen with DPP RCO [Why] DPP Root clock optimization when combined with 4to1 MPC combine results in the screen turning black. This is because the DPPCLK is stopped during the middle of an optimize_bandwidth sequence during commit_minimal_transition without going through plane power down/power up. [How] The intent of a 0Hz DPP clock through update_clocks is to disable the DTO. This differs from the behavior of stopping the DPPCLK entirely (utilizing a 0Hz clock on some ASIC) so it's better to move this logic to reside next to plane power up/power down where we gate the HUBP/DPP DOMAIN. The new sequence should be: Power down: PG enabled -> RCO on Power up: RCO off -> PG disabled Rename power_on_plane to power_on_plane_resources to reflect the actual operation that's occurring. Cc: stable@vger.kernel.org Cc: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1f5dcb73 |
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10-Jun-2022 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Fix dpstreamclk programming [WHY] Currently programming incorrect hpo inst as well as selecting incorrect source [HOW] Use hpo inst instead of otg inst to select dpstreamclk inst Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ee7b62e1 |
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28-Jun-2022 |
Roman Li <roman.li@amd.com> |
drm/amd/display: Enable DCN314 in DC Add support for DCN 3.1.4 in Display Core Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b94b02d7 |
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06-Jun-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/display: make some functions static Fixes "no previous prototype" warnings. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
405bb9ee |
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29-Apr-2022 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Implement DTBCLK ref switching on dcn32 [WHY & HOW] Implements DTB ref clock switching with reg key default to OFF. Refactors dccg DTBCLK logic to not store redundant state information dccg. Also removes duplicated functions that should be inherited from other dcn versions. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d3dfceb5 |
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23-Feb-2022 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Add dependant changes for DCN32/321 [Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a8201902 |
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13-May-2022 |
Leung, Martin <Martin.Leung@amd.com> |
drm/amdgpu/display: Prepare for new interfaces why: lut pipeline will be hooked up differently in some asics need to add new interfaces how: add them Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Martin <martin.leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f0ad66f4 |
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12-May-2022 |
Alvin <Alvin.Lee2@amd.com> |
drm/amd/display: Don't clear ref_dtbclk value [Description] ref_dtbclk value is assigned in clk_mgr_construct, but the clks struct is cleared in init_clocks. Make sure to restore the value or we will get 0 value for ref_dtbclk in DCN31. Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6ecf9773 |
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12-May-2022 |
Hung, Cruise <Cruise.Hung@amd.com> |
drm/amd/display: Fix DMUB outbox trace in S4 (#4465) [Why] DMUB Outbox0 read/write pointer not sync after resumed from S4. And that caused old traces were sent to outbox. [How] Disable DMUB Outbox0 interrupt and clear DMUB Outbox0 read/write pointer when resumes from S4. And then enable Outbox0 interrupt before starts DMCUB. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ec74408 |
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09-May-2022 |
Leung, Martin <Martin.Leung@amd.com> |
drm/amd/display: revert Blank eDP on disable/enable drv why and how: Revert this change. It was causing a black screen with certain blocks Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Leung, Martin <Martin.Leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
05d6aea3 |
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23-Jan-2022 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Disable physym clock [How & Why] Disable physym clock when it's not in use. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0015cce5 |
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23-Jan-2022 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Fix disabling dccg clocks [How & Why] Updated procedure to match hardware programming guide. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
240e6d25 |
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08-Dec-2021 |
Isabella Basso <isabbasso@riseup.net> |
drm/amd/display: fix function scopes This turns previously global functions into static, thus removing compile-time warnings such as: warning: no previous prototype for 'get_highest_allowed_voltage_level' [-Wmissing-prototypes] 742 | unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ warning: no previous prototype for 'rv1_vbios_smu_send_msg_with_param' [-Wmissing-prototypes] 102 | int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Changes since v1: - As suggested by Rodrigo Siqueira: 1. Rewrite function signatures to make them more readable. 2. Get rid of unused functions in order to remove 'defined but not used' warnings. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Isabella Basso <isabbasso@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bda24462 |
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22-Sep-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le [Why & How] Disable dpstreamclk, symclk32_se, and symclk32_le when not in use. Reviewed-by: Ariel Bernstein <eric.yang2@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e22ad7e3 |
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22-Sep-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Disable dsc root clock when not being used [Why & How] Disable root clock for dsc when not being used. Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3cf79bb7 |
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28-Sep-2021 |
Hansen <Hansen.Dsouza@amd.com> |
drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7a28bee0 |
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22-Sep-2021 |
Jake Wang <haonan.wang2@amd.com> |
drm/amd/display: Disable dpp root clock when not being used [Why & How] Disable root clock for dpp when not being used. Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d76b12da |
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26-Jul-2021 |
Fangzhi Zuo <Jerry.Zuo@amd.com> |
drm/amd/display: Add DP 2.0 DCCG HW Blocks: +--------+ +-----+ +------+ | OPTC | | HDA | | HUBP | +--------+ +-----+ +------+ | | | | | | HPO ====|==========|========|==== | | v | | | +-----+ | | | | APG | | | | +-----+ | | | | | | v v v | +---------------------+ | | HPO Stream Encoder | | +---------------------+ | | | v | +--------------------+ | | HPO Link Encoder | | +--------------------+ | | v ===============|============= v +------------------+ | DIO Output Mux | +------------------+ | v +-----+ | PHY | +-----+ | PHYD32CLK[0] v +------+ | DCCG | +------+ | v SYMCLK32 Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d8a2b4f3 |
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19-May-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Add DCN3.1 DCCG Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ | DCCG | +--------+ Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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