Searched refs:Mips (Results 26 - 50 of 61) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp15 #include "Mips.h"
60 MIB.addReg(Mips::DSPPos, Flag);
63 MIB.addReg(Mips::DSPSCount, Flag);
66 MIB.addReg(Mips::DSPCarry, Flag);
69 MIB.addReg(Mips::DSPOutFlag, Flag);
72 MIB.addReg(Mips::DSPCCond, Flag);
75 MIB.addReg(Mips::DSPEFI, Flag);
80 return Mips::MSACtrlRegClass.getRegister(RegNum);
88 if ((MI.getOpcode() == Mips::ADDiu) &&
89 (MI.getOperand(1).getReg() == Mips
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H A DMips16FrameLowering.cpp62 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
87 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
88 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
104 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
105 .addReg(Mips::S0);
109 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
131 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
170 bool SaveS2 = Reserved[Mips
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H A DMipsFastISel.cpp1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
305 Opc = Mips::AND;
308 Opc = Mips::OR;
311 Opc = Mips::XOR;
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
359 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
369 unsigned Opc = Mips::ADDiu;
370 emitInst(Opc, ResultReg).addReg(Mips
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H A DMipsConstantIslandPass.cpp22 #include "Mips.h"
90 case Mips::Bimm16:
91 case Mips::BimmX16:
92 case Mips::Bteqz16:
93 case Mips::BteqzX16:
94 case Mips::Btnez16:
95 case Mips::BtnezX16:
96 case Mips::JalB16:
98 case Mips::BeqzRxImm16:
99 case Mips
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H A DMips16RegisterInfo.cpp14 #include "Mips.h"
64 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
65 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
72 return &Mips::CPU16RegsRegClass;
102 FrameReg = Mips::SP;
106 FrameReg = Mips::S0;
112 FrameReg = Mips::SP;
H A DMipsISelLowering.cpp1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips
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H A DMipsAnalyzeImmediate.cpp10 #include "Mips.h"
134 ADDiu = Mips::ADDiu;
135 ORi = Mips::ORi;
136 SLL = Mips::SLL;
137 LUi = Mips::LUi;
139 ADDiu = Mips::DADDiu;
140 ORi = Mips::ORi64;
141 SLL = Mips::DSLL;
142 LUi = Mips::LUi64;
H A DMips16ISelDAGToDAG.cpp15 #include "Mips.h"
53 unsigned Opcode = Mips::Mflo16;
58 unsigned Opcode = Mips::Mfhi16;
76 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
89 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
197 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips
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H A DMipsSEISelLowering.cpp68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
89 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
118 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
119 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
120 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
121 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
122 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
123 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
124 addMSAFloatType(MVT::v2f64, &Mips
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H A DMipsFrameLowering.cpp1 //===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===//
9 // This file contains the Mips implementation of TargetFrameLowering class.
140 unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
144 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
H A DMipsDelaySlotFiller.cpp1 //===- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler -------------------===//
14 #include "Mips.h"
217 StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
355 Defs.set(Mips::RA);
361 Defs.reset(Mips::AT);
371 if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) {
372 Defs.set(Mips::RA);
373 Defs.set(Mips::RA_64);
379 CallerSavedRegs.reset(Mips
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H A DMipsMCInstLower.cpp1 //===- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ----------===//
9 // This file contains code to lower Mips MachineInstrs to their corresponding
216 OutMI.setOpcode(Mips::LUi);
299 case Mips::LONG_BRANCH_LUi:
300 case Mips::LONG_BRANCH_LUi2Op:
301 case Mips::LONG_BRANCH_LUi2Op_64:
304 case Mips::LONG_BRANCH_ADDiu:
305 case Mips::LONG_BRANCH_ADDiu2Op:
306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
308 case Mips
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H A DMipsCallLowering.cpp142 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
147 .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64
148 : Mips::BuildPairF64)
156 } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
157 MIRBuilder.buildInstr(Mips::MTC1)
257 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
259 .buildInstr(STI.isFP64bit() ? Mips
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H A DMipsLegalizerInfo.cpp9 /// This file implements the targeting of the Machinelegalizer class for Mips.
292 STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64},
375 MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
397 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
399 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
401 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
403 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
410 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
412 return SelectMSA3OpIntrinsic(MI, Mips
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H A DMipsOptimizePICCall.cpp15 #include "Mips.h"
82 StringRef getPassName() const override { return "Mips OptimizePICCall"; }
155 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
168 unsigned Reg = Ty == MVT::i32 ? Mips::GP : Mips::GP_64;
H A DMipsSubtarget.cpp1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
9 // This file implements the Mips specific subclass of TargetSubtargetInfo.
14 #include "Mips.h"
46 "floating point as Mips 16"),
229 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
230 : &Mips::GPR32RegClass);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
9 // This file provides Mips specific target streamer methods.
38 return STI->getFeatureBits()[Mips::FeatureMicroMips];
42 : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
260 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
268 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
272 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
278 emitRR(Mips::MOVE16_MM, Mips
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H A DMipsInstPrinter.h1 //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
9 // This class prints a Mips MCInst to a .s file.
21 namespace Mips { namespace in namespace:llvm
22 // Mips Branch Codes
31 // Mips Condition Codes
72 const char *MipsFCCToString(Mips::CondCode CC);
73 } // end namespace Mips
H A DMipsAsmBackend.h1 //===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
52 return Mips::NumTargetFixupKinds;
H A DMipsFixupKinds.h1 //===-- MipsFixupKinds.h - Mips Specific Fixup Entries ----------*- C++ -*-===//
15 namespace Mips { namespace in namespace:llvm
21 // MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
229 } // namespace Mips
H A DMipsMCTargetDesc.cpp1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
9 // This file provides Mips specific target descriptions.
47 /// Select the Mips CPU for the given triple and cpu name.
73 InitMipsMCRegisterInfo(X, Mips::RA);
88 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
/freebsd-12-stable/contrib/llvm-project/lld/ELF/Arch/
H A DMipsArchTree.cpp316 if (fpB == Mips::Val_GNU_MIPS_ABI_FP_ANY)
318 if (fpB == Mips::Val_GNU_MIPS_ABI_FP_64A &&
319 fpA == Mips::Val_GNU_MIPS_ABI_FP_64)
321 if (fpB != Mips::Val_GNU_MIPS_ABI_FP_XX)
323 if (fpA == Mips::Val_GNU_MIPS_ABI_FP_DOUBLE ||
324 fpA == Mips::Val_GNU_MIPS_ABI_FP_64 ||
325 fpA == Mips::Val_GNU_MIPS_ABI_FP_64A)
332 case Mips::Val_GNU_MIPS_ABI_FP_ANY:
334 case Mips::Val_GNU_MIPS_ABI_FP_DOUBLE:
336 case Mips
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMipsABIFlags.h20 namespace Mips { namespace in namespace:llvm
/freebsd-12-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaChecking.cpp3152 if (Mips::BI__builtin_mips_addu_qb <= BuiltinID &&
3153 BuiltinID <= Mips::BI__builtin_mips_lwx) {
3158 if (Mips::BI__builtin_mips_absq_s_qb <= BuiltinID &&
3159 BuiltinID <= Mips::BI__builtin_mips_subuh_r_qb) {
3165 if (Mips::BI__builtin_msa_add_a_b <= BuiltinID &&
3166 BuiltinID <= Mips::BI__builtin_msa_xori_b) {
3187 case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break;
3188 case Mips::BI__builtin_mips_rddsp: i = 0; l = 0; u = 63; break;
3189 case Mips::BI__builtin_mips_append: i = 2; l = 0; u = 31; break;
3190 case Mips
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/freebsd-12-stable/lib/clang/libllvm/
H A DMakefile21 .for arch in AArch64 ARM BPF Mips PowerPC RISCV Sparc X86
1109 SRCS_MIN+= Target/Mips/AsmParser/MipsAsmParser.cpp
1110 SRCS_XDW+= Target/Mips/Disassembler/MipsDisassembler.cpp
1111 SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
1112 SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIInfo.cpp
1113 SRCS_MIN+= Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
1114 SRCS_MIN+= Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
1115 SRCS_MIN+= Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
1116 SRCS_MIN+= Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
1117 SRCS_MIN+= Target/Mips/MCTargetDes
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