Lines Matching refs:Mips
68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
89 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
118 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
119 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
120 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
121 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
122 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
123 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
124 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
127 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
172 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
177 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
311 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
1072 case Mips::BPOSGE32_PSEUDO:
1074 case Mips::SNZ_B_PSEUDO:
1075 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1076 case Mips::SNZ_H_PSEUDO:
1077 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1078 case Mips::SNZ_W_PSEUDO:
1079 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1080 case Mips::SNZ_D_PSEUDO:
1081 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1082 case Mips::SNZ_V_PSEUDO:
1083 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1084 case Mips::SZ_B_PSEUDO:
1085 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1086 case Mips::SZ_H_PSEUDO:
1087 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1088 case Mips::SZ_W_PSEUDO:
1089 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1090 case Mips::SZ_D_PSEUDO:
1091 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1092 case Mips::SZ_V_PSEUDO:
1093 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1094 case Mips::COPY_FW_PSEUDO:
1096 case Mips::COPY_FD_PSEUDO:
1098 case Mips::INSERT_FW_PSEUDO:
1100 case Mips::INSERT_FD_PSEUDO:
1102 case Mips::INSERT_B_VIDX_PSEUDO:
1103 case Mips::INSERT_B_VIDX64_PSEUDO:
1105 case Mips::INSERT_H_VIDX_PSEUDO:
1106 case Mips::INSERT_H_VIDX64_PSEUDO:
1108 case Mips::INSERT_W_VIDX_PSEUDO:
1109 case Mips::INSERT_W_VIDX64_PSEUDO:
1111 case Mips::INSERT_D_VIDX_PSEUDO:
1112 case Mips::INSERT_D_VIDX64_PSEUDO:
1114 case Mips::INSERT_FW_VIDX_PSEUDO:
1115 case Mips::INSERT_FW_VIDX64_PSEUDO:
1117 case Mips::INSERT_FD_VIDX_PSEUDO:
1118 case Mips::INSERT_FD_VIDX64_PSEUDO:
1120 case Mips::FILL_FW_PSEUDO:
1122 case Mips::FILL_FD_PSEUDO:
1124 case Mips::FEXP2_W_1_PSEUDO:
1126 case Mips::FEXP2_D_1_PSEUDO:
1128 case Mips::ST_F16:
1130 case Mips::LD_F16:
1132 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1134 case Mips::MSA_FP_ROUND_W_PSEUDO:
1136 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1138 case Mips::MSA_FP_ROUND_D_PSEUDO:
3039 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3063 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3065 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3069 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3070 .addReg(Mips::ZERO).addImm(0);
3071 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3075 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3076 .addReg(Mips::ZERO).addImm(1);
3079 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3108 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3138 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3139 .addReg(Mips::ZERO).addImm(0);
3140 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3144 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3145 .addReg(Mips::ZERO).addImm(1);
3148 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3184 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3186 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3189 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3192 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3193 : &Mips::MSA128WEvensRegClass);
3195 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3196 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3226 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3228 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3230 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3231 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3255 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3256 : &Mips::MSA128WEvensRegClass);
3258 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3261 .addImm(Mips::sub_lo);
3262 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3290 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3292 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3295 .addImm(Mips::sub_64);
3296 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3340 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3341 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3342 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
3351 InsertOp = Mips::INSERT_B;
3352 InsveOp = Mips::INSVE_B;
3353 VecRC = &Mips::MSA128BRegClass;
3357 InsertOp = Mips::INSERT_H;
3358 InsveOp = Mips::INSVE_H;
3359 VecRC = &Mips::MSA128HRegClass;
3363 InsertOp = Mips::INSERT_W;
3364 InsveOp = Mips::INSVE_W;
3365 VecRC = &Mips::MSA128WRegClass;
3369 InsertOp = Mips::INSERT_D;
3370 InsveOp = Mips::INSVE_D;
3371 VecRC = &Mips::MSA128DRegClass;
3377 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3380 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3395 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3420 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3422 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3424 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3449 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3450 : &Mips::MSA128WEvensRegClass);
3452 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3453 : &Mips::MSA128WEvensRegClass);
3455 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3456 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3459 .addImm(Mips::sub_lo);
3460 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3483 Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3484 Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3486 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3487 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3490 .addImm(Mips::sub_64);
3491 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3525 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3526 : &Mips::GPR64RegClass);
3527 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3528 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3530 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3532 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3533 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3536 .addImm(Mips::sub_32);
3539 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3577 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3578 : &Mips::GPR64RegClass);
3580 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3584 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3589 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3590 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3594 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3668 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3670 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3672 ? Mips::DMFC1
3673 : (IsFGR64onMips32 ? Mips::MFC1_D64 : Mips::MFC1);
3674 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3684 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3685 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3686 Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3687 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3691 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3699 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3700 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3706 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3774 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3776 ? Mips::DMTC1
3777 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1);
3778 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3780 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3783 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3785 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3786 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3792 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3799 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3802 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3822 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3828 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3829 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3832 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3851 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3857 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3858 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3861 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())