Lines Matching refs:Mips
1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
305 Opc = Mips::AND;
308 Opc = Mips::OR;
311 Opc = Mips::XOR;
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
359 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
369 unsigned Opc = Mips::ADDiu;
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
381 emitInst(Mips::LUi, TmpReg).addImm(Hi);
382 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
384 emitInst(Mips::LUi, ResultReg).addImm(Hi);
394 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
396 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
400 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
402 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
404 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
405 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
415 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
422 emitInst(Mips::LW, DestReg)
428 emitInst(Mips::ADDiu, TempReg)
437 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
439 emitInst(Mips::LW, DestReg)
653 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
654 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
655 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
659 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
660 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
665 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
668 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
671 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
672 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
673 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
677 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
678 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
679 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
683 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
686 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
689 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
690 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
691 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
695 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
696 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
697 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
715 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
716 CondMovOpc = Mips::MOVT_I;
719 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
720 CondMovOpc = Mips::MOVF_I;
723 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
724 CondMovOpc = Mips::MOVT_I;
727 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
728 CondMovOpc = Mips::MOVT_I;
731 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
732 CondMovOpc = Mips::MOVF_I;
735 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
736 CondMovOpc = Mips::MOVF_I;
741 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
742 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
745 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
749 .addReg(Mips::FCC0)
765 ResultReg = createResultReg(&Mips::GPR32RegClass);
766 Opc = Mips::LW;
769 ResultReg = createResultReg(&Mips::GPR32RegClass);
770 Opc = Mips::LHu;
773 ResultReg = createResultReg(&Mips::GPR32RegClass);
774 Opc = Mips::LBu;
779 ResultReg = createResultReg(&Mips::FGR32RegClass);
780 Opc = Mips::LWC1;
785 ResultReg = createResultReg(&Mips::AFGR64RegClass);
786 Opc = Mips::LDC1;
821 Opc = Mips::SB;
824 Opc = Mips::SH;
827 Opc = Mips::SW;
832 Opc = Mips::SWC1;
837 Opc = Mips::SDC1;
962 ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
979 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
988 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1012 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
1013 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1034 CondMovOpc = Mips::MOVN_I_I;
1035 RC = &Mips::GPR32RegClass;
1037 CondMovOpc = Mips::MOVN_I_S;
1038 RC = &Mips::FGR32RegClass;
1040 CondMovOpc = Mips::MOVN_I_D32;
1041 RC = &Mips::AFGR64RegClass;
1054 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1089 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1093 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1127 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1128 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1129 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1133 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1152 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1163 VA.convertToReg(Mips::F12);
1166 VA.convertToReg(Mips::D6_64);
1168 VA.convertToReg(Mips::D6);
1173 VA.convertToReg(Mips::F14);
1176 VA.convertToReg(Mips::D7_64);
1178 VA.convertToReg(Mips::D7);
1187 VA.convertToReg(Mips::A0);
1190 VA.convertToReg(Mips::A1);
1193 VA.convertToReg(Mips::A2);
1196 VA.convertToReg(Mips::A3);
1237 llvm_unreachable("Mips does not use custom args.");
1242 // from the AArch64 port and should be essentially fine for Mips too.
1263 Addr.setReg(Mips::SP);
1282 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1334 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1335 Mips::A3}};
1336 std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1337 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1392 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1412 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1429 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1448 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1560 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1563 Mips::RA).addReg(Mips::T9);
1603 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1608 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1614 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1618 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1619 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1620 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1621 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1627 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1628 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1629 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1635 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1640 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1641 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1642 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1643 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1645 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1646 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1648 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1649 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1650 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1774 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1824 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1845 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1846 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1847 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1857 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1860 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1893 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1913 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1933 DivOpc = Mips::SDIV;
1937 DivOpc = Mips::UDIV;
1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1949 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1954 ? Mips::MFHI
1955 : Mips::MFLO;
1968 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1980 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1999 Opcode = Mips::SLL;
2002 Opcode = Mips::SRA;
2005 Opcode = Mips::SRL;
2022 Opcode = Mips::SLLV;
2025 Opcode = Mips::SRAV;
2028 Opcode = Mips::SRLV;
2106 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2117 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2118 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2119 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2135 if (MachineInstOpcode == Mips::MUL) {
2143 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2144 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2154 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,