Lines Matching refs:Mips
1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
302 // Mips does not have i1 type, so use i32 for
344 // Mips Custom Operations
400 // Operations not directly supported by Mips.
522 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
556 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
573 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
574 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
603 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
607 case ISD::SETOEQ: return Mips::FCOND_OEQ;
608 case ISD::SETUNE: return Mips::FCOND_UNE;
610 case ISD::SETOLT: return Mips::FCOND_OLT;
612 case ISD::SETOGT: return Mips::FCOND_OGT;
614 case ISD::SETOLE: return Mips::FCOND_OLE;
616 case ISD::SETOGE: return Mips::FCOND_OGE;
617 case ISD::SETULT: return Mips::FCOND_ULT;
618 case ISD::SETULE: return Mips::FCOND_ULE;
619 case ISD::SETUGT: return Mips::FCOND_UGT;
620 case ISD::SETUGE: return Mips::FCOND_UGE;
621 case ISD::SETUO: return Mips::FCOND_UN;
622 case ISD::SETO: return Mips::FCOND_OR;
624 case ISD::SETONE: return Mips::FCOND_ONE;
625 case ISD::SETUEQ: return Mips::FCOND_UEQ;
631 static bool invertFPCondCodeUser(Mips::CondCode CC) {
632 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
635 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
668 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
669 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1276 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1278 .addReg(Mips::ZERO)
1283 MIB->getOperand(0).setSubReg(Mips::sub_32);
1300 case Mips::ATOMIC_LOAD_ADD_I8:
1302 case Mips::ATOMIC_LOAD_ADD_I16:
1304 case Mips::ATOMIC_LOAD_ADD_I32:
1306 case Mips::ATOMIC_LOAD_ADD_I64:
1309 case Mips::ATOMIC_LOAD_AND_I8:
1311 case Mips::ATOMIC_LOAD_AND_I16:
1313 case Mips::ATOMIC_LOAD_AND_I32:
1315 case Mips::ATOMIC_LOAD_AND_I64:
1318 case Mips::ATOMIC_LOAD_OR_I8:
1320 case Mips::ATOMIC_LOAD_OR_I16:
1322 case Mips::ATOMIC_LOAD_OR_I32:
1324 case Mips::ATOMIC_LOAD_OR_I64:
1327 case Mips::ATOMIC_LOAD_XOR_I8:
1329 case Mips::ATOMIC_LOAD_XOR_I16:
1331 case Mips::ATOMIC_LOAD_XOR_I32:
1333 case Mips::ATOMIC_LOAD_XOR_I64:
1336 case Mips::ATOMIC_LOAD_NAND_I8:
1338 case Mips::ATOMIC_LOAD_NAND_I16:
1340 case Mips::ATOMIC_LOAD_NAND_I32:
1342 case Mips::ATOMIC_LOAD_NAND_I64:
1345 case Mips::ATOMIC_LOAD_SUB_I8:
1347 case Mips::ATOMIC_LOAD_SUB_I16:
1349 case Mips::ATOMIC_LOAD_SUB_I32:
1351 case Mips::ATOMIC_LOAD_SUB_I64:
1354 case Mips::ATOMIC_SWAP_I8:
1356 case Mips::ATOMIC_SWAP_I16:
1358 case Mips::ATOMIC_SWAP_I32:
1360 case Mips::ATOMIC_SWAP_I64:
1363 case Mips::ATOMIC_CMP_SWAP_I8:
1365 case Mips::ATOMIC_CMP_SWAP_I16:
1367 case Mips::ATOMIC_CMP_SWAP_I32:
1369 case Mips::ATOMIC_CMP_SWAP_I64:
1372 case Mips::ATOMIC_LOAD_MIN_I8:
1374 case Mips::ATOMIC_LOAD_MIN_I16:
1376 case Mips::ATOMIC_LOAD_MIN_I32:
1378 case Mips::ATOMIC_LOAD_MIN_I64:
1381 case Mips::ATOMIC_LOAD_MAX_I8:
1383 case Mips::ATOMIC_LOAD_MAX_I16:
1385 case Mips::ATOMIC_LOAD_MAX_I32:
1387 case Mips::ATOMIC_LOAD_MAX_I64:
1390 case Mips::ATOMIC_LOAD_UMIN_I8:
1392 case Mips::ATOMIC_LOAD_UMIN_I16:
1394 case Mips::ATOMIC_LOAD_UMIN_I32:
1396 case Mips::ATOMIC_LOAD_UMIN_I64:
1399 case Mips::ATOMIC_LOAD_UMAX_I8:
1401 case Mips::ATOMIC_LOAD_UMAX_I16:
1403 case Mips::ATOMIC_LOAD_UMAX_I32:
1405 case Mips::ATOMIC_LOAD_UMAX_I64:
1408 case Mips::PseudoSDIV:
1409 case Mips::PseudoUDIV:
1410 case Mips::DIV:
1411 case Mips::DIVU:
1412 case Mips::MOD:
1413 case Mips::MODU:
1416 case Mips::SDIV_MM_Pseudo:
1417 case Mips::UDIV_MM_Pseudo:
1418 case Mips::SDIV_MM:
1419 case Mips::UDIV_MM:
1420 case Mips::DIV_MMR6:
1421 case Mips::DIVU_MMR6:
1422 case Mips::MOD_MMR6:
1423 case Mips::MODU_MMR6:
1425 case Mips::PseudoDSDIV:
1426 case Mips::PseudoDUDIV:
1427 case Mips::DDIV:
1428 case Mips::DDIVU:
1429 case Mips::DMOD:
1430 case Mips::DMODU:
1433 case Mips::PseudoSELECT_I:
1434 case Mips::PseudoSELECT_I64:
1435 case Mips::PseudoSELECT_S:
1436 case Mips::PseudoSELECT_D32:
1437 case Mips::PseudoSELECT_D64:
1438 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1439 case Mips::PseudoSELECTFP_F_I:
1440 case Mips::PseudoSELECTFP_F_I64:
1441 case Mips::PseudoSELECTFP_F_S:
1442 case Mips::PseudoSELECTFP_F_D32:
1443 case Mips::PseudoSELECTFP_F_D64:
1444 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1445 case Mips::PseudoSELECTFP_T_I:
1446 case Mips::PseudoSELECTFP_T_I64:
1447 case Mips::PseudoSELECTFP_T_S:
1448 case Mips::PseudoSELECTFP_T_D32:
1449 case Mips::PseudoSELECTFP_T_D64:
1450 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1451 case Mips::PseudoD_SELECT_I:
1452 case Mips::PseudoD_SELECT_I64:
1457 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1458 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1471 case Mips::ATOMIC_LOAD_ADD_I32:
1472 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1474 case Mips::ATOMIC_LOAD_SUB_I32:
1475 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1477 case Mips::ATOMIC_LOAD_AND_I32:
1478 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1480 case Mips::ATOMIC_LOAD_OR_I32:
1481 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1483 case Mips::ATOMIC_LOAD_XOR_I32:
1484 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1486 case Mips::ATOMIC_LOAD_NAND_I32:
1487 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1489 case Mips::ATOMIC_SWAP_I32:
1490 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1492 case Mips::ATOMIC_LOAD_ADD_I64:
1493 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1495 case Mips::ATOMIC_LOAD_SUB_I64:
1496 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1498 case Mips::ATOMIC_LOAD_AND_I64:
1499 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1501 case Mips::ATOMIC_LOAD_OR_I64:
1502 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1504 case Mips::ATOMIC_LOAD_XOR_I64:
1505 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1507 case Mips::ATOMIC_LOAD_NAND_I64:
1508 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1510 case Mips::ATOMIC_SWAP_I64:
1511 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1513 case Mips::ATOMIC_LOAD_MIN_I32:
1514 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1517 case Mips::ATOMIC_LOAD_MAX_I32:
1518 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1521 case Mips::ATOMIC_LOAD_UMIN_I32:
1522 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1525 case Mips::ATOMIC_LOAD_UMAX_I32:
1526 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1529 case Mips::ATOMIC_LOAD_MIN_I64:
1530 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1533 case Mips::ATOMIC_LOAD_MAX_I64:
1534 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1537 case Mips::ATOMIC_LOAD_UMIN_I64:
1538 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1541 case Mips::ATOMIC_LOAD_UMAX_I64:
1542 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1594 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1595 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1623 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1628 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1640 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1641 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1679 case Mips::ATOMIC_LOAD_NAND_I8:
1680 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1682 case Mips::ATOMIC_LOAD_NAND_I16:
1683 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1685 case Mips::ATOMIC_SWAP_I8:
1686 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1688 case Mips::ATOMIC_SWAP_I16:
1689 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1691 case Mips::ATOMIC_LOAD_ADD_I8:
1692 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1694 case Mips::ATOMIC_LOAD_ADD_I16:
1695 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1697 case Mips::ATOMIC_LOAD_SUB_I8:
1698 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1700 case Mips::ATOMIC_LOAD_SUB_I16:
1701 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1703 case Mips::ATOMIC_LOAD_AND_I8:
1704 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1706 case Mips::ATOMIC_LOAD_AND_I16:
1707 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1709 case Mips::ATOMIC_LOAD_OR_I8:
1710 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1712 case Mips::ATOMIC_LOAD_OR_I16:
1713 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1715 case Mips::ATOMIC_LOAD_XOR_I8:
1716 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1718 case Mips::ATOMIC_LOAD_XOR_I16:
1719 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1721 case Mips::ATOMIC_LOAD_MIN_I8:
1722 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1725 case Mips::ATOMIC_LOAD_MIN_I16:
1726 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1729 case Mips::ATOMIC_LOAD_MAX_I8:
1730 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1733 case Mips::ATOMIC_LOAD_MAX_I16:
1734 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1737 case Mips::ATOMIC_LOAD_UMIN_I8:
1738 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1741 case Mips::ATOMIC_LOAD_UMIN_I16:
1742 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1745 case Mips::ATOMIC_LOAD_UMAX_I8:
1746 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1749 case Mips::ATOMIC_LOAD_UMAX_I16:
1750 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1785 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1786 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1788 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1791 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1793 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1795 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1796 .addReg(Mips::ZERO).addImm(MaskImm);
1797 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1799 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1800 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1841 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1842 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1845 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1853 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1854 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1855 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1873 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1874 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1875 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1924 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1925 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1926 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1968 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1970 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1972 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1973 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1975 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1978 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1980 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1982 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1983 .addReg(Mips::ZERO).addImm(MaskImm);
1984 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1986 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1987 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1989 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1991 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1993 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
2033 Mips::CondCode CC =
2034 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2035 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
2037 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
2099 // * Mips linkers don't support creating a page and a full got entry for
2440 DAG.getRegister(Mips::ZERO, MVT::i32),
2473 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2504 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2523 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2549 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2550 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2636 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64
2637 : Mips::PseudoD_SELECT_I,
2836 // Mips O32 ABI rules:
2860 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2864 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2866 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2915 if (Reg == Mips::A2)
2916 State.AllocateReg(Mips::A1);
2918 State.AllocateReg(Mips::A3);
2929 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2934 // available register is Mips::A1 or Mips::A3, shadow it too.
2936 if (Reg == Mips::A1 || Reg == Mips::A3)
2950 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2969 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2977 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3001 assert((Reg == Mips::A0) || (Reg == Mips::A2));
3002 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
3035 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
3037 // used for the function (that is, Mips linker doesn't generate lazy binding
3040 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
3088 case Mips::JALR:
3089 case Mips::JALRPseudo:
3090 case Mips::JALR64:
3091 case Mips::JALR64Pseudo:
3092 case Mips::JALR16_MM:
3093 case Mips::JALRC16_MMR6:
3094 case Mips::TAILCALLREG:
3095 case Mips::TAILCALLREG64:
3096 case Mips::TAILCALLR6REG:
3097 case Mips::TAILCALL64R6REG:
3098 case Mips::TAILCALLREG_MM:
3099 case Mips::TAILCALLREG_MMR6: {
3244 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3857 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3874 // Standard return on Mips is a "jr $ra"
3879 // Mips Inline Assembly Support
3886 // Mips specific constraints
4021 Mips::HI32RegClassID : Mips::LO32RegClassID);
4031 .Case("$msair", Mips::MSAIR)
4032 .Case("$msacsr", Mips::MSACSR)
4033 .Case("$msaaccess", Mips::MSAAccess)
4034 .Case("$msasave", Mips::MSASave)
4035 .Case("$msamodify", Mips::MSAModify)
4036 .Case("$msarequest", Mips::MSARequest)
4037 .Case("$msamap", Mips::MSAMap)
4038 .Case("$msaunmap", Mips::MSAUnmap)
4044 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
4059 if (RC == &Mips::AFGR64RegClass) {
4064 RC = TRI->getRegClass(Mips::FCCRegClassID);
4090 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4091 return std::make_pair(0U, &Mips::GPR32RegClass);
4094 return std::make_pair(0U, &Mips::GPR32RegClass);
4096 return std::make_pair(0U, &Mips::GPR64RegClass);
4101 return std::make_pair(0U, &Mips::MSA128BRegClass);
4103 return std::make_pair(0U, &Mips::MSA128HRegClass);
4105 return std::make_pair(0U, &Mips::MSA128WRegClass);
4107 return std::make_pair(0U, &Mips::MSA128DRegClass);
4109 return std::make_pair(0U, &Mips::FGR32RegClass);
4112 return std::make_pair(0U, &Mips::FGR64RegClass);
4113 return std::make_pair(0U, &Mips::AFGR64RegClass);
4118 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
4120 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4126 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
4127 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4267 // The Mips target isn't yet aware of offsets.
4594 .addReg(Mips::ZERO)
4611 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4663 BuildMI(BB, DL, TII->get(Mips::BNE))
4665 .addReg(Mips::ZERO)
4682 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4687 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4707 .Case("$28", Mips::GP_64)
4713 .Case("$28", Mips::GP)