Searched refs:ADD (Results 76 - 100 of 130) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp615 Op->Mem.AluOp = LPAC::ADD;
886 unsigned AluOp = LPAC::ADD;
932 Lanai::R0, std::move(Op), LPAC::ADD));
/freebsd-11-stable/contrib/byacc/test/yacc/
H A Dquote_calc2.tab.c150 #define ADD 258 macro
272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
284 "expr : expr \"ADD\" expr",
H A Dquote_calc.tab.c150 #define ADD 258 macro
272 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp138 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
167 // Emit a normal ADD instruction with the given operands.
168 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1063 setOperationAction(ISD::ADD, MVT::i16, Custom);
1064 setOperationAction(ISD::ADD, MVT::i32, Custom);
1267 setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom);
1416 setOperationAction(ISD::ADD, VT, Custom);
1733 setOperationAction(ISD::ADD, VT, Custom);
1998 setTargetDAGCombine(ISD::ADD);
3263 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getFrameIndex(FI, PtrVT),
3590 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3722 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
4135 Source = DAG.getNode(ISD::ADD, d
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp95 setOperationAction(ISD::ADD, VecTys[i], Legal);
333 setOperationAction(ISD::ADD, Ty, Legal);
819 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
1190 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1227 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
1584 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1590 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1993 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2002 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
2309 Address = DAG.getNode(ISD::ADD, D
[all...]
/freebsd-11-stable/sbin/setkey/
H A Dparse.y97 %token ADD GET DELETE DELETEALL FLUSH DUMP
155 : ADD ipaddropts ipaddr ipaddr protocol_spec spi extension_spec algorithm_spec EOT
/freebsd-11-stable/contrib/llvm-project/lld/ELF/Arch/
H A DPPC64.cpp38 ADD = 266, enumerator in enum:lld::elf::XFormOpcd
486 case ADD:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1449 setTargetDAGCombine(ISD::ADD);
2049 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2248 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2267 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2269 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
3181 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3196 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3207 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3301 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3516 SDValue Result = DAG.getNode(ISD::ADD, d
[all...]
H A DARMISelDAGToDAG.cpp381 if (N->getOpcode() != ISD::ADD)
632 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
705 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
706 // ISD::OR that is equivalent to an ISD::ADD.
711 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
1078 if (N.getOpcode() != ISD::ADD)
1090 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1121 if (N.getOpcode() == ISD::ADD) {
1246 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1300 if (N.getOpcode() != ISD::ADD
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp604 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2368 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2458 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2754 SDValue Offset = DAG.getNode(ISD::ADD, dl,
2762 Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
3265 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3271 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3272 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3449 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3556 SDValue Addr = DAG.getNode(ISD::ADD, d
[all...]
H A DSelectionDAGBuilder.h694 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
H A DSelectionDAGDumper.cpp225 case ISD::ADD: return "add";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp355 setOperationAction(ISD::ADD, VT, Legal);
1400 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
1418 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1550 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1574 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
3007 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
3144 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
3173 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
3339 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
3397 NeededSpace = DAG.getNode(ISD::ADD, D
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp86 unsigned Opc = RISCV::ADD;
/freebsd-11-stable/crypto/openssl/crypto/sha/asm/
H A Dsha512-ia64.pl78 $ADD="add";
92 $ADD="padd4";
/freebsd-11-stable/sys/dev/an/
H A Dif_an.c768 #define ADD(s, o) ifmedia_add(&sc->an_ifmedia, \ macro
770 ADD(IFM_AUTO, 0);
771 ADD(IFM_AUTO, IFM_IEEE80211_ADHOC);
779 ADD(mword, 0);
780 ADD(mword, IFM_IEEE80211_ADHOC);
785 #undef ADD macro
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp754 // We are selecting i64 ADD here instead of custom lower it during
976 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
1006 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE;
1374 if (N0.getOpcode() == ISD::ADD) {
2826 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
2842 if (Addr.getOpcode() == ISD::ADD
H A DR600ISelLowering.cpp176 // ADD, SUB overflow.
485 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
1168 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1398 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1816 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
H A DAMDGPUTargetTransformInfo.cpp377 case ISD::ADD:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp858 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
1286 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1353 if (Op->getOpcode() != ISD::ADD)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp445 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
729 /// need to create a real ADD instruction from it anyway and there's no point in
731 /// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
956 if (N.getOpcode() != ISD::ADD)
1026 // Check if the given immediate is preferred by ADD. If an immediate can be
1027 // encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
1030 // Constant in [0x0, 0xfff] can be encoded in ADD.
1033 // Check if it can be encoded in an "ADD LSL #12".
1035 // As a single MOVZ is faster than a "ADD o
[all...]
/freebsd-11-stable/contrib/byacc/test/btyacc/
H A Dbtyacc_demo.tab.c136 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF }; enumerator in enum:Operator
2013 { yyval.expr = build_expr(yystack.l_mark[-3].expr, ADD, yystack.l_mark[0].expr); }
/freebsd-11-stable/lib/libc/resolv/
H A Dres_mkupdate.c183 case ADD:
/freebsd-11-stable/sys/netipsec/
H A Dkey_debug.c95 SADB_NAME(ADD);

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