| /broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/ |
| H A D | ui_hspcmds.c | 126 #define WRITECSR(x,y) phys_write64(x,y) macro
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| H A D | ui_swtrace.c | 79 #define WRITECSR(x,y) phys_write64(x,y) macro
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| H A D | cfe_dmtest.c | 1424 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) macro
1433 #undef WRITECSR macro
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| H A D | ui_pmcmds.c | 85 #define WRITECSR(x,y) phys_write64(x,y) macro
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| /broadcom-cfe-1.4.2/cfe/dev/ |
| H A D | dev_ns16550.c | 65 #define WRITECSR WRITEREG macro
76 #undef WRITECSR macro
77 #define WRITECSR(sc,r,v) \ macro
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| H A D | dev_ds1743.c | 87 #define WRITECSR(p,v) phys_write8((p)^3,(v)) macro
90 #define WRITECSR(p,v) phys_write8((p),(v)) macro
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| H A D | dev_ds17887clock.c | 112 #define WRITECSR(p,v) phys_write8((p),(v)) macro
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| H A D | dev_m48txx.c | 95 #define WRITECSR(p,v) phys_write8((p)^0x3,(v)) macro
98 #define WRITECSR(p,v) phys_write8((p),(v)) macro
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| H A D | dev_bcm4401.c | 287 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val))) macro
291 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro
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| H A D | dev_dp83815.c | 270 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro
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| H A D | dev_i82559.c | 307 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro
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| H A D | dev_aic6915.c | 410 #define WRITECSR(sc,csr,val) (phys_write32((sc)->regbase+(csr), (val))) macro
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| H A D | dev_bcm5700.c | 471 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->regbase + (csr), (val))) macro
505 #define WRITECSR(sc,csr,val) (l_phys_write32((sc)->regbase + (csr), (val))) macro
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| H A D | dev_tulip.c | 311 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
| H A D | bcm1480_hsp_utils.c | 128 #define WRITECSR(x,y) phys_write64(x,y) macro
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| H A D | bcm1480_draminit.c | 285 #define WRITECSR(csr,val) sbwritecsr(csr,val) macro
290 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) macro
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| /broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/ |
| H A D | sb_pci_machdep.c | 105 #define WRITECSR(x,v) \ macro
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| H A D | sb_utils.c | 207 #define WRITECSR(x,v) \ macro
347 #define WRITECSR(x,v) \ macro
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| H A D | dev_sb_mac.c | 352 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | sb1250_draminit.c | 263 #define WRITECSR(csr,val) sbwritecsr(csr,val) macro
269 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) macro
[all...] |
| /broadcom-cfe-1.4.2/cfe/arch/ppc/chipset/mpc824x/src/ |
| H A D | dev_tulip.c | 372 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val))) macro
376 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro
[all...] |