1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * Broadcom Silicon Backplane MAC Driver File: dev_sb_mac.c 5 * 6 * Author: Ed Satterthwaite 7 * 8 ********************************************************************* 9 * 10 * Copyright 2001,2002,2003 11 * Broadcom Corporation. All rights reserved. 12 * 13 * This software is furnished under license and may be used and 14 * copied only in accordance with the following terms and 15 * conditions. Subject to these conditions, you may download, 16 * copy, install, use, modify and distribute modified or unmodified 17 * copies of this software in source and/or binary form. No title 18 * or ownership is transferred hereby. 19 * 20 * 1) Any source code used, modified or distributed must reproduce 21 * and retain this copyright notice and list of conditions 22 * as they appear in the source file. 23 * 24 * 2) No right is granted to use any trade name, trademark, or 25 * logo of Broadcom Corporation. The "Broadcom Corporation" 26 * name may not be used to endorse or promote products derived 27 * from this software without the prior written permission of 28 * Broadcom Corporation. 29 * 30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 42 * THE POSSIBILITY OF SUCH DAMAGE. 43 ********************************************************************* */ 44 45#include "cfe.h" 46#define blockcopy memcpy 47#include "cfe_irq.h" 48 49#include "lib_try.h" 50#include "lib_physio.h" 51 52#include "net_enet.h" 53 54#include "pcivar.h" 55#include "pcireg.h" 56 57#ifdef BCM47XX 58 59/* No bcm47xx SOC tested so far has been able to communicate with a 60 bcm4401 via PCI. In early revisions of the bcm4401, accesses to 61 CSRs in the DMA engine, EMAC, MIB and configuration regions (except 62 SBIDHIGH) appear to complete correctly, but all the others fault 63 with a bus error. In a B0 revision bcm4401, all such accesses give 64 bus errors. */ 65#undef CFG_PCI 66#define CFG_PCI 0 67 68#include "sb_bp.h" 69#include "sb_pci.h" 70#include "sb_mac.h" 71 72/* MII extensions shared by several Broadcom PHYs */ 73#define R_INTERRUPT 0x1A 74 75#define M_PHYINT_IS _DD_MAKEMASK1(0) /* InterruptStatus */ 76#define M_PHYINT_LC _DD_MAKEMASK1(1) /* LinkChangeInt */ 77#define M_PHYINT_SP _DD_MAKEMASK1(2) /* SpeedChangeInt */ 78#define M_PHYINT_DC _DD_MAKEMASK1(3) /* DuplexChangeInt */ 79#define M_PHYINT_MI _DD_MAKEMASK1(8) /* MasterIntMask */ 80#define M_PHYINT_LI _DD_MAKEMASK1(9) /* LinkIntMask */ 81#define M_PHYINT_SI _DD_MAKEMASK1(10) /* SpeedIntMask */ 82#define M_PHYINT_FD _DD_MAKEMASK1(11) /* FullDuplexIntMask */ 83#define M_PHYINT_IE _DD_MAKEMASK1(14) /* InterruptEnable */ 84 85#else 86#include "bcm4401.h" 87#endif 88#include "mii.h" 89 90/* 91 This is a driver for the Broadcom 4401 10/100 MAC with integrated 92 PHY as well as for the 10/100 MAC cores used in OCP-based SOCs. 93 94 This driver takes advantage of DMA coherence in systems that 95 support it (e.g., SB1250). For systems without coherent DMA (e.g, 96 BCM47xx SOCs), packet buffer memory is explicitly flushed, and 97 descriptors are referenced only in uncacheable modes. 98 99 The BCM4401 does not have a big-endian mode for DMA. On the 100 SB1250, this driver therefore uses "preserve byte lanes" addresses 101 for all DMA accesses that cross the ZBbus-PCI bridge. Descriptors 102 and packets headers as seen by the CPU must be byte-swapped for the 103 DMA engine. For hardware without such a mode, only little-endian 104 operation is supported. 105*/ 106 107#define K_PCI_ID_BCM4401 0x4401 /* Rev A0, A1 */ 108#define K_PCI_ID_BCM4401_B 0x170C /* Rev B0 and later */ 109#define K_PCI_ID_BCM4402 0x4402 /* used by HND */ 110 111#ifndef B44_DEBUG 112#define B44_DEBUG 0 113#endif 114 115#if ((ENDIAN_BIG + ENDIAN_LITTLE) != 1) 116#error "dev_sb_mac: system endian not set" 117#endif 118 119/* Set IPOLL to drive processing through the pseudo-interrupt 120 dispatcher. Set XPOLL to drive processing by an external polling 121 agent. Setting both is ok. */ 122 123#ifndef IPOLL 124#define IPOLL 0 125#endif 126#ifndef XPOLL 127#define XPOLL 1 128#endif 129 130#define CACHE_ALIGN 32 131#define PAGE_ALIGN 4096 132#define ALIGN(n,align) (((n)+((align)-1)) & ~((align)-1)) 133 134#define MIN_ETHER_PACK (ENET_MIN_PKT+ENET_CRC_SIZE) /* size of min packet */ 135#define MAX_ETHER_PACK (ENET_MAX_PKT+ENET_CRC_SIZE) /* size of max packet */ 136 137/* Packet buffers. For the BCM4401, an rx packet is preceded by 138 status information written into the rx buffer. The packet itself 139 begins at a programmable offset (PKTBUF_RX_OFFSET), which must be 140 at least 28. The DMA engine allows arbitrary buffer and packet 141 alignment, but aligning to a cache line boundary can reduce lines 142 touched on the copies. Also, header and packet must be 32-bit 143 aligned for 47xx byte swapping on RAM access to work correctly. */ 144 145#define PKTBUF_RX_OFFSET CACHE_ALIGN 146#define ETH_PKTBUF_LEN ALIGN(PKTBUF_RX_OFFSET+MAX_ETHER_PACK, CACHE_ALIGN) 147#define ETH_PKTPOOL_SIZE 32 148 149typedef struct eth_pkt_s { 150 queue_t next; /* 8 */ 151 uint8_t *buffer; /* 4 */ 152 uint32_t flags; /* 4 */ 153 int32_t length; /* 4 */ 154 uint32_t unused[3]; /* 12 */ 155 uint8_t data[ETH_PKTBUF_LEN]; 156} eth_pkt_t; 157 158/* Work around for apparent alignment problem with DMA (still needed?) */ 159/* #define ETH_PKTBUF_SIZE ALIGN(sizeof(eth_pkt_t), CACHE_ALIGN) */ 160#define ETH_PKTBUF_SIZE 2048 161#define ETH_PKTBUF_OFFSET (offsetof(eth_pkt_t, data)) 162 163#define ETH_PKT_BASE(data) ((eth_pkt_t *)((data) - ETH_PKTBUF_OFFSET)) 164 165static void 166show_packet(char c, eth_pkt_t *pkt, int offset) 167{ 168 int i; 169 int n = (pkt->length < 32 ? pkt->length : 32); 170 171 xprintf("%c[%4d]:", c, pkt->length); 172 for (i = 0; i < n; i++) { 173 if (i % 4 == 0) 174 xprintf(" "); 175 xprintf("%02x", pkt->buffer[offset+i]); 176 } 177 xprintf("\n"); 178} 179 180 181/* Descriptor structures. The descriptor ring must begin on a 4K 182 boundary and cannot exceed 512 entries. Note that descriptors are 183 referenced by the DMA engine using match-bytes addresses. */ 184 185typedef struct rx_dscr { 186 uint32_t rxd_cmdsts; 187 pci_addr_t rxd_bufptr; 188} rx_dscr; 189 190typedef struct tx_dscr { 191 uint32_t txd_cmdsts; 192 pci_addr_t txd_bufptr; 193} tx_dscr; 194 195 196/* Driver data structures */ 197 198typedef enum { 199 eth_state_uninit, 200 eth_state_off, 201 eth_state_on, 202 eth_state_broken 203} eth_state_t; 204 205typedef struct bcm4401_softc { 206 uint32_t membase; 207 uint8_t irq; /* interrupt mapping (used if IPOLL) */ 208 pcitag_t tag; /* tag for configuration registers */ 209 210 /* functions for mapping between memory and dma addresses */ 211 uint32_t (*phys_to_dma)(uint32_t); 212 uint32_t (*dma_to_phys)(uint32_t); 213 214 uint8_t hwaddr[ENET_ADDR_LEN]; 215 uint16_t device; /* chip device code */ 216 uint8_t revision; /* chip revision and step */ 217 218 eth_state_t state; /* current state */ 219 uint32_t intmask; /* interrupt mask */ 220 221 /* These fields are set before calling bcm4401_hwinit */ 222 int linkspeed; /* encodings from cfe_ioctl */ 223 int loopback; 224 225 /* Packet free list */ 226 queue_t freelist; 227 uint8_t *pktpool; 228 queue_t rxqueue; 229 230 /* The descriptor tables */ 231 uint8_t *rxdscrmem; /* receive descriptors */ 232 uint8_t *txdscrmem; /* transmit descriptors */ 233 234 /* These fields keep track of where we are in tx/rx processing */ 235 volatile rx_dscr *rxdscr_start; /* beginning of ring */ 236 volatile rx_dscr *rxdscr_end; /* end of ring */ 237 volatile rx_dscr *rxdscr_remove; /* oldest one owned by DMA */ 238 volatile rx_dscr *rxdscr_add; /* next place to put a buffer */ 239 int rxdscr_onring; 240 241 volatile tx_dscr *txdscr_start; /* beginning of ring */ 242 volatile tx_dscr *txdscr_end; /* end of ring */ 243 volatile tx_dscr *txdscr_remove; /* oldest one owned by DMA */ 244 volatile tx_dscr *txdscr_add; /* next place to put a buffer */ 245 246 cfe_devctx_t *devctx; 247 248 int phy_addr; 249 uint32_t phy_vendor; 250 uint16_t phy_device; 251 int phy_interrupt; /* bcm5221-like MII interrupt reg */ 252 int slow_poll; 253 254 /* Statistics */ 255 uint32_t inpkts; 256 uint32_t outpkts; 257 uint32_t interrupts; 258 uint32_t rx_interrupts; 259 uint32_t tx_interrupts; 260} bcm4401_softc; 261 262 263/* Entry to and exit from critical sections (currently relative to 264 interrupts only, not SMP) */ 265 266#if CFG_INTERRUPTS 267#define CS_ENTER(sc) cfe_disable_irq(sc->irq) 268#define CS_EXIT(sc) cfe_enable_irq(sc->irq) 269#else 270#define CS_ENTER(sc) ((void)0) 271#define CS_EXIT(sc) ((void)0) 272#endif 273 274 275/* Chip parameterization */ 276 277#define GP_TIMER_HZ 62500000 278 279 280/* Driver parameterization */ 281 282#define MAXRXDSCR 32 283#define MAXTXDSCR 32 284#define MINRXRING 8 285 286 287/* Prototypes */ 288 289#if CFG_PCI 290static void bcm4401_ether_probe(cfe_driver_t *drv, 291 unsigned long probe_a, unsigned long probe_b, 292 void *probe_ptr); 293#endif 294static void sb_ether_probe(cfe_driver_t *drv, 295 unsigned long probe_a, unsigned long probe_b, 296 void *probe_ptr); 297 298 299/* Address mapping macros. Accesses in which the BCM4401 is the 300 target are to registers and use match bits mode. Accesses in which 301 it is the initiator always assume little-endian responses and must 302 use match bytes, per the macros below. For big-endian hosts, the 303 DMA status word must be byte-swapped. */ 304 305/* Note that PTR_TO_PHYS only works with 32-bit addresses, but then 306 so does the BCM4401. */ 307#define PTR_TO_PHYS(x) (PHYSADDR((uintptr_t)(x))) 308#define PHYS_TO_PTR(a) ((uint8_t *)KERNADDR(a)) 309 310/* The DMA engine does not have a big-endian option for descriptors 311 and data. All its accesses through the host bridge use match bytes 312 mode. The CPU must construct descriptors and headers accordingly. 313 PIO accesses to the configuration and host interface registers use 314 match bits. */ 315 316#if CFG_PCI 317#if ENDIAN_BIG && defined(BCM47XX) 318/* XXX Not clear that hardware really supports this combination. */ 319static uint32_t phys_to_pci(uint32_t a) {return a + 0x50000000;} 320static uint32_t pci_to_phys(uint32_t a) {return a - 0x50000000;} 321#else 322static uint32_t phys_to_pci(uint32_t a) {return a + 0x40000000;} 323static uint32_t pci_to_phys(uint32_t a) {return a - 0x40000000;} 324#endif 325#endif /* CFG_PCI */ 326 327#if ENDIAN_BIG && defined(BCM47XX) 328/* XXX This needs cleanup/abstraction. The 47xx SOCs efectively have 329 an endian bit that is used to swap bytes in SDRAM accesses 330 (only). */ 331static uint32_t phys_to_sb(uint32_t a) {return a + 0x10000000;} 332static uint32_t sb_to_phys(uint32_t a) {return a - 0x10000000;} 333#else 334static uint32_t phys_to_sb(uint32_t a) {return a;} 335static uint32_t sb_to_phys(uint32_t a) {return a;} 336#endif 337 338#undef PHYS_TO_PCI 339#undef PCI_TO_PHYS 340 341#define PCI_TO_PTR(sc,a) (PHYS_TO_PTR((*(sc)->dma_to_phys)(a))) 342#define PTR_TO_PCI(sc,x) ((*(sc)->phys_to_dma)(PTR_TO_PHYS(x))) 343 344#if ENDIAN_BIG 345#define READCSR2(sc,csr) (phys_read16((sc)->membase + ((csr)^2))) 346#define WRITECSR2(sc,csr,val) (phys_write16((sc)->membase + ((csr)^2), (val))) 347#else 348#define READCSR2(sc,csr) (phys_read16((sc)->membase + (csr))) 349#define WRITECSR2(sc,csr,val) (phys_write16((sc)->membase + (csr), (val))) 350#endif 351#define READCSR(sc,csr) (phys_read32((sc)->membase + (csr))) 352#define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) 353 354/* Byte swap utilities: host to/from little-endian */ 355 356#if ENDIAN_BIG 357#define HTOL4(x) \ 358 ((((x) & 0x00FF) << 24) | \ 359 (((x) & 0xFF00) << 8) | \ 360 (((x) >> 8) & 0xFF00) | \ 361 (((x) >> 24) & 0x00FF)) 362 363static uint32_t 364htol4(uint32_t x) 365{ 366 uint32_t t; 367 368 t = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); 369 return (t >> 16) | ((t & 0xFFFF) << 16); 370} 371#else 372#define HTOL4(x) (x) 373#define htol4(x) (x) 374#endif 375 376#define ltoh4 htol4 /* self-inverse */ 377 378 379/* Packet management */ 380 381static eth_pkt_t * 382eth_alloc_pkt(bcm4401_softc *sc) 383{ 384 eth_pkt_t *pkt; 385 386 CS_ENTER(sc); 387 pkt = (eth_pkt_t *) q_deqnext(&sc->freelist); 388 CS_EXIT(sc); 389 390 if (!pkt) return NULL; 391 392 pkt->buffer = pkt->data; 393 pkt->length = ETH_PKTBUF_LEN; 394 pkt->flags = 0; 395 396 return pkt; 397} 398 399static void 400eth_free_pkt(bcm4401_softc *sc, eth_pkt_t *pkt) 401{ 402 CS_ENTER(sc); 403 q_enqueue(&sc->freelist, &pkt->next); 404 CS_EXIT(sc); 405} 406 407 408static void 409eth_initfreelist(bcm4401_softc *sc) 410{ 411 int idx; 412 uint8_t *ptr; 413 eth_pkt_t *pkt; 414 415 q_init(&sc->freelist); 416 417 ptr = sc->pktpool; 418 for (idx = 0; idx < ETH_PKTPOOL_SIZE; idx++) { 419 pkt = (eth_pkt_t *) ptr; 420 eth_free_pkt(sc, pkt); 421 ptr += ETH_PKTBUF_SIZE; 422 } 423} 424 425 426/* Utilities */ 427 428static const char * 429bcm4401_devname(bcm4401_softc *sc) 430{ 431 return (sc->devctx != NULL ? cfe_device_name(sc->devctx) : "eth?"); 432} 433 434 435/* Descriptor ring management */ 436 437static int 438bcm4401_add_rcvbuf(bcm4401_softc *sc, eth_pkt_t *pkt) 439{ 440 volatile rx_dscr *rxd; 441 volatile rx_dscr *nextrxd; 442 443 rxd = sc->rxdscr_add; 444 nextrxd = rxd+1; 445 if (nextrxd == sc->rxdscr_end) { 446 nextrxd = sc->rxdscr_start; 447 } 448 449 /* If the next one is the same as our remove pointer, the ring is 450 considered full. */ 451 if (nextrxd == sc->rxdscr_remove) return -1; 452 453 /* Only the buffer pointer needs updating. */ 454 rxd->rxd_bufptr = htol4(V_DSCR1_DB(PTR_TO_PCI(sc, pkt->buffer))); 455 456 sc->rxdscr_add = nextrxd; 457 458 mips_wbflush(); 459 WRITECSR(sc, R_RCV_PTR, V_RPTR_LD(PTR_TO_PCI(sc, nextrxd) & 0xFFF)); 460 461 return 0; 462} 463 464static void 465bcm4401_fillrxring(bcm4401_softc *sc) 466{ 467 eth_pkt_t *pkt; 468 469 CS_ENTER(sc); 470 while (1) { 471 if (sc->rxdscr_onring >= MINRXRING) { 472 CS_EXIT(sc); 473 break; 474 } 475 CS_EXIT(sc); 476 pkt = eth_alloc_pkt(sc); 477 if (pkt == NULL) { 478 /* could not allocate a buffer */ 479 break; 480 } 481 if (bcm4401_add_rcvbuf(sc, pkt) != 0) { 482 /* could not add buffer to ring */ 483 eth_free_pkt(sc, pkt); 484 break; 485 } 486 CS_ENTER(sc); 487 sc->rxdscr_onring++; 488 } 489} 490 491 492/* Receive buffer processing. */ 493 494static void 495bcm4401_rx_callback(bcm4401_softc *sc, eth_pkt_t *pkt) 496{ 497 if (B44_DEBUG) show_packet('>', pkt, PKTBUF_RX_OFFSET); 498 499 CS_ENTER(sc); 500 q_enqueue(&sc->rxqueue, &pkt->next); 501 CS_EXIT(sc); 502 sc->inpkts++; 503} 504 505static void 506bcm4401_procrxring(bcm4401_softc *sc) 507{ 508 uint32_t rxstat; 509 volatile rx_dscr *rxcurr; 510 volatile rx_dscr *rxd; 511 eth_pkt_t *pkt; 512 eth_pkt_t *newpkt; 513 uint32_t hdr0; 514 515 rxstat = READCSR(sc, R_RCV_STATUS); 516 rxcurr = (volatile rx_dscr *) 517 ((uint8_t *)sc->rxdscr_start + G_RSTAT_CD(rxstat)); 518 519 for (;;) { 520 rxd = sc->rxdscr_remove; 521 522 if (rxd == rxcurr) { 523 /* all packets processed */ 524 break; 525 } 526 527 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, (ltoh4(rxd->rxd_bufptr)))); 528 529 CACHE_DMA_INVAL(pkt->buffer, PKTBUF_RX_OFFSET); 530 hdr0 = ltoh4(*(uint32_t *)(pkt->buffer)); 531 532 /* Drop error packets. */ 533 /* The header word apparently reports this (undocumented for 4401, 534 but documented in the 4710 manual. */ 535 if (hdr0 & M_RCVHDR0_ERRORS) { 536 xprintf("BCM4401: rx error %08X\n", hdr0); 537 newpkt = pkt; /* recycle the buffer */ 538 } 539 else { 540 /* Pass up the packet */ 541 pkt->length = G_RCVHDR0_CD(hdr0) - ENET_CRC_SIZE; 542 bcm4401_rx_callback(sc, pkt); 543 /* put a buffer back on the ring to replace this one */ 544 newpkt = eth_alloc_pkt(sc); 545 } 546 547 /* update the pointer, accounting for buffer wrap. */ 548 rxd++; 549 if (rxd == sc->rxdscr_end) 550 rxd = sc->rxdscr_start; 551 sc->rxdscr_remove = rxd; 552 553 if (newpkt) { 554 /* The ring must have space now. */ 555 bcm4401_add_rcvbuf(sc, newpkt); 556 } 557 else { 558 CS_ENTER(sc); 559 sc->rxdscr_onring--; 560 CS_EXIT(sc); 561 } 562 } 563 564 /* XXX Check for error stops. */ 565} 566 567 568/* Transmit ring processing. */ 569 570static int 571bcm4401_add_txbuf(bcm4401_softc *sc, eth_pkt_t *pkt) 572{ 573 volatile tx_dscr *txd; 574 volatile tx_dscr *nexttxd; 575 uint32_t cmdsts; 576 577 txd = sc->txdscr_add; 578 cmdsts = M_DSCR0_SF | M_DSCR0_EF | M_DSCR0_IC; 579 nexttxd = (txd+1); 580 if (nexttxd == sc->txdscr_end) { 581 cmdsts |= M_DSCR0_ET; 582 nexttxd = sc->txdscr_start; 583 } 584 585 /* If the next one is the same as our remove pointer, the ring is 586 considered full. */ 587 if (nexttxd == sc->txdscr_remove) return -1; 588 589 txd->txd_bufptr = htol4(V_DSCR1_DB(PTR_TO_PCI(sc, pkt->buffer))); 590 cmdsts |= V_DSCR0_BC(pkt->length); 591 txd->txd_cmdsts = htol4(cmdsts); 592 593 sc->txdscr_add = nexttxd; 594 595 return 0; 596} 597 598 599static int 600bcm4401_transmit(bcm4401_softc *sc, eth_pkt_t *pkt) 601{ 602 int rv; 603 604 if (B44_DEBUG) show_packet('<', pkt, 0); 605 606 rv = bcm4401_add_txbuf(sc, pkt); 607 if (rv == 0) { 608 mips_wbflush(); 609 WRITECSR(sc, R_XMT_PTR, 610 V_XPTR_LD(PTR_TO_PCI(sc, sc->txdscr_add) & 0xFFF)); 611 } 612 613 sc->outpkts++; 614 return rv; 615} 616 617static void 618bcm4401_proctxring(bcm4401_softc *sc) 619{ 620 uint32_t txstat; 621 volatile tx_dscr *txcurr; 622 volatile tx_dscr *txd; 623 eth_pkt_t *pkt; 624 625 txstat = READCSR(sc, R_XMT_STATUS); 626 txcurr = (volatile tx_dscr *) 627 ((uint8_t *)sc->txdscr_start + G_XSTAT_CD(txstat)); 628 629 for (;;) { 630 txd = sc->txdscr_remove; 631 632 if (txd == txcurr) { 633 /* ring is empty, no buffers to process */ 634 break; 635 } 636 637 /* Just free the packet */ 638 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, ltoh4(txd->txd_bufptr))); 639 eth_free_pkt(sc, pkt); 640 641 /* update the pointer, accounting for buffer wrap. */ 642 txd++; 643 if (txd == sc->txdscr_end) 644 txd = sc->txdscr_start; 645 646 sc->txdscr_remove = txd; 647 } 648 649 /* XXX Check for error halt. */ 650} 651 652 653static void 654bcm4401_initrings(bcm4401_softc *sc) 655{ 656 volatile tx_dscr *txd; 657 volatile rx_dscr *rxd; 658 659 for (txd = sc->txdscr_start; txd != sc->txdscr_end; txd++) { 660 txd->txd_cmdsts = HTOL4(M_DSCR0_SF | M_DSCR0_EF | M_DSCR0_IC); 661 txd->txd_bufptr = 0; 662 } 663 (txd-1)->txd_cmdsts |= HTOL4(M_DSCR0_ET); 664 665 for (rxd = sc->rxdscr_start; rxd != sc->rxdscr_end; rxd++) { 666 rxd->rxd_cmdsts = HTOL4(M_DSCR0_SF | M_DSCR0_EF /* XXX needed? */ 667 | V_DSCR0_BC(ETH_PKTBUF_LEN)); 668 rxd->rxd_bufptr = 0; 669 } 670 (rxd-1)->rxd_cmdsts |= HTOL4(M_DSCR0_ET); 671 672 sc->txdscr_add = sc->txdscr_remove = sc->txdscr_start; 673 sc->rxdscr_add = sc->rxdscr_remove = sc->rxdscr_start; 674 sc->rxdscr_onring = 0; 675 676 /* Precharge the receive ring */ 677 bcm4401_fillrxring(sc); 678} 679 680 681/* Allocate an integral number of cache lines suitable for DMA access. */ 682static uint8_t * 683dma_alloc(size_t size, unsigned int align) 684{ 685 uint8_t *base; 686 size_t len = ALIGN(size, CACHE_ALIGN); 687 688 base = KMALLOC(len, ALIGN(align, CACHE_ALIGN)); 689 if (base != NULL) 690 CACHE_DMA_INVAL(base, len); 691 return base; 692} 693 694static int 695bcm4401_init(bcm4401_softc *sc) 696{ 697 /* Allocate descriptor rings */ 698 sc->rxdscrmem = CACHE_DMA_SHARED(dma_alloc(MAXRXDSCR*sizeof(rx_dscr), PAGE_ALIGN)); 699 sc->txdscrmem = CACHE_DMA_SHARED(dma_alloc(MAXTXDSCR*sizeof(tx_dscr), PAGE_ALIGN)); 700 701 /* Allocate buffer pool (4K aligned to fix apparent DMA alignment bug) */ 702 sc->pktpool = dma_alloc(ETH_PKTPOOL_SIZE*ETH_PKTBUF_SIZE, PAGE_ALIGN); 703 if (sc->pktpool == NULL) { 704 xprintf("%s: No buffer memory available.\n", bcm4401_devname(sc)); 705 return -1; 706 } 707 eth_initfreelist(sc); 708 q_init(&sc->rxqueue); 709 710 /* Fill in pointers to the rings */ 711 sc->rxdscr_start = (volatile rx_dscr *) (sc->rxdscrmem); 712 sc->rxdscr_end = sc->rxdscr_start + MAXRXDSCR; 713 714 sc->txdscr_start = (volatile tx_dscr *) (sc->txdscrmem); 715 sc->txdscr_end = sc->txdscr_start + MAXTXDSCR; 716 717 bcm4401_initrings(sc); 718 719 return 0; 720} 721 722 723static void 724bcm4401_resetrings(bcm4401_softc *sc) 725{ 726 volatile tx_dscr *txd; 727 volatile rx_dscr *rxd; 728 eth_pkt_t *pkt; 729 730 /* Free any pending transmit packets (sent and unsent) */ 731 txd = sc->txdscr_remove; 732 while (txd != sc->txdscr_add) { 733 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, ltoh4(txd->txd_bufptr))); 734 eth_free_pkt(sc, pkt); 735 736 txd++; 737 if (txd == sc->txdscr_end) 738 txd = sc->txdscr_start; 739 } 740 sc->txdscr_remove = txd; 741 742 /* Discard any received packets as well as all free buffers */ 743 rxd = sc->rxdscr_remove; 744 while (rxd != sc->rxdscr_add) { 745 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, ltoh4(rxd->rxd_bufptr))); 746 eth_free_pkt(sc, pkt); 747 748 rxd++; 749 if (rxd == sc->rxdscr_end) 750 rxd = sc->rxdscr_start; 751 CS_ENTER(sc); 752 sc->rxdscr_onring--; 753 CS_EXIT(sc); 754 } 755 sc->rxdscr_remove = rxd; 756 757 /* Reestablish the initial state. */ 758 bcm4401_initrings(sc); 759} 760 761 762/* CRC */ 763 764 765/* EEPROM access */ 766 767 768/* MII access */ 769 770static void 771mii_enable(bcm4401_softc *sc) 772{ 773 uint32_t devctl, enetctl; 774 775 devctl = READCSR(sc, R_DEV_CONTROL); 776 if ((devctl & M_DVCTL_IP) != 0) { 777 WRITECSR(sc, R_MII_STATUS_CONTROL, M_MIICTL_PR | V_MIICTL_MD(0xD)); 778 devctl = READCSR(sc, R_DEV_CONTROL); 779 if ((devctl & M_DVCTL_ER) != 0) { 780 devctl &= ~M_DVCTL_ER; 781 WRITECSR(sc, R_DEV_CONTROL, devctl); 782 cfe_usleep(100); 783 } 784 } 785 else { 786 WRITECSR(sc, R_MII_STATUS_CONTROL, M_MIICTL_PR | V_MIICTL_MD(0x9)); 787 enetctl = READCSR(sc, R_ENET_CONTROL); 788 enetctl |= M_ECTL_EP; 789 WRITECSR(sc, R_ENET_CONTROL, enetctl); 790 } 791} 792 793static uint16_t 794mii_read(bcm4401_softc *sc, int reg) 795{ 796 uint32_t cmd, status; 797 uint32_t data; 798 int timeout; 799 800 WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI); 801 (void)READCSR(sc, R_ENET_INT_STATUS); 802 803 cmd = (V_MIIDATA_OP(K_MII_OP_READ) | V_MIIDATA_TA(K_TA_VALID) | 804 V_MIIDATA_RA(reg) | V_MIIDATA_PM(sc->phy_addr)); 805 WRITECSR(sc, R_MII_DATA, cmd | V_MIIDATA_SB(K_MII_START)); 806 807 for (timeout = 1000; timeout > 0; timeout -= 100) { 808 status = READCSR(sc, R_ENET_INT_STATUS); 809 if ((status & M_EINT_MI) != 0) 810 break; 811 cfe_usleep(100); 812 } 813 814 if (timeout <= 0) 815 return 0xFFFF; 816 817 data = G_MIIDATA_D(READCSR(sc, R_MII_DATA)); 818 return data; 819} 820 821static void 822mii_write(bcm4401_softc *sc, int reg, uint16_t value) 823{ 824 uint32_t cmd, status; 825 int timeout; 826 827 WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI); 828 (void)READCSR(sc, R_ENET_INT_STATUS); 829 830 cmd = (V_MIIDATA_OP(K_MII_OP_WRITE) | V_MIIDATA_TA(0x2) | 831 V_MIIDATA_RA(reg) | V_MIIDATA_PM(sc->phy_addr) | 832 V_MIIDATA_D(value)); 833 WRITECSR(sc, R_MII_DATA, cmd | V_MIIDATA_SB(K_MII_START)); 834 835 for (timeout = 1000; timeout > 0; timeout -= 100) { 836 status = READCSR(sc, R_ENET_INT_STATUS); 837 if ((status & M_EINT_MI) != 0) 838 break; 839 cfe_usleep(100); 840 } 841} 842 843/* For an integrated PHY (bcm4401), unimplemented PHY addresses return 844 id's of 0. For (some?) external PHYs, unimplmented addresses 845 appear to return 0x1FFF or 0x3FFF for id1 but reliably (?) return 846 0xFFFF for id2. */ 847static int 848mii_probe(bcm4401_softc *sc) 849{ 850 int i; 851 uint16_t id1, id2; 852 int prev = sc->phy_addr; 853 854 for (i = 0; i < 32; i++) { 855 sc->phy_addr = i; 856 id1 = mii_read(sc, R_PHYIDR1); 857 id2 = mii_read(sc, R_PHYIDR2); 858 if (id2 != 0x0000 && id2 != 0xFFFF) { 859 sc->phy_vendor = ((uint32_t)id1 << 6) | ((id2 >> 10) & 0x3F); 860 sc->phy_device = (id2 >> 4) & 0x3F; 861 xprintf("phy %d, vendor %06x part %02x\n", 862 i, sc->phy_vendor, sc->phy_device); 863 864#if 0 865 return 0; 866#endif 867 } 868 } 869#if 0 870 xprintf("mii_probe: No PHY found\n"); 871#else 872 xprintf("mii_probe: Using PHY %d\n", prev); 873#endif 874 sc->phy_addr = prev; /* Expected addr (if any) */ 875 return -1; 876} 877 878#if B44_DEBUG 879static void 880mii_dump(bcm4401_softc *sc, const char *label) 881{ 882 int i; 883 uint16_t r; 884 uint32_t idr, part; 885 886 xprintf("%s, MII:\n", label); 887 idr = part = 0; 888 889 /* Common registers */ 890 for (i = 0x0; i <= 0x8; ++i) { 891 r = mii_read(sc, i); 892 xprintf(" REG%02X: %04X", i, r); 893 if (i % 4 == 3) xprintf("\n"); 894 if (i == MII_PHYIDR1) { 895 idr |= r << 6; 896 } 897 else if (i == MII_PHYIDR2) { 898 idr |= (r >> 10) & 0x3F; 899 part = (r >> 4) & 0x3F; 900 } 901 } 902 xprintf("\nIDR %06x, PART %02x\n", idr, part); 903 904 /* Broadcom extensions */ 905 for (i = 0x10; i <= 0x14; ++i) { 906 r = mii_read(sc, i); 907 xprintf(" REG%02X: %04X", i, r); 908 if (i % 4 == 3) xprintf("\n"); 909 } 910 xprintf("\n"); 911 912 /* Broadcom extensions (52xx family) */ 913 for (i = 0x18; i <= 0x1F; i++) { 914 r = mii_read(sc, i); 915 xprintf(" REG%02X: %04X", i, r); 916 if (i % 4 == 3) xprintf("\n"); 917 } 918 xprintf("\n"); 919} 920#else 921#define mii_dump(sc,label) 922#endif 923 924static void 925mii_set_speed(bcm4401_softc *sc, int speed) 926{ 927 /* NYI */ 928} 929 930static uint16_t 931mii_interrupt(bcm4401_softc *sc) 932{ 933 /* The read also clears any interrupt bits. */ 934 return mii_read(sc, R_INTERRUPT); 935} 936 937 938static void 939mii_autonegotiate(bcm4401_softc *sc) 940{ 941 uint16_t control, status, remote; 942 unsigned int timeout; 943 int linkspeed; 944 945 linkspeed = ETHER_SPEED_UNKNOWN; 946 947 xprintf("%s: Link speed: ", bcm4401_devname(sc)); 948 949 if (sc->phy_addr == 0x1E) { 950 /* XXX for SOC parts, this address may indicate a Roboswitch. */ 951 xprintf("100BaseT FDX (switch)\n"); 952 linkspeed = ETHER_SPEED_100FDX; 953 } 954 else { 955 /* Read twice to clear latching bits */ 956 status = mii_read(sc, MII_BMSR); 957 status = mii_read(sc, MII_BMSR); 958 959 if ((status & (BMSR_AUTONEG | BMSR_LINKSTAT)) == 960 (BMSR_AUTONEG | BMSR_LINKSTAT)) 961 control = mii_read(sc, MII_BMCR); 962 else { 963 for (timeout = 4*CFE_HZ; timeout > 0; timeout -= CFE_HZ/2) { 964 status = mii_read(sc, MII_BMSR); 965 if ((status & BMSR_ANCOMPLETE) != 0) 966 break; 967 cfe_sleep(CFE_HZ/2); 968 } 969 } 970 971 remote = mii_read(sc, MII_ANLPAR); 972 if ((status & BMSR_ANCOMPLETE) != 0) { 973 /* A link partner was negotiated... */ 974 975 if ((remote & ANLPAR_TXFD) != 0) { 976 xprintf("100BaseT FDX\n"); 977 linkspeed = ETHER_SPEED_100FDX; 978 } 979 else if ((remote & ANLPAR_TXHD) != 0) { 980 xprintf("100BaseT HDX\n"); 981 linkspeed = ETHER_SPEED_100HDX; 982 } 983 else if ((remote & ANLPAR_10FD) != 0) { 984 xprintf("10BaseT FDX\n"); 985 linkspeed = ETHER_SPEED_10FDX; 986 } 987 else if ((remote & ANLPAR_10HD) != 0) { 988 xprintf("10BaseT HDX\n"); 989 linkspeed = ETHER_SPEED_10HDX; 990 } 991 } 992 else { 993 /* no link partner convergence */ 994 xprintf("Unknown\n"); 995 linkspeed = ETHER_SPEED_UNKNOWN; 996 } 997 sc->linkspeed = linkspeed; 998 999 /* clear latching bits */ 1000 status = mii_read(sc, MII_BMSR); 1001 } 1002 1003 mii_dump(sc, "final PHY"); 1004} 1005 1006 1007static int 1008bcm4401_reset(bcm4401_softc *sc) 1009{ 1010 return -1; 1011} 1012 1013 1014/* SPROM access routines. Random read access to the SPROM will 1015 produce a bus error due to PCI timeouts. As an apparent 1016 (undocumented) side effect, the requested word will be fetched to a 1017 local buffer so that the next access will succeed. */ 1018 1019#define SPROM_SIZE 0x80 1020 1021static int 1022sprom_read_all(bcm4401_softc *sc, uint8_t dest[]) 1023{ 1024 int i; 1025 uint32_t t; 1026 jmpbuf_t *jb; 1027 1028 jb = exc_initialize_block(); 1029 if (jb == NULL) 1030 return -1; 1031 1032 for (i = 0; i < SPROM_SIZE; i += 4) { 1033 if (exc_try(jb) == 0) { 1034 /* On pass 2 parts, the following read gets a bus error */ 1035 t = READCSR(sc, SPROM_BASE + i); 1036 cfe_usleep(1000); 1037 /* the read with valid data (pass 1). */ 1038 t = READCSR(sc, SPROM_BASE + i); 1039 } 1040 else { 1041 /* and this one doesn't (pass 2). */ 1042 cfe_usleep(1000); /* Delay needed; value is empirical. */ 1043 t = READCSR(sc, SPROM_BASE + i); 1044 } 1045 1046 dest[i+0] = (t >> 8) & 0xFF; dest[i+1] = (t >> 0) & 0xFF; 1047 t >>= 16; 1048 dest[i+2] = (t >> 8) & 0xFF; dest[i+3] = (t >> 0) & 0xFF; 1049 1050 /* The following is a kludge, but otherwise setjmp is a one-shot. */ 1051 exc_handler.catch_exc = 1; 1052 } 1053 1054 exc_cleanup_block(jb); 1055 return 0; 1056} 1057 1058static void 1059sprom_dump(uint8_t srom[]) 1060{ 1061 int i; 1062 1063 xprintf("BCM4401: SPROM data:"); 1064 for (i = 0; i < SPROM_SIZE; i++) { 1065 if (i % 16 == 0) 1066 xprintf("\n %02x: ", i); 1067 xprintf(" %02x", srom[i]); 1068 } 1069 xprintf("\n"); 1070} 1071 1072 1073static int 1074bcm4401_set_hw_addr(bcm4401_softc *sc, uint8_t addr[]) 1075{ 1076 uint32_t enet_upper, enet_lower; 1077 int timeout; 1078 1079 enet_upper = (addr[0] << 8) | addr[1]; 1080 enet_lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; 1081 1082 WRITECSR(sc, R_CAM_DATA_H, M_CAM_VB | V_CAM_CD_H(enet_upper)); 1083 WRITECSR(sc, R_CAM_DATA_L, V_CAM_CD_L(enet_lower)); 1084 1085 WRITECSR(sc, R_CAM_CONTROL, V_CAMCTL_IX(0) | M_CAMCTL_CW); 1086 for (timeout = CFE_HZ; timeout > 0; timeout -= CFE_HZ/10) { 1087 if ((READCSR(sc, R_CAM_CONTROL) & M_CAMCTL_CB) != 0) 1088 break; 1089 cfe_sleep(1); 1090 } 1091 if (timeout <= 0) 1092 return -1; 1093 1094 return 0; 1095} 1096 1097 1098static void 1099bcm4401_set_linkspeed(bcm4401_softc *sc) 1100{ 1101 uint32_t ctrl; 1102 1103 ctrl = READCSR(sc, R_XMT_CONTROL1); 1104 switch (sc->linkspeed) { 1105 case ETHER_SPEED_100FDX: 1106 case ETHER_SPEED_10FDX: 1107 ctrl |= (M_TCTL_FD | M_TCTL_SB); 1108 break; 1109 default: 1110 ctrl &= ~(M_TCTL_FD | M_TCTL_SB); 1111 break; 1112 } 1113 WRITECSR(sc, R_XMT_CONTROL1, ctrl); 1114} 1115 1116static void 1117bcm4401_hwinit(bcm4401_softc *sc) 1118{ 1119 if (sc->state == eth_state_uninit) { 1120 uint32_t ctrl; 1121 1122 bcm4401_reset(sc); 1123 1124 mii_probe(sc); 1125 mii_dump(sc, "initial PHY"); 1126 1127 sc->phy_interrupt = 0; 1128 if (sc->phy_vendor == OUI_BCMxx) { 1129 uint16_t phy_isr; 1130 1131 switch (sc->phy_device) { 1132 case DEV_BCM5201: case DEV_BCM5221: 1133 case DEV_BCM4401: 1134 phy_isr = mii_read(sc, R_INTERRUPT); 1135 phy_isr &= ~(M_PHYINT_LI | M_PHYINT_SI | M_PHYINT_FD | 1136 M_PHYINT_MI); 1137 phy_isr |= M_PHYINT_IE; 1138 mii_write(sc, R_INTERRUPT, phy_isr); 1139 sc->phy_interrupt = 1; 1140 break; 1141 default: 1142 break; 1143 } 1144 } 1145 mii_autonegotiate(sc); 1146 if (sc->phy_interrupt) { 1147 (void)mii_read(sc, R_INTERRUPT); /* clear any pending */ 1148 } 1149 1150 bcm4401_set_hw_addr(sc, sc->hwaddr); 1151 WRITECSR(sc, R_CAM_CONTROL, M_CAMCTL_CE); 1152 1153 /* XXX Set the transmit watermark here, if needed. */ 1154 1155 /* Initialize the receive channel. */ 1156 WRITECSR(sc, R_RCV_PTR, 0); 1157 WRITECSR(sc, R_RCV_CONTROL, M_RCTL_RE | V_RCTL_RO(PKTBUF_RX_OFFSET)); 1158 WRITECSR(sc, R_RCV_ADDR, PTR_TO_PCI(sc, sc->rxdscrmem)); 1159 WRITECSR(sc, R_RCV_PTR, PTR_TO_PCI(sc, sc->rxdscr_add) & 0xFFF); 1160 1161 /* Initialize the transmit channel. */ 1162 WRITECSR(sc, R_XMT_PTR, 0); 1163 WRITECSR(sc, R_XMT_CONTROL, M_XCTL_XE); 1164 WRITECSR(sc, R_XMT_ADDR, PTR_TO_PCI(sc, sc->txdscrmem)); 1165 1166 /* Modify Ethernet RX MAC settings (probably obsolete). */ 1167 WRITECSR(sc, R_EMAC_XMT_MAX_BURST, 32); 1168 WRITECSR(sc, R_EMAC_RCV_MAX_BURST, 32); 1169#if 0 1170 WRITECSR(sc, R_RCV_CONFIG, M_RCFG_AM); /* All multicast */ 1171#else 1172 WRITECSR(sc, R_RCV_CONFIG, 0); 1173#endif 1174 WRITECSR(sc, R_RCV_MAX_LENGTH, MAX_ETHER_PACK); 1175 1176 ctrl = READCSR(sc, R_EMAC_CONTROL); 1177 ctrl |= M_EMCTL_CC; 1178 WRITECSR(sc, R_EMAC_CONTROL, ctrl); 1179 1180 bcm4401_set_linkspeed(sc); 1181 1182 WRITECSR(sc, R_XMT_MAX_LENGTH, MAX_ETHER_PACK); 1183 1184 WRITECSR(sc, R_INT_RECV_LAZY, V_INTLZY_FC(1) | V_INTLZY_TO(100)); 1185 1186 /* Enable the MAC */ 1187 ctrl = READCSR(sc, R_ENET_CONTROL); 1188 ctrl |= M_ECTL_EE; 1189 WRITECSR(sc, R_ENET_CONTROL, ctrl); 1190 1191 sc->state = eth_state_on; 1192 } 1193} 1194 1195 1196static void 1197bcm4401_setspeed(bcm4401_softc *sc, int speed) 1198{ 1199 /* XXX Not yet implemented - autonegotiation only. */ 1200 (void)mii_set_speed; 1201} 1202 1203static void 1204bcm4401_setloopback(bcm4401_softc *sc, int mode) 1205{ 1206 /* XXX Not yet implemented. */ 1207} 1208 1209 1210static void 1211bcm4401_isr(void *arg) 1212{ 1213 bcm4401_softc *sc = (bcm4401_softc *)arg; 1214 uint32_t status; 1215 1216#if IPOLL 1217 sc->interrupts++; 1218#endif 1219 1220 for (;;) { 1221 1222 /* Read and clear the interrupt status. */ 1223 status = READCSR(sc, R_INT_STATUS); 1224 status &= sc->intmask; 1225 if (status == 0) 1226 break; 1227 1228 WRITECSR(sc, R_INT_STATUS, status); /* write-to-clear */ 1229 1230 /* XXX Handle SERR, etc. */ 1231 1232 if (status & M_INT_RI) { 1233#if IPOLL 1234 sc->rx_interrupts++; 1235#endif 1236 bcm4401_procrxring(sc); 1237 } 1238 1239 if (status & M_INT_XI) { 1240#if IPOLL 1241 sc->tx_interrupts++; 1242#endif 1243 bcm4401_proctxring(sc); 1244 } 1245 1246 if (status & M_INT_TO) { 1247 sc->slow_poll = 1; 1248 } 1249 1250 if (status & (M_INT_XU | M_INT_RO)) { 1251 if (status & M_INT_XU) { 1252 xprintf("BCM4401: tx underrun, %08x\n", status); 1253 /* XXX Try to restart */ 1254 } 1255 if (status & M_INT_RO) { 1256 xprintf("BCM4401: rx overrun, %08x\n", status); 1257 /* XXX Try to restart */ 1258 } 1259 } 1260 } 1261} 1262 1263 1264static void 1265bcm4401_start(bcm4401_softc *sc) 1266{ 1267 uint32_t status; 1268 1269 bcm4401_hwinit(sc); 1270 1271 /* Set up loopback here */ 1272 1273 WRITECSR(sc, R_GP_TIMER, 0); /* stop the timer */ 1274 1275 sc->intmask = 0; 1276 WRITECSR(sc, R_INT_MASK, 0); 1277 status = READCSR(sc, R_INT_STATUS); /* clear any pending */ 1278 WRITECSR(sc, R_INT_STATUS, status); 1279 1280 sc->intmask = (M_INT_RI | M_INT_XI); /* XXX add errors */ 1281 if (sc->phy_interrupt) 1282 sc->intmask |= M_INT_TO; 1283 1284#if IPOLL 1285 cfe_request_irq(sc->irq, bcm4401_isr, sc, CFE_IRQ_FLAGS_SHARED, 0); 1286 WRITECSR(sc, R_INT_MASK, sc->intmask); 1287#endif 1288 1289 sc->slow_poll = 0; 1290 if (sc->phy_interrupt) { 1291 WRITECSR(sc, R_GP_TIMER, GP_TIMER_HZ/4); 1292 } 1293 1294 sc->state = eth_state_on; 1295} 1296 1297static void 1298bcm4401_stop(bcm4401_softc *sc) 1299{ 1300 uint32_t ctl, status; 1301 int i; 1302 1303 /* Cancel the timer */ 1304 if (sc->phy_interrupt) { 1305 WRITECSR(sc, R_GP_TIMER, 0); 1306 (void)READCSR(sc, R_GP_TIMER); 1307 } 1308 sc->slow_poll = 0; 1309 1310 /* Make sure that no further interrupts will be processed. */ 1311 sc->intmask = 0; 1312 WRITECSR(sc, R_INT_MASK, 0); 1313 (void)READCSR(sc, R_INT_MASK); /* push */ 1314 status = READCSR(sc, R_INT_STATUS); 1315 WRITECSR(sc, R_INT_STATUS, status); /* write-to-clear */ 1316 1317 /* Shut down MAC */ 1318 WRITECSR(sc, R_ENET_CONTROL, M_ECTL_ED); 1319 for (i = 1000; i > 0; i--) { 1320 ctl = READCSR(sc, R_ENET_CONTROL); 1321 if ((ctl & M_ECTL_ED) == 0) 1322 break; 1323 cfe_usleep(100); 1324 } 1325 if (i == 0) 1326 xprintf("%s: cannot clear MAC\n", bcm4401_devname(sc)); 1327 1328 /* Shut down DMA engines */ 1329 WRITECSR(sc, R_XMT_CONTROL, 0); 1330 for (i = 1000; i > 0; i--) { 1331 status = READCSR(sc, R_XMT_STATUS); 1332 if (G_XSTAT_XS(status) == K_XS_DISABLED) 1333 break; 1334 cfe_usleep(100); 1335 } 1336 if (i == 0) 1337 xprintf("%s: cannot clear tx DMA\n", bcm4401_devname(sc)); 1338 1339 WRITECSR(sc, R_RCV_CONTROL, 0); 1340 for (i = 1000; i > 0; i--) { 1341 status = READCSR(sc, R_RCV_STATUS); 1342 if (G_RSTAT_RS(status) == K_RS_DISABLED) 1343 break; 1344 cfe_usleep(100); 1345 } 1346 if (i == 0) 1347 xprintf("%s: cannot clear rx DMA\n", bcm4401_devname(sc)); 1348 1349 status = READCSR(sc, R_INT_STATUS); 1350 WRITECSR(sc, R_INT_STATUS, status); 1351#if IPOLL 1352 cfe_free_irq(sc->irq, 0); 1353#endif 1354 1355 /* Leave the mii inteface enabled */ 1356 mii_enable(sc); 1357} 1358 1359 1360/* Silicon Backplane initialization for the MAC core. */ 1361 1362static void 1363bcm4401_coreinit(bcm4401_softc *sc) 1364{ 1365 /* Enable the core by enabling the core clocks and then clearing 1366 RESET. The backplane mapping registers have been initialized 1367 from the SPROM, but a more paranoid implementation would 1368 reconfigure at this point. */ 1369 WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_RS | M_SBTS_CE | M_SBTS_FC); 1370 (void)READCSR(sc, R_SBTMSTATELOW); /* push */ 1371 cfe_usleep(100); 1372 1373 /* "PR3158 workaround - not fixed in any chip yet" */ 1374 if ((READCSR(sc, R_SBTMSTATEHI) & M_SBTS_SE) != 0) { 1375 WRITECSR(sc, R_SBTMSTATEHI, 0); 1376 } 1377 if ((READCSR(sc, R_SBIMSTATE) & (M_SBIS_IE | M_SBIS_TO)) != 0) { 1378 uint32_t sbis; 1379 sbis = READCSR(sc, R_SBIMSTATE); 1380 sbis &= ~(M_SBIS_IE | M_SBIS_TO); 1381 WRITECSR(sc, R_SBIMSTATE, sbis); 1382 } 1383 /* End of workaround */ 1384 1385 WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_CE | M_SBTS_FC); 1386 (void)READCSR(sc, R_SBTMSTATELOW); /* push */ 1387 cfe_usleep(100); 1388 WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_CE); 1389 (void)READCSR(sc, R_SBTMSTATELOW); /* push */ 1390 cfe_usleep(100); 1391} 1392 1393 1394/* Declarations for CFE Device Driver Interface routines */ 1395 1396static int bcm4401_ether_open(cfe_devctx_t *ctx); 1397static int bcm4401_ether_read(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1398static int bcm4401_ether_inpstat(cfe_devctx_t *ctx,iocb_inpstat_t *inpstat); 1399static int bcm4401_ether_write(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1400static int bcm4401_ether_ioctl(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1401static int bcm4401_ether_close(cfe_devctx_t *ctx); 1402static void bcm4401_ether_poll(cfe_devctx_t *ctx, int64_t ticks); 1403static void bcm4401_ether_reset(void *softc); 1404 1405 1406/* CFE Device Driver dispatch structure */ 1407 1408const static cfe_devdisp_t bcm4401_ether_dispatch = { 1409 bcm4401_ether_open, 1410 bcm4401_ether_read, 1411 bcm4401_ether_inpstat, 1412 bcm4401_ether_write, 1413 bcm4401_ether_ioctl, 1414 bcm4401_ether_close, 1415 bcm4401_ether_poll, 1416 bcm4401_ether_reset 1417}; 1418 1419 1420#if CFG_PCI 1421/* CFE Device Driver probe functions for PCI NIC (bcm4401) */ 1422 1423/* The following are for the cores as packaged in the 4401. */ 1424 1425#define SB4401_ENET_BASE 0x18000000 1426#define SB4401_CODEC_BASE 0x18001000 /* bond-out on 4402 only */ 1427#define SB4401_PCI_BASE 0x18002000 1428 1429#define K_SB4401INT_PCI (1<<0) 1430#define K_SB4401INT_ENET_MAC (1<<1) 1431#define K_SB4401INT_CODEC (1<<2) 1432 1433const cfe_driver_t bcm4401drv = { 1434 "BCM4401 Ethernet", 1435 "eth", 1436 CFE_DEV_NETWORK, 1437 &bcm4401_ether_dispatch, 1438 bcm4401_ether_probe 1439}; 1440 1441static void 1442bcm4401_pciconfig(bcm4401_softc *sc) 1443{ 1444 uint32_t oldsb; 1445 uint32_t idhigh; 1446 uint32_t xlat; 1447 1448 oldsb = pci_conf_read(sc->tag, PCI_PCIBAR0WINDOW_REG); 1449 pci_conf_write(sc->tag, PCI_PCIBAR0WINDOW_REG, SB4401_PCI_BASE); 1450 (void)pci_conf_read(sc->tag, PCI_PCIBAR0WINDOW_REG); /* push */ 1451 1452 idhigh = READCSR(sc, R_SBIDHIGH); 1453 if (G_SBID_RV(idhigh) < 6) { 1454 /* A0 and A1 parts */ 1455 WRITECSR(sc, R_SBINTVEC, V_SBINT_MK(K_SB4401INT_ENET_MAC)); 1456 } 1457 else { 1458 /* B0 parts (PCI Rev 2.3 support) */ 1459 uint32_t mask; 1460 1461 mask = pci_conf_read(sc->tag, PCI_PCIINTMASK_REG); 1462 mask |= V_SBINT_IM(K_SB4401INT_ENET_MAC); 1463 pci_conf_write(sc->tag, PCI_PCIINTMASK_REG, mask); 1464 } 1465 1466 xlat = READCSR(sc, R_SB_TO_PCI_TRANSLATION2); 1467 xlat |= (M_SBXLAT_PE | M_SBXLAT_WB); 1468 WRITECSR(sc, R_SB_TO_PCI_TRANSLATION2, xlat); 1469 1470 (void)READCSR(sc, R_SB_TO_PCI_TRANSLATION2); /* push */ 1471 1472 pci_conf_write(sc->tag, PCI_PCIBAR0WINDOW_REG, oldsb); 1473 (void)pci_conf_read(sc->tag, PCI_PCIBAR0WINDOW_REG); /* push */ 1474} 1475 1476static int 1477bcm4401_ether_attach(cfe_driver_t *drv, pcitag_t tag) 1478{ 1479 bcm4401_softc *sc; 1480 uint32_t device; 1481 uint32_t class; 1482 phys_addr_t pa; 1483 uint8_t sprom[SPROM_SIZE]; 1484 char descr[100]; 1485 1486 device = pci_conf_read(tag, PCI_ID_REG); 1487 class = pci_conf_read(tag, PCI_CLASS_REG); 1488 1489 /* Use memory space for the CSRs */ 1490 pci_map_mem(tag, PCI_MAPREG(0), PCI_MATCH_BITS, &pa); 1491 1492 sc = (bcm4401_softc *) KMALLOC(sizeof(bcm4401_softc), 0); 1493 1494 if (sc == NULL) { 1495 xprintf("BCM4401: No memory to complete probe\n"); 1496 return 0; 1497 } 1498 memset(sc, 0, sizeof(*sc)); 1499 1500 sc->phys_to_dma = phys_to_pci; 1501 sc->dma_to_phys = pci_to_phys; 1502 1503 sc->membase = (uint32_t)pa; 1504 sc->irq = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG) & 0xFF; 1505 sc->tag = tag; 1506 1507 sc->device = PCI_PRODUCT(device); 1508 sc->revision = PCI_REVISION(class); 1509 sc->devctx = NULL; 1510 1511 sc->linkspeed = ETHER_SPEED_AUTO; /* only autonegotiation for now */ 1512 sc->loopback = ETHER_LOOPBACK_OFF; 1513 1514 /* SOC core initialization. */ 1515 bcm4401_coreinit(sc); 1516 1517 bcm4401_pciconfig(sc); 1518 1519 mii_enable(sc); 1520 1521 bcm4401_init(sc); 1522 1523 sprom_read_all(sc, sprom); 1524 if (B44_DEBUG) sprom_dump(sprom); 1525 1526 /* Use the address in EEPROM. */ 1527 memcpy(sc->hwaddr, &sprom[SPROM_MAC_ADDR], ENET_ADDR_LEN); 1528 sc->phy_addr = sprom[SPROM_PHY_ADDR] & 0x1F; 1529 1530 sc->state = eth_state_uninit; 1531 1532 xsprintf(descr, "%s at 0x%X (%a)", 1533 drv->drv_description, sc->membase, sc->hwaddr); 1534 1535 cfe_attach(drv, sc, NULL, descr); 1536 return 1; 1537} 1538 1539static void 1540bcm4401_ether_probe(cfe_driver_t *drv, 1541 unsigned long probe_a, unsigned long probe_b, 1542 void *probe_ptr) 1543{ 1544 int index; 1545 1546 index = 0; 1547 for (;;) { 1548 pcitag_t tag; 1549 pcireg_t device; 1550 1551 if (pci_find_class(PCI_CLASS_NETWORK, index, &tag) != 0) 1552 break; 1553 1554 index++; 1555 1556 device = pci_conf_read(tag, PCI_ID_REG); 1557 if (PCI_VENDOR(device) == K_PCI_VENDOR_BROADCOM) { 1558 switch (PCI_PRODUCT(device)) { 1559 case K_PCI_ID_BCM4401: 1560 case K_PCI_ID_BCM4401_B: 1561 case K_PCI_ID_BCM4402: 1562 bcm4401_ether_attach(drv, tag); 1563 break; 1564 default: 1565 break; 1566 } 1567 } 1568 } 1569} 1570#endif /* CFG_PCI */ 1571 1572 1573/* CFE Device Driver probe functions for SOC core. */ 1574 1575const cfe_driver_t sb_mac = { 1576 "BCM47xx Ethernet", 1577 "eth", 1578 CFE_DEV_NETWORK, 1579 &bcm4401_ether_dispatch, 1580 sb_ether_probe 1581}; 1582 1583 1584static int 1585sb_ether_attach(cfe_driver_t *drv, 1586 int unit, const char *mac_addr, int phy_addr) 1587{ 1588 bcm4401_softc *sc; 1589 phys_addr_t pa; 1590 uint32_t flag, id; 1591 char descr[100]; 1592 1593 /* XXX The map of enumeration space should be discovered by scanning. */ 1594#ifdef SB_ENET1_BASE 1595 static const phys_addr_t enet_base[2] = {SB_ENET0_BASE, SB_ENET1_BASE}; 1596#else 1597 static const phys_addr_t enet_base[1] = {SB_ENET0_BASE}; 1598#endif 1599 1600 /* Use memory space for the CSRs */ 1601 pa = enet_base[unit]; 1602 1603 sc = (bcm4401_softc *) KMALLOC(sizeof(bcm4401_softc), CACHE_ALIGN); 1604 if (sc == NULL) { 1605 xprintf("BCM4xxx MAC: No memory to complete probe\n"); 1606 return 0; 1607 } 1608 memset(sc, 0, sizeof(*sc)); 1609 1610 sc->membase = (uint32_t)pa; 1611 1612 sc->phys_to_dma = phys_to_sb; 1613 sc->dma_to_phys = sb_to_phys; 1614 1615 flag = READCSR(sc, R_SBTPSFLAG); 1616 sc->irq = G_SBTSF_FN(flag); 1617 sc->tag = 0; 1618 id = READCSR(sc, R_SBIDHIGH); 1619 sc->device = G_SBID_CR(id); 1620 sc->revision = G_SBID_RV(id); 1621 sc->devctx = NULL; 1622 1623 sc->linkspeed = ETHER_SPEED_AUTO; /* select autonegotiation */ 1624 sc->loopback = ETHER_LOOPBACK_OFF; 1625 1626 /* Enable the core by enabling the core clocks and then clearing 1627 RESET. The backplane mapping registers are fixed but vary 1628 among the various 47xx SOCs. */ 1629 WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_RS | M_SBTS_CE | M_SBTS_FC); 1630 (void)READCSR(sc, R_SBTMSTATELOW); /* push */ 1631 cfe_usleep(100); 1632 1633 /* "PR3158 workaround - not fixed in any chip yet" */ 1634 if ((READCSR(sc, R_SBTMSTATEHI) & M_SBTS_SE) != 0) { 1635 WRITECSR(sc, R_SBTMSTATEHI, 0); 1636 } 1637 if ((READCSR(sc, R_SBIMSTATE) & (M_SBIS_IE | M_SBIS_TO)) != 0) { 1638 uint32_t sbis; 1639 sbis = READCSR(sc, R_SBIMSTATE); 1640 sbis &= ~(M_SBIS_IE | M_SBIS_TO); 1641 WRITECSR(sc, R_SBIMSTATE, sbis); 1642 } 1643 /* End of workaround */ 1644 1645 WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_CE | M_SBTS_FC); 1646 (void)READCSR(sc, R_SBTMSTATELOW); /* push */ 1647 cfe_usleep(100); 1648 WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_CE); 1649 (void)READCSR(sc, R_SBTMSTATELOW); /* push */ 1650 cfe_usleep(100); 1651 1652 bcm4401_coreinit(sc); 1653 1654 mii_enable(sc); 1655 1656 bcm4401_init(sc); 1657 1658 /* XXX How should 47xx SOCs get their MAC addresses? */ 1659 (void)sprom_read_all; 1660 (void)sprom_dump; 1661 if (mac_addr) { 1662 enet_parse_hwaddr(mac_addr, sc->hwaddr); 1663 } 1664 else { 1665 sc->hwaddr[0] = 0x02; sc->hwaddr[1] = 0x00; sc->hwaddr[2] = 0x00; 1666 sc->hwaddr[3] = 0x47; sc->hwaddr[4] = 0x10; sc->hwaddr[5] = 0x10+unit; 1667 } 1668 sc->phy_addr = phy_addr; 1669 1670 sc->state = eth_state_uninit; 1671 1672 xsprintf(descr, "%s at 0x%X (%a)", 1673 drv->drv_description, sc->membase, sc->hwaddr); 1674 1675 cfe_attach(drv, sc, NULL, descr); 1676 return 1; 1677} 1678 1679/* 1680 * Probe arguments: 1681 * probe_a - index of the MAC to probe 1682 * probe_b - PHY address for MII 1683 * probe_ptr - string pointer to hardware address for this 1684 * MAC, in the form xx:xx:xx:xx:xx:xx. 1685 */ 1686 1687static void 1688sb_ether_probe(cfe_driver_t *drv, 1689 unsigned long probe_a, unsigned long probe_b, 1690 void *probe_ptr) 1691{ 1692 int index = probe_a; 1693 int phy_addr = probe_b; 1694 const char *mac_addr = probe_ptr; 1695 1696 if (index == 0 || index == 1) 1697 sb_ether_attach(drv, index, mac_addr, phy_addr); 1698} 1699 1700 1701/* The functions below are called via the dispatch vector for the 4401. */ 1702 1703static int 1704bcm4401_ether_open(cfe_devctx_t *ctx) 1705{ 1706 bcm4401_softc *sc = ctx->dev_softc; 1707 1708 if (sc->state == eth_state_on) 1709 bcm4401_stop(sc); 1710 1711 sc->devctx = ctx; 1712 1713 sc->inpkts = sc->outpkts = 0; 1714 sc->interrupts = 0; 1715 sc->rx_interrupts = sc->tx_interrupts = 0; 1716 1717 bcm4401_start(sc); 1718 1719#if XPOLL 1720 bcm4401_isr(sc); 1721#endif 1722 1723 return 0; 1724} 1725 1726static int 1727bcm4401_ether_read(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1728{ 1729 bcm4401_softc *sc = ctx->dev_softc; 1730 eth_pkt_t *pkt; 1731 int blen; 1732 1733#if XPOLL 1734 bcm4401_isr(sc); 1735#endif 1736 1737 if (sc->state != eth_state_on) return -1; 1738 1739 CS_ENTER(sc); 1740 pkt = (eth_pkt_t *) q_deqnext(&(sc->rxqueue)); 1741 CS_EXIT(sc); 1742 1743 if (pkt == NULL) { 1744 buffer->buf_retlen = 0; 1745 return 0; 1746 } 1747 1748 blen = buffer->buf_length; 1749 if (blen > pkt->length) blen = pkt->length; 1750 1751 CACHE_DMA_INVAL(pkt->buffer+PKTBUF_RX_OFFSET, blen); 1752 hs_memcpy_to_hs(buffer->buf_ptr, pkt->buffer+PKTBUF_RX_OFFSET, blen); 1753 buffer->buf_retlen = blen; 1754 1755 eth_free_pkt(sc, pkt); 1756 bcm4401_fillrxring(sc); 1757 1758#if XPOLL 1759 bcm4401_isr(sc); 1760#endif 1761 1762 return 0; 1763} 1764 1765static int 1766bcm4401_ether_inpstat(cfe_devctx_t *ctx, iocb_inpstat_t *inpstat) 1767{ 1768 bcm4401_softc *sc = ctx->dev_softc; 1769 1770#if XPOLL 1771 bcm4401_isr(sc); 1772#endif 1773 1774 if (sc->state != eth_state_on) return -1; 1775 1776 /* We avoid an interlock here because the result is a hint and an 1777 interrupt cannot turn a non-empty queue into an empty one. */ 1778 inpstat->inp_status = (q_isempty(&(sc->rxqueue))) ? 0 : 1; 1779 1780 return 0; 1781} 1782 1783static int 1784bcm4401_ether_write(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1785{ 1786 bcm4401_softc *sc = ctx->dev_softc; 1787 eth_pkt_t *pkt; 1788 int blen; 1789 1790#if XPOLL 1791 bcm4401_isr(sc); 1792#endif 1793 1794 if (sc->state != eth_state_on) return -1; 1795 1796 pkt = eth_alloc_pkt(sc); 1797 if (!pkt) return CFE_ERR_NOMEM; 1798 1799 blen = buffer->buf_length; 1800 if (blen > pkt->length) blen = pkt->length; 1801 1802 hs_memcpy_from_hs(pkt->buffer, buffer->buf_ptr, blen); 1803 pkt->length = blen; 1804 CACHE_DMA_SYNC(pkt->buffer, blen); 1805 1806 if (bcm4401_transmit(sc, pkt) != 0) { 1807 eth_free_pkt(sc,pkt); 1808 return CFE_ERR_IOERR; 1809 } 1810 1811#if XPOLL 1812 bcm4401_isr(sc); 1813#endif 1814 1815 return 0; 1816} 1817 1818static int 1819bcm4401_ether_ioctl(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1820{ 1821 bcm4401_softc *sc = ctx->dev_softc; 1822 int mode; 1823 int speed; 1824 1825 switch ((int)buffer->buf_ioctlcmd) { 1826 case IOCTL_ETHER_GETHWADDR: 1827 hs_memcpy_to_hs(buffer->buf_ptr, sc->hwaddr, sizeof(sc->hwaddr)); 1828 return 0; 1829 1830 case IOCTL_ETHER_SETHWADDR: 1831 return -1; /* not supported */ 1832 1833 case IOCTL_ETHER_GETSPEED: 1834 speed = sc->linkspeed; 1835 hs_memcpy_to_hs(buffer->buf_ptr, &speed, sizeof(speed)); 1836 return 0; 1837 1838 case IOCTL_ETHER_SETSPEED: 1839 hs_memcpy_from_hs(&speed,buffer->buf_ptr, sizeof(speed)); 1840 bcm4401_setspeed(sc, speed); 1841 return -1; /* not supported yet */ 1842 1843 case IOCTL_ETHER_GETLINK: 1844 speed = sc->linkspeed; 1845 hs_memcpy_to_hs(buffer->buf_ptr, &speed, sizeof(speed)); 1846 return 0; 1847 1848 case IOCTL_ETHER_GETLOOPBACK: 1849 speed = sc->loopback; 1850 hs_memcpy_to_hs(buffer->buf_ptr, &speed, sizeof(speed)); 1851 return 0; 1852 1853 case IOCTL_ETHER_SETLOOPBACK: 1854 hs_memcpy_from_hs(&mode,buffer->buf_ptr, sizeof(mode)); 1855 sc->loopback = ETHER_LOOPBACK_OFF; /* default */ 1856 if (mode == ETHER_LOOPBACK_INT || mode == ETHER_LOOPBACK_EXT) { 1857 bcm4401_setloopback(sc, mode); 1858 } 1859 return -1; /* not supported yet */ 1860 1861 default: 1862 return -1; 1863 } 1864} 1865 1866static int 1867bcm4401_ether_close(cfe_devctx_t *ctx) 1868{ 1869 bcm4401_softc *sc = ctx->dev_softc; 1870 1871 sc->state = eth_state_off; 1872 bcm4401_stop(sc); 1873 1874 xprintf("%s: %d sent, %d received, %d interrupts\n", 1875 bcm4401_devname(sc), sc->outpkts, sc->inpkts, sc->interrupts); 1876 if (IPOLL) { 1877 xprintf(" %d tx interrupts, %d rx interrupts\n", 1878 sc->tx_interrupts, sc->rx_interrupts); 1879 } 1880 1881 /* resynchronize descriptor rings */ 1882 bcm4401_resetrings(sc); 1883 1884 sc->devctx = NULL; 1885#if 1 /* XXX Redo partitioning among hwinit, start and stop */ 1886 sc->state = eth_state_uninit; 1887#endif 1888 return 0; 1889} 1890 1891static void 1892bcm4401_ether_poll(cfe_devctx_t *ctx, int64_t ticks) 1893{ 1894 bcm4401_softc *sc = (bcm4401_softc *)ctx->dev_softc; 1895 uint16_t phy_isr; 1896 1897 /* The PHY Interrupt register appears to work as claimed with 1898 respect to link status changes, but I've had no luck clearing 1899 the MIIInt bit in the EnetIntStatus register. We therefore use 1900 polling but reduce the frequency since reading MII registers is 1901 expensive. */ 1902 if (sc->slow_poll) { 1903 sc->slow_poll = 0; 1904 if (sc->phy_interrupt) { 1905 phy_isr = mii_interrupt(sc); 1906 if ((phy_isr & (M_PHYINT_LC | M_PHYINT_SP | M_PHYINT_DC)) != 0) { 1907 mii_autonegotiate(sc); 1908 bcm4401_set_linkspeed(sc); 1909 } 1910 } 1911 } 1912} 1913 1914static void 1915bcm4401_ether_reset(void *softc) 1916{ 1917 bcm4401_softc *sc = (bcm4401_softc *)softc; 1918 1919 /* Turn off the Ethernet interface. */ 1920 if (sc->state == eth_state_on) 1921 bcm4401_stop(sc); 1922 bcm4401_reset(sc); 1923 1924 sc->state = eth_state_uninit; 1925} 1926