1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * DC21x4x Ethernet Driver File: dev_tulip.c 5 * 6 * Author: Ed Satterthwaite 7 * 8 ********************************************************************* 9 * 10 * Copyright 2000,2001,2002,2003,2004 11 * Broadcom Corporation. All rights reserved. 12 * 13 * This software is furnished under license and may be used and 14 * copied only in accordance with the following terms and 15 * conditions. Subject to these conditions, you may download, 16 * copy, install, use, modify and distribute modified or unmodified 17 * copies of this software in source and/or binary form. No title 18 * or ownership is transferred hereby. 19 * 20 * 1) Any source code used, modified or distributed must reproduce 21 * and retain this copyright notice and list of conditions 22 * as they appear in the source file. 23 * 24 * 2) No right is granted to use any trade name, trademark, or 25 * logo of Broadcom Corporation. The "Broadcom Corporation" 26 * name may not be used to endorse or promote products derived 27 * from this software without the prior written permission of 28 * Broadcom Corporation. 29 * 30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 42 * THE POSSIBILITY OF SUCH DAMAGE. 43 ********************************************************************* */ 44 45#include "cfe.h" 46#include "lib_physio.h" 47 48#ifdef CPUCFG_MEMCPY 49#error "This is broken right now." 50extern void *CPUCFG_MEMCPY(void *dest, const void *src, size_t cnt); 51#define blockcopy CPUCFG_MEMCPY 52#else 53#define blockcopy memcpy 54#endif 55 56#include "cfe_irq.h" 57 58#include "net_enet.h" 59 60#include "pcivar.h" 61#include "pcireg.h" 62 63#include "dc21143.h" 64#include "mii.h" 65 66/* This is a driver for specific configurations of the DC21040, DC21041, 67 DC21140A and DC21143, not a generic Tulip driver. The prefix 68 "tulip_" is used to indicate generic Tulip functions, while 69 "dc21040_", "dc21041_", "dc21140_" or "dc21143_" indicates functions 70 specific to a chip variant. 71 72 The 21041 driver assumes a 10BT HD interface, since autonegotiation 73 is known to be broken in the early revisons of that chip. Example 74 cards come from DEC and SMC. Essentially the same driver is used 75 for 21040 cards. 76 77 The 21140 driver assumes that the PHY uses a standard MII interface 78 for both 100BT and 10BT. Example cards come from DEC (National DP83840 79 plus Twister PHY) and Netgear (Level One PHY). 80 81 Some early 21140 boards are exceptions and use SYM plus SRL 82 with different PHY chips for 10 and 100 (limited support). 83 84 The 21143 driver assumes by default that the PHY uses the SYM ("5 85 wire") interface for 100BT with pass-through for 10BT. Example 86 cards come from DEC (MicroLinear ML6694 PHY) and Znyx (QS6611 or 87 Kendin KS8761 PHY). It also supports an MII interface for 88 recognized adapters. An example card comes from Adaptec (National 89 DP83840A and Twister PHY). There is no support for AUI interfaces. 90 91 The SB1250 version takes advantage of DMA coherence and uses 92 "preserve bit lanes" addresses for all accesses that cross the 93 ZBbus-PCI bridge. For non-coherent memory systems, all addresses 94 of descriptors are converted to do uncached access, and packet data 95 is flushed as required. */ 96 97#ifndef TULIP_DEBUG 98#define TULIP_DEBUG 0 99#endif 100 101#if ((ENDIAN_BIG + ENDIAN_LITTLE) != 1) 102#error "dev_tulip: system endian not set" 103#endif 104 105/* Set IPOLL to drive processing through the pseudo-interrupt 106 dispatcher. Set XPOLL to drive processing by an external polling 107 agent. Setting both is ok. */ 108 109#ifndef IPOLL 110#define IPOLL 0 111#endif 112#ifndef XPOLL 113#define XPOLL 1 114#endif 115 116#define MAX_ETHER_PACK (ENET_MAX_PKT+ENET_CRC_SIZE) /* max packet size */ 117 118/* Packet buffers. For tulip, the packet must be aligned to a 32-bit 119 word boundary, and we would like it aligned to a cache line 120 boundary for performance. */ 121 122#define CACHE_ALIGN 32 123#define ALIGN(n,align) (((n)+((align)-1)) & ~((align)-1)) 124 125typedef struct eth_pkt_s { 126 queue_t next; /* 8 */ 127 uint8_t *buffer; /* 4 */ 128 uint32_t flags; /* 4 */ 129 int32_t length; /* 4 */ 130 uint32_t unused[3]; /* 12 */ 131 uint8_t data[MAX_ETHER_PACK]; 132} eth_pkt_t; 133 134#define ETH_PKTBUF_LINES ((sizeof(eth_pkt_t) + (CACHE_ALIGN-1))/CACHE_ALIGN) 135#define ETH_PKTBUF_SIZE (ETH_PKTBUF_LINES*CACHE_ALIGN) 136#define ETH_PKTBUF_OFFSET (offsetof(eth_pkt_t, data)) 137 138#define ETH_PKT_BASE(data) ((eth_pkt_t *)((data) - ETH_PKTBUF_OFFSET)) 139 140/* packet flags */ 141#define ETH_TX_SETUP 1 /* assumes Perfect Filtering format */ 142 143static void 144show_packet(char c, eth_pkt_t *pkt) 145{ 146 int i; 147 int n = (pkt->length < 32 ? pkt->length : 32); 148 149 xprintf("%c[%4d]:", c, pkt->length); 150 for (i = 0; i < n; i++) { 151 if (i % 4 == 0) 152 xprintf(" "); 153 xprintf("%02x", pkt->buffer[i]); 154 } 155 xprintf("\n"); 156} 157 158 159/* Descriptor structures */ 160 161typedef struct rx_dscr { 162 uint32_t rxd_flags; 163 uint32_t rxd_bufsize; 164 pci_addr_t rxd_bufaddr1; 165 pci_addr_t rxd_bufaddr2; 166} rx_dscr; 167 168typedef struct tx_dscr { 169 uint32_t txd_flags; 170 uint32_t txd_bufsize; 171 pci_addr_t txd_bufaddr1; 172 pci_addr_t txd_bufaddr2; 173} tx_dscr; 174 175/* CAM structure */ 176 177typedef union { 178 struct { 179 uint32_t physical[CAM_PERFECT_ENTRIES][3]; 180 } p; 181 struct { 182 uint32_t hash[32]; 183 uint32_t mbz[7]; 184 uint32_t physical[3]; 185 } h; 186} tulip_cam; 187 188 189/* Driver data structures */ 190 191typedef enum { 192 eth_state_uninit, 193 eth_state_setup, 194 eth_state_off, 195 eth_state_on, 196 eth_state_broken 197} eth_state_t; 198 199#define ETH_PKTPOOL_SIZE 32 200#define ETH_PKT_SIZE MAX_ETHER_PACK 201 202typedef struct tulip_softc { 203 uint32_t membase; 204 uint8_t irq; /* interrupt mapping (used if IPOLL) */ 205 pcitag_t tag; /* tag for configuration registers */ 206 207 uint8_t hwaddr[ENET_ADDR_LEN]; 208 uint16_t device; /* chip device code */ 209 uint8_t revision; /* chip revision and step (Table 3-7) */ 210 211 /* current state */ 212 eth_state_t state; 213 214 /* These fields are the chip startup values. */ 215// uint16_t media; /* media type */ 216 uint32_t opmode; /* operating mode */ 217 uint32_t intmask; /* interrupt mask */ 218 uint32_t gpdata; /* output bits for csr15 (21143) */ 219 220 /* These fields are set before calling dc21x4x_hwinit */ 221 int linkspeed; /* encodings from cfe_ioctl */ 222 int loopback; 223 224 /* Packet free list */ 225 queue_t freelist; 226 uint8_t *pktpool; 227 queue_t rxqueue; 228 229 /* The descriptor tables */ 230 uint8_t *rxdscrmem; /* receive descriptors */ 231 uint8_t *txdscrmem; /* transmit descriptors */ 232 233 /* These fields keep track of where we are in tx/rx processing */ 234 volatile rx_dscr *rxdscr_start; /* beginning of ring */ 235 volatile rx_dscr *rxdscr_end; /* end of ring */ 236 volatile rx_dscr *rxdscr_remove; /* next one we expect tulip to use */ 237 volatile rx_dscr *rxdscr_add; /* next place to put a buffer */ 238 int rxdscr_onring; 239 240 volatile tx_dscr *txdscr_start; /* beginning of ring */ 241 volatile tx_dscr *txdscr_end; /* end of ring */ 242 volatile tx_dscr *txdscr_remove; /* next one we will use for tx */ 243 volatile tx_dscr *txdscr_add; /* next place to put a buffer */ 244 245 cfe_devctx_t *devctx; 246 247 /* These fields describe the PHY */ 248 enum {NONE, SRL, MII, SYM} phy_type; 249 int phy_addr; 250 uint32_t phy_vendor; 251 uint16_t phy_device; 252 253 /* Statistics */ 254 uint32_t inpkts; 255 uint32_t outpkts; 256 uint32_t interrupts; 257 uint32_t rx_interrupts; 258 uint32_t tx_interrupts; 259 uint32_t bus_errors; 260} tulip_softc; 261 262 263/* Entry to and exit from critical sections (currently relative to 264 interrupts only, not SMP) */ 265 266#if CFG_INTERRUPTS 267#define CS_ENTER(sc) cfe_disable_irq(sc->irq) 268#define CS_EXIT(sc) cfe_enable_irq(sc->irq) 269#else 270#define CS_ENTER(sc) ((void)0) 271#define CS_EXIT(sc) ((void)0) 272#endif 273 274 275/* Driver parameterization */ 276 277#define MAXRXDSCR 32 278#define MAXTXDSCR 32 279#define MINRXRING 8 280 281#define MEDIA_UNKNOWN 0 282#define MEDIA_AUI 1 283#define MEDIA_BNC 2 284#define MEDIA_UTP_FULL_DUPLEX 3 285#define MEDIA_UTP_NO_LINK_TEST 4 286#define MEDIA_UTP 5 287 288/* Prototypes */ 289 290static void tulip_ether_probe(cfe_driver_t *drv, 291 unsigned long probe_a, unsigned long probe_b, 292 void *probe_ptr); 293 294 295/* Address mapping macros */ 296 297/* Note that PTR_TO_PHYS only works with 32-bit addresses, but then 298 so does the Tulip. */ 299#if CFG_L2_RAM /* Temporarily here for SiByte SOCs running from L2 */ 300#define PTR_TO_PHYS(x) (((uintptr_t)(x)) + 0xD0000000) 301#define PHYS_TO_PTR(a) ((uint8_t *)((a) - 0xD0000000)) 302#else 303#define PTR_TO_PHYS(x) (PHYSADDR((uintptr_t)(x))) 304#define PHYS_TO_PTR(a) ((uint8_t *)KERNADDR(a)) 305#endif 306 307#define PCI_TO_PTR(a) (PHYS_TO_PTR(PCI_TO_PHYS(a))) 308#define PTR_TO_PCI(x) (PHYS_TO_PCI(PTR_TO_PHYS(x))) 309 310#define READCSR(sc,csr) (phys_read32((sc)->membase + (csr))) 311#define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) 312 313 314#define RESET_ADAPTER(sc) \ 315 { \ 316 WRITECSR((sc), R_CSR_BUSMODE, M_CSR0_SWRESET); \ 317 cfe_sleep(CFE_HZ/10); \ 318 } 319 320 321/* Debugging */ 322 323static void 324dumpstat(tulip_softc *sc) 325{ 326 xprintf("-- CSR 5 = %08X CSR 6 = %08x\n", 327 READCSR(sc, R_CSR_STATUS), READCSR(sc, R_CSR_OPMODE)); 328} 329 330static void 331dumpcsrs(tulip_softc *sc) 332{ 333 int idx; 334 335 xprintf("-------------\n"); 336 for (idx = 0; idx < 16; idx++) { 337 xprintf("CSR %2d = %08X\n", idx, READCSR(sc, idx*8)); 338 } 339 xprintf("-------------\n"); 340} 341 342 343/* Packet management */ 344 345/* ********************************************************************* 346 * ETH_ALLOC_PKT(sc) 347 * 348 * Allocate a packet from the free list. 349 * 350 * Input parameters: 351 * sc - eth structure 352 * 353 * Return value: 354 * pointer to packet structure, or NULL if none available 355 ********************************************************************* */ 356static eth_pkt_t * 357eth_alloc_pkt(tulip_softc *sc) 358{ 359 eth_pkt_t *pkt; 360 361 CS_ENTER(sc); 362 pkt = (eth_pkt_t *) q_deqnext(&sc->freelist); 363 CS_EXIT(sc); 364 if (!pkt) return NULL; 365 366 pkt->buffer = pkt->data; 367 pkt->length = ETH_PKT_SIZE; 368 pkt->flags = 0; 369 370 return pkt; 371} 372 373 374/* ********************************************************************* 375 * ETH_FREE_PKT(sc,pkt) 376 * 377 * Return a packet to the free list 378 * 379 * Input parameters: 380 * sc - sbmac structure 381 * pkt - packet to return 382 * 383 * Return value: 384 * nothing 385 ********************************************************************* */ 386static void 387eth_free_pkt(tulip_softc *sc, eth_pkt_t *pkt) 388{ 389 CS_ENTER(sc); 390 q_enqueue(&sc->freelist, &pkt->next); 391 CS_EXIT(sc); 392} 393 394 395/* ********************************************************************* 396 * ETH_INITFREELIST(sc) 397 * 398 * Initialize the buffer free list for this mac. The memory 399 * allocated to the free list is carved up and placed on a linked 400 * list of buffers for use by the mac. 401 * 402 * Input parameters: 403 * sc - eth structure 404 * 405 * Return value: 406 * nothing 407 ********************************************************************* */ 408static void 409eth_initfreelist(tulip_softc *sc) 410{ 411 int idx; 412 uint8_t *ptr; 413 eth_pkt_t *pkt; 414 415 q_init(&sc->freelist); 416 417 ptr = sc->pktpool; 418 for (idx = 0; idx < ETH_PKTPOOL_SIZE; idx++) { 419 pkt = (eth_pkt_t *) ptr; 420 eth_free_pkt(sc, pkt); 421 ptr += ETH_PKTBUF_SIZE; 422 } 423} 424 425 426/* Utilities */ 427 428static const char * 429tulip_devname(tulip_softc *sc) 430{ 431 return (sc->devctx != NULL ? cfe_device_name(sc->devctx) : "eth?"); 432} 433 434 435/* Descriptor ring management */ 436 437static int 438tulip_add_rcvbuf(tulip_softc *sc, eth_pkt_t *pkt) 439{ 440 volatile rx_dscr *rxd; 441 volatile rx_dscr *nextrxd; 442 uint32_t ctrl = 0; 443 444 rxd = sc->rxdscr_add; 445 446 /* Figure out where the next descriptor will go */ 447 nextrxd = rxd+1; 448 if (nextrxd == sc->rxdscr_end) { 449 nextrxd = sc->rxdscr_start; 450 ctrl = M_RDES1_ENDOFRING; 451 } 452 453 /* If the next one is the same as our remove pointer, the ring is 454 considered full. */ 455 if (nextrxd == sc->rxdscr_remove) return -1; 456 457 rxd->rxd_bufsize = V_RDES1_BUF1SIZE(1520) | ctrl; 458 rxd->rxd_bufaddr1 = PTR_TO_PCI(pkt->buffer); 459 rxd->rxd_bufaddr2 = 0; 460 rxd->rxd_flags = M_RDES0_OWNADAP; 461 462 /* success, advance the pointer */ 463 sc->rxdscr_add = nextrxd; 464 465 return 0; 466} 467 468static void 469tulip_fillrxring(tulip_softc *sc) 470{ 471 eth_pkt_t *pkt; 472 473 CS_ENTER(sc); 474 while (1) { 475 if (sc->rxdscr_onring >= MINRXRING) { 476 CS_EXIT(sc); 477 break; 478 } 479 CS_EXIT(sc); 480 pkt = eth_alloc_pkt(sc); 481 if (pkt == NULL) { 482 /* could not allocate a buffer */ 483 break; 484 } 485 if (tulip_add_rcvbuf(sc, pkt) != 0) { 486 /* could not add buffer to ring */ 487 eth_free_pkt(sc, pkt); 488 break; 489 } 490 CS_ENTER(sc); 491 sc->rxdscr_onring++; 492 } 493} 494 495 496/* ********************************************************************* 497 * TULIP_RX_CALLBACK(sc, pkt) 498 * 499 * Receive callback routine. This routine is invoked when a 500 * buffer queued for receives is filled. In this simple driver, 501 * all we do is add the packet to a per-MAC queue for later 502 * processing, and try to put a new packet in the place of the one 503 * that was removed from the queue. 504 * 505 * Input parameters: 506 * sc - interface 507 * ptk - packet context (eth_pkt structure) 508 * 509 * Return value: 510 * nothing 511 ********************************************************************* */ 512static void 513tulip_rx_callback(tulip_softc *sc, eth_pkt_t *pkt) 514{ 515 if (TULIP_DEBUG) show_packet('>', pkt); /* debug */ 516 517 CS_ENTER(sc); 518 q_enqueue(&sc->rxqueue, &pkt->next); 519 CS_EXIT(sc); 520 sc->inpkts++; 521} 522 523 524static void 525tulip_procrxring(tulip_softc *sc) 526{ 527 volatile rx_dscr *rxd; 528 eth_pkt_t *pkt; 529 eth_pkt_t *newpkt; 530 uint32_t flags; 531 532 for (;;) { 533 rxd = sc->rxdscr_remove; 534 535 flags = rxd->rxd_flags; 536 if (flags & M_RDES0_OWNADAP) { 537 /* end of ring, no more packets */ 538 break; 539 } 540 541 pkt = ETH_PKT_BASE(PCI_TO_PTR(rxd->rxd_bufaddr1)); 542 543 /* Drop error packets */ 544 if (flags & M_RDES0_ERRORSUM) { 545 xprintf("%s: rx error %04X\n", tulip_devname(sc), flags & 0xFFFF); 546 newpkt = pkt; /* recycle the buffer */ 547 } 548 else { 549 /* Pass up the packet */ 550 pkt->length = G_RDES0_FRAMELEN(flags) - ENET_CRC_SIZE; 551 tulip_rx_callback(sc, pkt); 552 553 /* put a buffer back on the ring to replace this one */ 554 newpkt = eth_alloc_pkt(sc); 555 } 556 557 /* update the pointer, accounting for buffer wrap. */ 558 rxd++; 559 if (rxd == sc->rxdscr_end) 560 rxd = sc->rxdscr_start; 561 sc->rxdscr_remove = rxd; 562 563 if (newpkt) { 564 /* The ring must have space now. */ 565 tulip_add_rcvbuf(sc, newpkt); 566 } 567 else { 568 CS_ENTER(sc); 569 sc->rxdscr_onring--; 570 CS_EXIT(sc); 571 } 572 } 573} 574 575 576static int 577tulip_add_txbuf(tulip_softc *sc, eth_pkt_t *pkt) 578{ 579 volatile tx_dscr *txd; 580 volatile tx_dscr *nexttxd; 581 uint32_t bufsize = 0; 582 583 txd = sc->txdscr_add; 584 585 /* Figure out where the next descriptor will go */ 586 nexttxd = (txd+1); 587 if (nexttxd == sc->txdscr_end) { 588 nexttxd = sc->txdscr_start; 589 bufsize = M_TDES1_ENDOFRING; 590 } 591 592 /* If the next one is the same as our remove pointer, 593 the ring is considered full. (it actually has room for 594 one more, but we reserve the remove == add case for "empty") */ 595 596 if (nexttxd == sc->txdscr_remove) return -1; 597 598 bufsize |= V_TDES1_BUF1SIZE(pkt->length) | 599 M_TDES1_FIRSTSEG | M_TDES1_LASTSEG | M_TDES1_INTERRUPT; 600 if (pkt->flags & ETH_TX_SETUP) { 601 /* For a setup packet, FIRSTSEG and LASTSEG should be clear (!) */ 602 bufsize ^= M_TDES1_SETUP | M_TDES1_FIRSTSEG | M_TDES1_LASTSEG; 603 } 604 txd->txd_bufsize = bufsize; 605 txd->txd_bufaddr1 = PTR_TO_PCI(pkt->buffer); 606 txd->txd_bufaddr2 = 0; 607 txd->txd_flags = M_TDES0_OWNADAP; 608 609 /* success, advance the pointer */ 610 sc->txdscr_add = nexttxd; 611 612 return 0; 613} 614 615 616static int 617tulip_transmit(tulip_softc *sc,eth_pkt_t *pkt) 618{ 619 int rv; 620 621 if (TULIP_DEBUG) show_packet('<', pkt); /* debug */ 622 623 rv = tulip_add_txbuf(sc, pkt); 624 sc->outpkts++; 625 626 WRITECSR(sc, R_CSR_TXPOLL, 1); 627 return rv; 628} 629 630 631static void 632tulip_proctxring(tulip_softc *sc) 633{ 634 volatile tx_dscr *txd; 635 eth_pkt_t *pkt; 636 uint32_t flags; 637 638 for (;;) { 639 txd = sc->txdscr_remove; 640 641 if (txd == sc->txdscr_add) { 642 /* ring is empty, no buffers to process */ 643 break; 644 } 645 646 flags = txd->txd_flags; 647 if (flags & M_TDES0_OWNADAP) { 648 /* Reached a packet still being transmitted */ 649 break; 650 } 651 652 /* Check for a completed setup packet */ 653 pkt = ETH_PKT_BASE(PCI_TO_PTR(txd->txd_bufaddr1)); 654 if (pkt->flags & ETH_TX_SETUP) { 655 if (sc->state == eth_state_setup) { 656 uint32_t opmode; 657 658 /* check flag bits */ 659 opmode = READCSR(sc, R_CSR_OPMODE); 660 opmode |= M_CSR6_RXSTART; 661 WRITECSR(sc, R_CSR_OPMODE, opmode); 662 sc->inpkts = sc->outpkts = 0; 663 sc->state = eth_state_on; 664 } 665 pkt->flags &=~ ETH_TX_SETUP; 666 } 667 668 /* Just free the packet */ 669 eth_free_pkt(sc, pkt); 670 671 /* update the pointer, accounting for buffer wrap. */ 672 txd++; 673 if (txd == sc->txdscr_end) 674 txd = sc->txdscr_start; 675 676 sc->txdscr_remove = txd; 677 } 678} 679 680 681static void 682tulip_initrings(tulip_softc *sc) 683{ 684 volatile tx_dscr *txd; 685 volatile rx_dscr *rxd; 686 687 /* Claim ownership of all descriptors for the driver */ 688 689 for (txd = sc->txdscr_start; txd != sc->txdscr_end; txd++) 690 txd->txd_flags = 0; 691 for (rxd = sc->rxdscr_start; rxd != sc->rxdscr_end; rxd++) 692 rxd->rxd_flags = 0; 693 694 /* Init the ring pointers */ 695 696 sc->txdscr_add = sc->txdscr_remove = sc->txdscr_start; 697 sc->rxdscr_add = sc->rxdscr_remove = sc->rxdscr_start; 698 sc->rxdscr_onring = 0; 699 700 /* Add stuff to the receive ring */ 701 702 tulip_fillrxring(sc); 703} 704 705 706/* Allocate an integral number of cache lines suitable for DMA access. */ 707static uint8_t * 708dma_alloc(size_t size, unsigned int align) 709{ 710 uint8_t *base; 711 size_t len = ALIGN(size, CACHE_ALIGN); 712 713 base = KMALLOC(len, ALIGN(align, CACHE_ALIGN)); 714 if (base != NULL) { 715 CACHE_DMA_INVAL(base, len); 716 } 717 return base; 718} 719 720static int 721tulip_init(tulip_softc *sc) 722{ 723 /* Allocate descriptor rings */ 724 sc->rxdscrmem = CACHE_DMA_SHARED(dma_alloc(MAXRXDSCR*sizeof(rx_dscr), CACHE_ALIGN)); 725 sc->txdscrmem = CACHE_DMA_SHARED(dma_alloc(MAXTXDSCR*sizeof(tx_dscr), CACHE_ALIGN)); 726 727 /* Allocate buffer pool */ 728 sc->pktpool = dma_alloc(ETH_PKTPOOL_SIZE*ETH_PKTBUF_SIZE, CACHE_ALIGN); 729 eth_initfreelist(sc); 730 q_init(&sc->rxqueue); 731 732 /* Fill in pointers to the rings */ 733 sc->rxdscr_start = (volatile rx_dscr *) (sc->rxdscrmem); 734 sc->rxdscr_end = sc->rxdscr_start + MAXRXDSCR; 735 sc->rxdscr_add = sc->rxdscr_start; 736 sc->rxdscr_remove = sc->rxdscr_start; 737 sc->rxdscr_onring = 0; 738 739 sc->txdscr_start = (volatile tx_dscr *) (sc->txdscrmem); 740 sc->txdscr_end = sc->txdscr_start + MAXTXDSCR; 741 sc->txdscr_add = sc->txdscr_start; 742 sc->txdscr_remove = sc->txdscr_start; 743 744 tulip_initrings(sc); 745 746 return 0; 747} 748 749 750static void 751tulip_resetrings(tulip_softc *sc) 752{ 753 volatile tx_dscr *txd; 754 volatile rx_dscr *rxd; 755 eth_pkt_t *pkt; 756 757 /* Free already-sent descriptors and buffers */ 758 tulip_proctxring(sc); 759 760 /* Free any pending but unsent */ 761 txd = sc->txdscr_remove; 762 while (txd != sc->txdscr_add) { 763 txd->txd_flags &=~ M_TDES0_OWNADAP; 764 pkt = ETH_PKT_BASE(PCI_TO_PTR(txd->txd_bufaddr1)); 765 eth_free_pkt(sc, pkt); 766 767 txd++; 768 if (txd == sc->txdscr_end) 769 txd = sc->txdscr_start; 770 } 771 sc->txdscr_add = sc->txdscr_remove; 772 773 /* Discard any received packets as well as all free buffers */ 774 rxd = sc->rxdscr_remove; 775 while (rxd != sc->rxdscr_add) { 776 rxd->rxd_flags &=~ M_RDES0_OWNADAP; 777 pkt = ETH_PKT_BASE(PCI_TO_PTR(rxd->rxd_bufaddr1)); 778 eth_free_pkt(sc, pkt); 779 780 rxd++; 781 if (rxd == sc->rxdscr_end) 782 rxd = sc->rxdscr_start; 783 CS_ENTER(sc); 784 sc->rxdscr_onring--; 785 CS_EXIT(sc); 786 } 787 788 /* Reestablish the initial state. */ 789 tulip_initrings(sc); 790} 791 792 793/* CRCs */ 794 795static uint32_t 796tulip_crc32(const uint8_t *databuf, unsigned int datalen) 797{ 798 unsigned int idx, bit, data; 799 uint32_t crc; 800 801 crc = 0xFFFFFFFFUL; 802 for (idx = 0; idx < datalen; idx++) 803 for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1) 804 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? ENET_CRC32_POLY : 0); 805 return crc; 806} 807 808#define tulip_mchash(mca) (tulip_crc32((mca), 6) & 0x1FF) 809 810 811/* Serial ROM access */ 812 813/* 814 * Delays below (nsec) are chosen to meet specs for NS93C64 (slow M variant). 815 * Current parts are faster. 816 * Reference: NS Memory Data Book, 1994 817 */ 818 819#define SROM_SIZE 128 820#define SROM_MAX_CYCLES 32 821 822#define SROM_CMD_BITS 3 823#define SROM_ADDR_BITS 6 824 825#define K_SROM_READ_CMD 06 826#define K_SROM_WRITE_CMD 05 827#define K_SROM_WEN_CMD 04 /* WEN, WDS, also WRAL, ERAL */ 828 829#define SROM_VENDOR_INDEX 0x00 830#define SROM_FORMAT_INDEX 0x12 831#define SROM_ADDR_INDEX 0x14 832 833#define SROM_DEVICE0_INDEX 0x1A 834#define SROM_LEAF0_OFFSET_INDEX 0x1B 835 836#define SROM_CRC_INDEX (SROM_SIZE-2) 837/* Note recent chips supporting wake-on-lan have CRC in bytes 94, 95 */ 838 839#define SROM_WORD(rom,offset) ((rom)[offset] | ((rom)[offset+1] << 8)) 840 841static void 842srom_idle_state(tulip_softc *sc) 843{ 844 uint32_t csr9; 845 unsigned int i; 846 847 csr9 = READCSR(sc, R_CSR_ROM_MII); 848 849 csr9 |= M_CSR9_SROMCHIPSEL; 850 WRITECSR(sc, R_CSR_ROM_MII, csr9); 851 cfe_nsleep(100); /* CS setup (Tcss=100) */ 852 853 /* Run the clock through the maximum number of pending read cycles */ 854 for (i = 0; i < SROM_MAX_CYCLES*2; i++) { 855 csr9 ^= M_CSR9_SROMCLOCK; 856 WRITECSR(sc, R_CSR_ROM_MII, csr9); 857 cfe_nsleep(1000); /* SK period (Fsk=0.5MHz) */ 858 } 859 860 /* Deassert SROM Chip Select */ 861 csr9 &=~ M_CSR9_SROMCHIPSEL; 862 WRITECSR(sc, R_CSR_ROM_MII, csr9); 863 cfe_nsleep(50); /* CS recovery (Tsks=50) */ 864} 865 866static void 867srom_write_bit(tulip_softc *sc, unsigned int data) 868{ 869 uint32_t csr9; 870 871 csr9 = READCSR(sc, R_CSR_ROM_MII); 872 873 /* Place the data bit on the bus */ 874 if (data == 1) 875 csr9 |= M_CSR9_SROMDATAIN; 876 else 877 csr9 &=~ M_CSR9_SROMDATAIN; 878 879 WRITECSR(sc, R_CSR_ROM_MII, csr9); 880 cfe_nsleep(360); /* setup: Tdis=200 */ 881 882 /* Now clock the data into the SROM */ 883 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK); 884 cfe_nsleep(900); /* clock high, Tskh=500 */ 885 WRITECSR(sc, R_CSR_ROM_MII, csr9); 886 cfe_nsleep(450); /* clock low, Tskl=250 */ 887 888 /* Now clear the data bit */ 889 csr9 &=~ M_CSR9_SROMDATAIN; /* data invalid, Tidh=20 for SK^ */ 890 WRITECSR(sc, R_CSR_ROM_MII, csr9); 891 cfe_nsleep(270); /* min cycle, 1/Fsk=2000 */ 892} 893 894static uint16_t 895srom_read_bit(tulip_softc *sc) 896{ 897 uint32_t csr9; 898 899 csr9 = READCSR(sc, R_CSR_ROM_MII); 900 901 /* Generate a clock cycle before doing a read */ 902 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK); /* rising edge */ 903 cfe_nsleep(1000); /* clock high, Tskh=500, Tpd=1000 */ 904 WRITECSR(sc, R_CSR_ROM_MII, csr9); /* falling edge */ 905 cfe_nsleep(1000); /* clock low, 1/Fsk=2000 */ 906 907 csr9 = READCSR(sc, R_CSR_ROM_MII); 908 return ((csr9 & M_CSR9_SROMDATAOUT) != 0 ? 1 : 0); 909} 910 911#define CMD_BIT_MASK (1 << (SROM_CMD_BITS+SROM_ADDR_BITS-1)) 912 913static uint16_t 914srom_read_word(tulip_softc *sc, unsigned int index) 915{ 916 uint16_t command, word; 917 uint32_t csr9; 918 unsigned int i; 919 920 csr9 = READCSR(sc, R_CSR_ROM_MII) | M_CSR9_SROMCHIPSEL; 921 922 /* Assert the SROM CS line */ 923 WRITECSR(sc, R_CSR_ROM_MII, csr9); 924 cfe_nsleep(100); /* CS setup, Tcss = 100 */ 925 926 /* Send the read command to the SROM */ 927 command = (K_SROM_READ_CMD << SROM_ADDR_BITS) | index; 928 for (i = 0; i < SROM_CMD_BITS+SROM_ADDR_BITS; i++) { 929 srom_write_bit(sc, (command & CMD_BIT_MASK) != 0 ? 1 : 0); 930 command <<= 1; 931 } 932 933 /* Now read the bits from the SROM (MSB first) */ 934 word = 0; 935 for (i = 0; i < 16; ++i) { 936 word <<= 1; 937 word |= srom_read_bit(sc); 938 } 939 940 /* Clear the SROM CS Line, CS hold, Tcsh = 0 */ 941 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL); 942 943 return word; 944} 945 946 947/**************************************************************************** 948 * srom_calc_crc() 949 * 950 * Calculate the CRC of the SROM and return it. We compute the 951 * CRC per Appendix A of the 21140A ROM/external register data 952 * sheet (EC-QPQWA-TE). 953 ***************************************************************************/ 954 955static uint16_t 956srom_calc_crc(tulip_softc *sc, uint8_t srom[], int length) 957{ 958 uint32_t crc = tulip_crc32(srom, length) ^ 0xFFFFFFFF; 959 960 return (uint16_t)(crc & 0xFFFF); 961} 962 963/**************************************************************************** 964 * srom_read_all(sc, uint8_t dest) 965 * 966 * Read the entire SROM into the srom array 967 * 968 * Input parameters: 969 * sc - tulip state 970 ***************************************************************************/ 971 972static int 973srom_read_all(tulip_softc *sc, uint8_t dest[]) 974{ 975 int i; 976 uint16_t crc, temp; 977 978 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMREAD); 979 980 srom_idle_state(sc); 981 982 for (i = 0; i < SROM_SIZE/2; i++) { 983 temp = srom_read_word(sc, i); 984 dest[2*i] = temp & 0xFF; 985 dest[2*i+1] =temp >> 8; 986 } 987 988 WRITECSR(sc, R_CSR_ROM_MII, 0); /* CS hold, Tcsh=0 */ 989 990 crc = srom_calc_crc(sc, dest, SROM_CRC_INDEX); 991 if (crc != SROM_WORD(dest, SROM_CRC_INDEX)) { 992 crc = srom_calc_crc(sc, dest, 94); /* "alternative" */ 993 if (crc != SROM_WORD(dest, 94)) { 994 xprintf("%s: Invalid SROM CRC, calc %04x, stored %04x\n", 995 tulip_devname(sc), crc, SROM_WORD(dest, 94)); 996 return 0/*-1*/; 997 } 998 } 999 return 0; 1000} 1001 1002static int 1003srom_read_addr(tulip_softc *sc, uint8_t buf[]) 1004{ 1005 uint8_t srom[SROM_SIZE]; 1006 1007 if (srom_read_all(sc, srom) == 0) { 1008 memcpy(buf, &srom[SROM_ADDR_INDEX], ENET_ADDR_LEN); 1009 return 0; 1010 } 1011 1012 return -1; 1013} 1014 1015 1016/**************************************************************************** 1017 * earom_read_all(sc, uint8_t dest) 1018 * 1019 * Read the entire Ethernet address ROM into the srom array (21040 only) 1020 * 1021 * Input parameters: 1022 * sc - tulip state 1023 ***************************************************************************/ 1024 1025static int 1026earom_read_all(tulip_softc *sc, uint8_t dest[]) 1027{ 1028 int i; 1029 uint32_t csr9; 1030 1031 WRITECSR(sc, R_CSR_ROM_MII, 0); /* reset pointer */ 1032 1033 for (i = 0; i < SROM_SIZE; i++) { 1034 for (;;) { 1035 csr9 = READCSR(sc, R_CSR_ROM_MII); 1036 if ((csr9 & M_CSR9_DATANOTVALID) == 0) 1037 break; 1038 POLL(); /* XXX need a timeout */ 1039 } 1040 dest[i] = G_CSR9_ROMDATA(csr9); 1041 } 1042 1043 return 0; 1044} 1045 1046static int 1047earom_read_addr(tulip_softc *sc, uint8_t buf[]) 1048{ 1049 uint8_t srom[SROM_SIZE]; 1050 1051 if (earom_read_all(sc, srom) == 0) { 1052 memcpy(buf, &srom[0], ENET_ADDR_LEN); 1053 return 0; 1054 } 1055 1056 return -1; 1057} 1058 1059 1060static int 1061rom_read_all(tulip_softc *sc, uint8_t buf[]) 1062{ 1063 if (sc->device == K_PCI_ID_DC21040) 1064 return earom_read_all(sc, buf); 1065 else 1066 return srom_read_all(sc, buf); 1067} 1068 1069static int 1070rom_read_addr(tulip_softc *sc, uint8_t buf[]) 1071{ 1072 if (sc->device == K_PCI_ID_DC21040) 1073 return earom_read_addr(sc, buf); 1074 else 1075 return srom_read_addr(sc, buf); 1076} 1077 1078#if 0 1079static void 1080rom_dump(uint8_t srom[]) 1081{ 1082 int i; 1083 1084 xprintf("DC21x4x: SROM data:"); 1085 for (i = 0; i < SROM_SIZE; i++) { 1086 if (i % 16 == 0) 1087 xprintf("\n %02x: ", i); 1088 xprintf(" %02x", srom[i]); 1089 } 1090 xprintf("\n"); 1091} 1092#else 1093#define rom_dump(srom) 1094#endif 1095 1096 1097/**************************************************************************** 1098 * MII access utility routines 1099 ***************************************************************************/ 1100 1101/* MII clock limited to 2.5 MHz, transactions end with MDIO tristated */ 1102 1103static void 1104mii_write_bits(tulip_softc *sc, uint32_t data, unsigned int count) 1105{ 1106 uint32_t csr9; 1107 uint32_t bitmask; 1108 1109 csr9 = READCSR(sc, R_CSR_ROM_MII) &~ (M_CSR9_MDC | M_CSR9_MIIMODE); 1110 1111 for (bitmask = 1 << (count-1); bitmask != 0; bitmask >>= 1) { 1112 csr9 &=~ M_CSR9_MDO; 1113 if ((data & bitmask) != 0) csr9 |= M_CSR9_MDO; 1114 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1115 1116 cfe_nsleep(2000); /* setup */ 1117 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC); 1118 cfe_nsleep(2000); /* hold */ 1119 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1120 } 1121} 1122 1123static void 1124mii_turnaround(tulip_softc *sc) 1125{ 1126 uint32_t csr9; 1127 1128 csr9 = READCSR(sc, R_CSR_ROM_MII) | M_CSR9_MIIMODE; 1129 1130 /* stop driving data */ 1131 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1132 cfe_nsleep(2000); /* setup */ 1133 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC); 1134 cfe_nsleep(2000); /* clock high */ 1135 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1136 1137 /* read back and check for 0 here? */ 1138} 1139 1140/**************************************************************************** 1141 * mii_read_register 1142 * 1143 * This routine reads a register from the PHY chip using the MII 1144 * serial management interface. 1145 * 1146 * Input parameters: 1147 * index - index of register to read (0-31) 1148 * 1149 * Return value: 1150 * word read from register 1151 ***************************************************************************/ 1152 1153static uint16_t 1154mii_read_register(tulip_softc *sc, unsigned int index) 1155{ 1156 /* Send the command and address to the PHY. The sequence is 1157 a synchronization sequence (32 1 bits) 1158 a "start" command (2 bits) 1159 a "read" command (2 bits) 1160 the PHY addr (5 bits) 1161 the register index (5 bits) 1162 */ 1163 uint32_t csr9; 1164 uint16_t word; 1165 int i; 1166 1167 mii_write_bits(sc, 0xFF, 8); 1168 mii_write_bits(sc, 0xFFFFFFFF, 32); 1169 mii_write_bits(sc, MII_COMMAND_START, 2); 1170 mii_write_bits(sc, MII_COMMAND_READ, 2); 1171 mii_write_bits(sc, sc->phy_addr, 5); 1172 mii_write_bits(sc, index, 5); 1173 1174 mii_turnaround(sc); 1175 1176 csr9 = (READCSR(sc, R_CSR_ROM_MII) &~ M_CSR9_MDC) | M_CSR9_MIIMODE; 1177 word = 0; 1178 1179 for (i = 0; i < 16; i++) { 1180 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1181 cfe_nsleep(2000); /* clock width low */ 1182 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC); 1183 cfe_nsleep(2000); /* clock width high */ 1184 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1185 cfe_nsleep(1000); /* output delay */ 1186 word <<= 1; 1187 if ((READCSR(sc, R_CSR_ROM_MII) & M_CSR9_MDI) != 0) 1188 word |= 0x0001; 1189 } 1190 1191 return word; 1192 1193 /* reset to output mode? */ 1194} 1195 1196/**************************************************************************** 1197 * mii_write_register 1198 * 1199 * This routine writes a register in the PHY chip using the MII 1200 * serial management interface. 1201 * 1202 * Input parameters: 1203 * index - index of register to write (0-31) 1204 * value - word to write 1205 ***************************************************************************/ 1206 1207static void 1208mii_write_register(tulip_softc *sc, unsigned int index, uint16_t value) 1209{ 1210 mii_write_bits(sc, 0xFF, 8); 1211 mii_write_bits(sc, 0xFFFFFFFF, 32); 1212 mii_write_bits(sc, MII_COMMAND_START, 2); 1213 mii_write_bits(sc, MII_COMMAND_WRITE, 2); 1214 mii_write_bits(sc, sc->phy_addr, 5); 1215 mii_write_bits(sc, index, 5); 1216 mii_write_bits(sc, MII_COMMAND_ACK, 2); 1217 mii_write_bits(sc, value, 16); 1218 1219 /* reset to input mode? */ 1220} 1221 1222 1223static int 1224mii_probe(tulip_softc *sc) 1225{ 1226 int i; 1227 uint16_t id1, id2; 1228 1229 for (i = 0; i < 32; i++) { 1230 sc->phy_addr = i; 1231 id1 = mii_read_register(sc, MII_PHYIDR1); 1232 id2 = mii_read_register(sc, MII_PHYIDR2); 1233 if ((id1 != 0x0000 && id1 != 0xFFFF) || 1234 (id2 != 0x0000 && id2 != 0xFFFF)) { 1235 sc->phy_vendor = ((uint32_t)id1 << 6) | ((id2 >> 10) & 0x3F); 1236 sc->phy_device = (id2 >> 4) & 0x3F; 1237 return 0; 1238 } 1239 } 1240 return -1; 1241} 1242 1243#if 0 1244static void 1245mii_dump(tulip_softc *sc, const char *label) 1246{ 1247 int i; 1248 uint16_t r; 1249 1250 xprintf("%s\n", label); 1251 for (i = 0; i <= 6; ++i) { 1252 r = mii_read_register(sc, i); 1253 xprintf("MII_REG%02x: %04x\n", i, r); 1254 } 1255 if (sc->phy_vendor == OUI_NAT_SEMI) { /* DP83840, DP83840A */ 1256 for (i = 0x15; i <= 0x19; ++i) { 1257 r = mii_read_register(sc, i); 1258 if (r != 0) xprintf("MII_REG%02x: %04x\n", i, r); 1259 } 1260 } 1261 else if (sc->phy_vendor == OUI_LEVEL_ONE) { /* LXT970, etc. */ 1262 for (i = 0x10; i <= 0x14; ++i) { 1263 r = mii_read_register(sc, i); 1264 if (r != 0) xprintf("MII_REG%02x: %04x\n", i, r); 1265 } 1266 } 1267 xprintf("OUI: %08x, Part %02x\n", sc->phy_vendor, sc->phy_device); 1268} 1269#else 1270#define mii_dump(sc,label) 1271#endif 1272 1273 1274/* The following functions are suitable for all tulips with MII 1275 interfaces. */ 1276 1277static void 1278mii_set_speed(tulip_softc *sc, int speed, int autoneg) 1279{ 1280 uint16_t control; 1281 uint32_t opmode = 0; 1282 1283 if (sc->phy_vendor == OUI_NAT_SEMI && sc->phy_device == DEV_DP83840) { 1284 uint16_t pcr; 1285 1286 /* Work-around for NS DP83840/A from ???. Needed? */ 1287 pcr = mii_read_register(sc, 0x17); 1288 pcr |= (0x400|0x100|0x40|0x20); 1289 mii_write_register(sc, 0x17, pcr); 1290 } 1291 1292 control = mii_read_register(sc, MII_BMCR); 1293 1294 if (!autoneg) { 1295 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1296 mii_write_register(sc, MII_BMCR, control); 1297 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX); 1298 } 1299 1300 switch (speed) { 1301 case ETHER_SPEED_10HDX: 1302 default: 1303 opmode = M_CSR6_SPEED_10_MII; 1304 break; 1305 case ETHER_SPEED_10FDX: 1306 control |= BMCR_DUPLEX; 1307 opmode = M_CSR6_SPEED_10_MII | M_CSR6_FULLDUPLEX; 1308 break; 1309 case ETHER_SPEED_100HDX: 1310 control |= BMCR_SPEED100; 1311 opmode = M_CSR6_SPEED_100_MII; 1312 break; 1313 case ETHER_SPEED_100FDX: 1314 control |= BMCR_SPEED100 | BMCR_DUPLEX ; 1315 opmode = M_CSR6_SPEED_100_MII | M_CSR6_FULLDUPLEX; 1316 break; 1317 } 1318 1319 if (!autoneg) 1320 mii_write_register(sc, MII_BMCR, control); 1321 1322 opmode |= M_CSR6_MBO; 1323 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 1324 WRITECSR(sc, R_CSR_OPMODE, opmode); 1325 mii_dump(sc, "setspeed PHY"); 1326} 1327 1328static void 1329mii_autonegotiate(tulip_softc *sc) 1330{ 1331 uint16_t control, status, cap; 1332 unsigned int timeout; 1333 int linkspeed; 1334 int autoneg; 1335 1336 linkspeed = ETHER_SPEED_UNKNOWN; 1337 1338 /* Read twice to clear latching bits */ 1339 status = mii_read_register(sc, MII_BMSR); 1340 status = mii_read_register(sc, MII_BMSR); 1341 mii_dump(sc, "query PHY"); 1342 1343 if ((status & (BMSR_AUTONEG | BMSR_LINKSTAT)) == 1344 (BMSR_AUTONEG | BMSR_LINKSTAT)) 1345 control = mii_read_register(sc, MII_BMCR); 1346 else { 1347 /* reset the PHY */ 1348 mii_write_register(sc, MII_BMCR, BMCR_RESET); 1349 timeout = 3000; 1350 for (;;) { 1351 control = mii_read_register(sc, MII_BMCR); 1352 if ((control && BMCR_RESET) == 0) break; 1353 cfe_sleep(CFE_HZ/2); 1354 timeout -= 500; 1355 if (timeout <= 0) break; 1356 } 1357 if ((control & BMCR_RESET) != 0) { 1358 xprintf("%s: PHY reset failed\n", tulip_devname(sc)); 1359 return; 1360 } 1361 1362 status = mii_read_register(sc, MII_BMSR); 1363 cap = ((status >> 6) & (ANAR_TXFD | ANAR_TXHD | ANAR_10FD | ANAR_10HD)) 1364 | PSB_802_3; 1365 mii_write_register(sc, MII_ANAR, cap); 1366 control |= (BMCR_ANENABLE | BMCR_RESTARTAN); 1367 mii_write_register(sc, MII_BMCR, control); 1368 1369 timeout = 3000; 1370 for (;;) { 1371 status = mii_read_register(sc, MII_BMSR); 1372 if ((status & BMSR_ANCOMPLETE) != 0) break; 1373 cfe_sleep(CFE_HZ/2); 1374 timeout -= 500; 1375 if (timeout <= 0) break; 1376 } 1377 mii_dump(sc, "done PHY"); 1378 } 1379 1380 xprintf("%s: Link speed: ", tulip_devname(sc)); 1381 if ((status & BMSR_ANCOMPLETE) != 0) { 1382 /* A link partner was negogiated... */ 1383 1384 uint16_t remote = mii_read_register(sc, MII_ANLPAR); 1385 1386 autoneg = 1; 1387 if ((remote & ANLPAR_TXFD) != 0) { 1388 xprintf("100BaseT FDX"); 1389 linkspeed = ETHER_SPEED_100FDX; 1390 } 1391 else if ((remote & ANLPAR_TXHD) != 0) { 1392 xprintf("100BaseT HDX"); 1393 linkspeed = ETHER_SPEED_100HDX; 1394 } 1395 else if ((remote & ANLPAR_10FD) != 0) { 1396 xprintf("10BaseT FDX"); 1397 linkspeed = ETHER_SPEED_10FDX; 1398 } 1399 else if ((remote & ANLPAR_10HD) != 0) { 1400 xprintf("10BaseT HDX"); 1401 linkspeed = ETHER_SPEED_10HDX; 1402 } 1403 xprintf("\n"); 1404 } 1405 else { 1406 /* no link partner negotiation */ 1407 1408 autoneg = 0; 1409 xprintf("Unknown, assuming 10BaseT\n"); 1410 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1411 mii_write_register(sc, MII_BMCR, control); 1412 linkspeed = ETHER_SPEED_10HDX; 1413 } 1414 1415 if ((status & BMSR_LINKSTAT) == 0) 1416 mii_write_register(sc, MII_BMCR, control); 1417 mii_set_speed(sc, linkspeed, autoneg); 1418 1419 status = mii_read_register(sc, MII_BMSR); /* clear latching bits */ 1420 mii_dump(sc, "final PHY"); 1421} 1422 1423 1424/* Chip specific code */ 1425 1426/* For the 21140 and 21143, we support only the MII (10/100) and SYM 1427 (100) interfaces. We attempt to discover the appropriate interface 1428 and port settings by scanning the vendor ROMs, but some are 1429 sufficiently confused or quirky to require special case code. */ 1430 1431/* Known vendors with cards requiring special initialization. */ 1432#define K_PCI_VENDOR_COGENT 0x1109 /* inherited by Adaptec */ 1433#define K_PCI_VENDOR_ZNYX 0x110D 1434#define K_PCI_VENDOR_PHOBOS 0x13D8 1435 1436static void 1437dc21143_set_speed(tulip_softc *sc, int speed) 1438{ 1439 uint32_t opmode = 0; 1440 1441 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1442 1443 switch (speed) { 1444 case ETHER_SPEED_AUTO: 1445 break; 1446 case ETHER_SPEED_10HDX: 1447 default: 1448 WRITECSR(sc, R_CSR_SIAMODE1, M_CSR14_10BT_HD); 1449 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1450 opmode = M_CSR6_SPEED_10; 1451 break; 1452 case ETHER_SPEED_10FDX: 1453 WRITECSR(sc, R_CSR_SIAMODE1, M_CSR14_10BT_FD); 1454 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1455 opmode = M_CSR6_SPEED_10 | M_CSR6_FULLDUPLEX; 1456 break; 1457 case ETHER_SPEED_100HDX: 1458 WRITECSR(sc, R_CSR_SIAMODE1, 0); 1459 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1460 opmode = M_CSR6_SPEED_100; 1461 break; 1462 case ETHER_SPEED_100FDX: 1463 WRITECSR(sc, R_CSR_SIAMODE1, 0); 1464 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1465 opmode = M_CSR6_SPEED_100 | M_CSR6_FULLDUPLEX; 1466 break; 1467 } 1468 1469 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1470 1471 opmode |= M_CSR6_MBO; 1472 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 1473 WRITECSR(sc, R_CSR_OPMODE, opmode); 1474} 1475 1476static void 1477dc21143_autonegotiate(tulip_softc *sc) 1478{ 1479 uint32_t opmode; 1480 uint32_t tempword; 1481 int count; 1482 int linkspeed; 1483 1484 linkspeed = ETHER_SPEED_UNKNOWN; 1485 1486 /* Program the media setup into the CSRs. */ 1487 /* reset SIA */ 1488 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1489 1490 /* set to speed_10, fullduplex to start_nway */ 1491 opmode = 1492 M_CSR6_SPEED_10 | 1493 M_CSR6_FULLDUPLEX | 1494 M_CSR6_MBO; 1495 WRITECSR(sc, R_CSR_OPMODE, opmode); 1496 1497 /* Choose advertised capabilities */ 1498 tempword = 1499 M_CSR14_100BASETHALFDUP | 1500 M_CSR14_100BASETFULLDUP | 1501 M_CSR14_HALFDUPLEX10BASET; 1502 WRITECSR(sc, R_CSR_SIAMODE1, tempword); 1503 1504 /* Enable autonegotiation */ 1505 tempword |= M_CSR14_AUTONEGOTIATE | 0xFFFF; 1506 WRITECSR(sc, R_CSR_SIAMODE1, tempword); 1507 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1508 WRITECSR(sc, R_CSR_OPMODE, opmode); 1509 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1510 1511 /* STATE check nway, poll until a valid 10/100mbs signal seen */ 1512 WRITECSR(sc, R_CSR_STATUS, M_CSR5_LINKPASS); /* try to clear this... */ 1513 1514 /* (Re)start negotiation */ 1515 tempword = READCSR(sc, R_CSR_SIASTATUS); 1516 tempword &=~ M_CSR12_AUTONEGARBIT; 1517 tempword |= V_CSR12_AUTONEGARBIT(0x1); 1518 1519 for (count = 0; count <= 13; count++) { 1520 tempword = READCSR(sc, R_CSR_STATUS); 1521 if (tempword & M_CSR5_LINKPASS) 1522 break; 1523 cfe_sleep(CFE_HZ/10); 1524 } 1525 1526 if (count > 13) 1527 xprintf("%s: Link autonegotiation failed\n", tulip_devname(sc)); 1528 1529 /* STATE configure nway, check to see if any abilities common to us. 1530 If they do, set to highest mode, if not, we will see if the partner 1531 will do 100mb or 10mb - then set it */ 1532 1533 tempword = READCSR(sc, R_CSR_SIASTATUS); 1534 /* clear the autonegogiate complete bit */ 1535 WRITECSR(sc, R_CSR_STATUS, M_CSR5_LINKPASS); 1536 1537 if (tempword & M_CSR12_LINKPARTNEG) { 1538 /* A link partner was negogiated... */ 1539 1540 xprintf("%s: Link speed: ", tulip_devname(sc)); 1541 if (tempword & 0x01000000) { /* 100FD */ 1542 xprintf("100BaseT FDX"); 1543 linkspeed = ETHER_SPEED_100FDX; 1544 } 1545 else if (tempword & 0x00800000) { /* 100HD */ 1546 xprintf("100BaseT HDX"); 1547 linkspeed = ETHER_SPEED_100HDX; 1548 } 1549 else if (tempword & 0x00400000) { /* 10FD */ 1550 xprintf("10BaseT FDX"); 1551 linkspeed = ETHER_SPEED_10FDX; 1552 } 1553 else if (tempword & 0x00200000) { /* 10HD */ 1554 xprintf("10BaseT HDX"); 1555 linkspeed = ETHER_SPEED_10HDX; 1556 } 1557 xprintf("\n"); 1558 } 1559 else { 1560 /* no link partner negotiation */ 1561 /* disable link for 1.3 seconds to break any existing connections */ 1562 1563 xprintf("%s: ", tulip_devname(sc)); 1564 dc21143_set_speed(sc, ETHER_SPEED_10HDX); 1565 cfe_sleep(CFE_HZ/8); 1566 1567 tempword = READCSR(sc, R_CSR_SIASTATUS); 1568 1569 if ((tempword & 0x02) == 0) { 1570 /* 100 mb signal present set to 100mb */ 1571 xprintf("No link partner... setting to 100BaseT HDX\n"); 1572 linkspeed = ETHER_SPEED_100HDX; 1573 } 1574 else if ((tempword & 0x04) == 0) { 1575 /* 10 mb signal present */ 1576 xprintf("No link partner... setting to 10BaseT HDX\n"); 1577 linkspeed = ETHER_SPEED_10HDX; 1578 } 1579 else { 1580 /* couldn't determine line speed, so set to 10mbs */ 1581 xprintf("Unknown; defaulting to 10BaseT HDX\n"); 1582 linkspeed = ETHER_SPEED_10HDX; 1583 } 1584 } 1585 1586 dc21143_set_speed(sc, linkspeed); 1587} 1588 1589static void 1590dc21143_set_loopback(tulip_softc *sc, int mode) 1591{ 1592 uint32_t v; 1593 1594 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1595 if (mode == ETHER_LOOPBACK_EXT) { 1596 /* deal with CSRs 13-15 */ 1597 } 1598 cfe_sleep(CFE_HZ/10); /* check this */ 1599 1600 /* Update the SIA registers */ 1601 v = READCSR(sc, R_CSR_SIAMODE0); 1602 WRITECSR(sc, R_CSR_SIAMODE0, v &~ 0xFFFF); 1603 v = READCSR(sc, R_CSR_SIAMODE1); 1604 WRITECSR(sc, R_CSR_SIAMODE1, v &~ 0xFFFF); 1605 v = READCSR(sc, R_CSR_SIAMODE2); 1606 WRITECSR(sc, R_CSR_SIAMODE2, v | 0xC000); /* WC of HCKR, RMP */ 1607 if (mode == ETHER_LOOPBACK_OFF) 1608 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1609 else 1610 WRITECSR(sc, R_CSR_SIAMODE2, (v &~ 0xFFFF) | M_CSR15_GP_AUIBNC); 1611 1612 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1613 1614 sc->loopback = mode; 1615} 1616 1617static void 1618dc21143_hwinit(tulip_softc *sc, uint8_t srom[]) 1619{ 1620 uint16_t vendor; 1621 uint16_t leaf, block, info; 1622 uint8_t i; 1623 uint16_t gpr_control; 1624 uint32_t v; 1625 uint32_t csr6word, csr14word; 1626 1627 vendor = SROM_WORD(srom, SROM_VENDOR_INDEX); 1628 sc->phy_type = NONE; 1629 info = 0; 1630 1631 if (srom[SROM_FORMAT_INDEX] != 0 || srom[SROM_FORMAT_INDEX] <= 4) { 1632 leaf = SROM_WORD(srom, SROM_LEAF0_OFFSET_INDEX); 1633 block = leaf + 3; 1634 1635 /* Note that blocks are arranged by increasing preference. */ 1636 for (i = 0; i < srom[leaf+2]; i++) { 1637 switch (srom[block+1]) { 1638 case 0x03: 1639 sc->phy_type = MII; 1640 info = block; 1641 break; 1642 case 0x04: 1643 sc->phy_type = SYM; 1644 info = block; 1645 break; 1646 } 1647 block += (srom[block+0] & 0x7F); 1648 } 1649 } 1650 1651 if (sc->phy_type == MII) { 1652 sc->gpdata = 0; 1653 if (vendor == K_PCI_VENDOR_COGENT) { 1654 /* Cogent/Adaptec MII (ANA-6911A). */ 1655 WRITECSR(sc, R_CSR_SIAMODE2, 0x0821 << 16); 1656 WRITECSR(sc, R_CSR_SIAMODE2, 0x0001 << 16); 1657 cfe_sleep(CFE_HZ/10); 1658 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000 << 16); 1659 cfe_sleep(CFE_HZ/2); 1660 sc->gpdata = 0; 1661 } 1662 else if (vendor == K_PCI_VENDOR_PHOBOS) { 1663 /* Phobos 430TX quad card. The advertised values appear 1664 not to work. Note that Phobos also neglects to set the 1665 0x80 bit on the block length. */ 1666#if 0 /* per EEPROM */ 1667 WRITECSR(sc, R_CSR_SIAMODE2, 0x080E << 16); 1668 WRITECSR(sc, R_CSR_SIAMODE2, 0x000E << 16); 1669 cfe_sleep(CFE_HZ/10); 1670 sc->gpdata = 0x0E; 1671#else /* following Adaptec 21143 with MII interface */ 1672 WRITECSR(sc, R_CSR_SIAMODE2, 0x0821 << 16); 1673 WRITECSR(sc, R_CSR_SIAMODE2, 0x0001 << 16); 1674 cfe_sleep(CFE_HZ/10); 1675 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000 << 16); 1676 cfe_sleep(CFE_HZ/2); 1677 sc->gpdata = 0; 1678#endif 1679 } 1680 mii_probe(sc); 1681 } 1682 else if (sc->phy_type == SYM) { 1683 gpr_control = SROM_WORD(srom, info+3) << 16; 1684 if (vendor == K_PCI_VENDOR_ZNYX) { 1685 /* Znyz 34xQ family of adapters */ 1686 1687 /* The ZX345Q with wake-on-LAN enabled apparently clears 1688 ANE and TAS on power up (but not cold reset) */ 1689 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFFFFFF); 1690 1691 /* The following is a reset workaround for QS/Kendin PHYs 1692 as suggested by an Intel app note. Bit 0x40000 is the 1693 PHY reset (low true) on Znyx cards. */ 1694 WRITECSR(sc, R_CSR_SIAMODE2, gpr_control | M_CSR15_GP_AUIBNC); 1695 cfe_sleep(CFE_HZ/5); 1696 WRITECSR(sc, R_CSR_SIAMODE2, 0x40000); /* release reset */ 1697 cfe_sleep(CFE_HZ/5); 1698 sc->gpdata = 0x40000; 1699 } 1700 else { 1701 WRITECSR(sc, R_CSR_SIAMODE2, gpr_control); 1702 sc->gpdata = 0; 1703 } 1704 sc->gpdata |= (SROM_WORD(srom, info+5) << 16) | M_CSR15_GP_AUIBNC; 1705 } 1706 else { 1707 /* Most 21143 cards use SYM. Match the DEC reference design. */ 1708 sc->phy_type = SYM; 1709 WRITECSR(sc, R_CSR_SIAMODE2, M_CSR15_CONFIG_GEPS_LEDS); 1710 sc->gpdata = M_CSR15_DEFAULT_VALUE; 1711 } 1712 1713 /* CSR0 - bus mode */ 1714 v = V_CSR0_SKIPLEN(0) | 1715 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 1716 M_CSR0_READMULTENAB | M_CSR0_READLINEENAB | 1717 M_CSR0_WRITEINVALENAB | 1718 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 1719#if ENDIAN_BIG 1720 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 1721#endif 1722 WRITECSR(sc, R_CSR_BUSMODE, v); 1723 1724 /* CSR6 - operation mode */ 1725 v = M_CSR6_PORTSEL | 1726 V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72) | 1727 M_CSR6_MBO; 1728 if (sc->phy_type == SYM) 1729 v |= M_CSR6_PCSFUNC |M_CSR6_SCRAMMODE; 1730 WRITECSR(sc, R_CSR_OPMODE, v); 1731 1732 /* About to muck with the SIA, reset it.(?) */ 1733 /* WRITECSR(sc, R_CSR_SIASTATUS, 0); */ 1734 1735 /* Must shut off all transmit/receive in order to attempt to 1736 achieve Full Duplex */ 1737 csr6word = READCSR(sc, R_CSR_OPMODE); 1738 WRITECSR(sc, R_CSR_OPMODE, csr6word &~ (M_CSR6_TXSTART | M_CSR6_RXSTART)); 1739 csr6word = READCSR(sc, R_CSR_OPMODE); 1740 1741 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc->rxdscr_start)); 1742 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc->txdscr_start)); 1743 1744 if (sc->phy_type == MII) { 1745 if (sc->linkspeed == ETHER_SPEED_AUTO) 1746 mii_autonegotiate(sc); 1747 else 1748 mii_set_speed(sc, sc->linkspeed, 0); 1749 } 1750 else { 1751 if (sc->linkspeed == ETHER_SPEED_AUTO) { 1752 dc21143_autonegotiate(sc); 1753 } 1754 else { 1755 /* disable autonegotiate so we can set full duplex to on */ 1756 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1757 csr14word = READCSR(sc, R_CSR_SIAMODE1); 1758 csr14word &=~ M_CSR14_AUTONEGOTIATE; 1759 WRITECSR(sc, R_CSR_SIAMODE1, csr14word); 1760 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1761 1762 dc21143_set_speed(sc, sc->linkspeed); 1763 } 1764 } 1765} 1766 1767 1768static void 1769dc21140_set_speed(tulip_softc *sc, int speed, int autoneg) 1770{ 1771 mii_set_speed(sc, speed, autoneg); 1772} 1773 1774static void 1775dc21140_set_loopback(tulip_softc *sc, int mode) 1776{ 1777 if (mode == ETHER_LOOPBACK_EXT) { 1778 xprintf("%s: external loopback mode NYI\n", tulip_devname(sc)); 1779 mode = ETHER_LOOPBACK_OFF; 1780 } 1781 else if (mode != ETHER_LOOPBACK_INT) 1782 mode = ETHER_LOOPBACK_OFF; 1783 1784 sc->loopback = mode; 1785} 1786 1787static void 1788dc21140_hwinit(tulip_softc *sc, uint8_t srom[]) 1789{ 1790 uint16_t vendor; 1791 uint16_t leaf, block; 1792 uint8_t i; 1793 uint8_t gpr_control, gpr_data; 1794 uint32_t v; 1795 uint32_t opmode; 1796 1797 /* Assume that we will use an MII or a SYM interface for 100 Mbps 1798 operation and default to MII, the most common arrangement for 1799 21140 boards. */ 1800 1801 vendor = SROM_WORD(srom, SROM_VENDOR_INDEX); 1802 if (srom[SROM_FORMAT_INDEX] == 0 || srom[SROM_FORMAT_INDEX] > 4) { 1803 /* Most 21140 cards use MII. Match the DEC reference design. */ 1804 gpr_control = 0x1F; 1805 gpr_data = 0x00; 1806 sc->phy_type = MII; 1807 } 1808 else if (srom[SROM_ADDR_INDEX+0] == 0x00 && srom[SROM_ADDR_INDEX+1] == 0xC0 1809 && srom[SROM_ADDR_INDEX+2] == 0x95) { 1810 /* Znyx 34x 21140 cards implement only an MII interface but 1811 the ROM uses version 1 encoding, which has no provision for 1812 MII blocks. Also, an additional copy of the MAC address 1813 appears at the usual location for the vendor id; 00-C0-95 1814 is Znyx' IEEE OUI. */ 1815 gpr_control = 0x00; /* All inputs, per Znyx docs */ 1816 gpr_data = 0x00; 1817 sc->phy_type = MII; 1818 } 1819 else { 1820 leaf = SROM_WORD(srom, SROM_LEAF0_OFFSET_INDEX); 1821 gpr_control = srom[leaf+2]; 1822 gpr_data = 0; 1823 block = leaf + 4; 1824 sc->phy_type = NONE; 1825 1826 /* Note that blocks are arranged by increasing preference. */ 1827 for (i = 0; i < srom[leaf+3]; i++) { 1828 if ((srom[block] & 0x80) == 0) { 1829 if (srom[block] == 0x03 || srom[block] == 0x05) { 1830 gpr_data = srom[block+1]; 1831 sc->phy_type = SYM; 1832 } 1833 block += 4; 1834 } 1835 else { 1836 if (srom[block+1] == 0x01) { 1837 gpr_data = 0x00; 1838 sc->phy_type = MII; 1839 } 1840 else if (srom[block+1] == 0x00 && 1841 (srom[block+2] == 0x03 || srom[block+2] == 0x05)) { 1842 gpr_data = srom[block+3]; 1843 sc->phy_type = SYM; 1844 } 1845 block += (srom[block] & 0x7F) + 1; 1846 } 1847 if (sc->phy_type == NONE) { 1848 sc->phy_type = MII; /* Try MII */ 1849 } 1850 } 1851 } 1852 1853 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL); 1854 RESET_ADAPTER(sc); 1855 1856 WRITECSR(sc, R_CSR_GENPORT, M_CSR12_CONTROL | gpr_control); 1857 cfe_nsleep(100); /* CS setup (Tcss=100) */ 1858 WRITECSR(sc, R_CSR_GENPORT, gpr_data); /* setup PHY */ 1859 1860 if (sc->phy_type == MII) { 1861 mii_probe(sc); 1862 } 1863 1864 /* CSR0 - bus mode */ 1865 v = V_CSR0_SKIPLEN(0) | 1866 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 1867 M_CSR0_READMULTENAB | M_CSR0_READLINEENAB | 1868 M_CSR0_WRITEINVALENAB | 1869 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 1870#if ENDIAN_BIG 1871 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 1872#endif 1873 WRITECSR(sc, R_CSR_BUSMODE, v); 1874 1875 /* CSR6 - operation mode */ 1876 v = M_CSR6_PORTSEL | 1877 V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72) | 1878 M_CSR6_MBO; 1879 WRITECSR(sc, R_CSR_OPMODE, v); 1880 1881 /* Must shut off all transmit/receive in order to attempt to 1882 achieve Full Duplex */ 1883 opmode = READCSR(sc, R_CSR_OPMODE); 1884 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART)); 1885 opmode = READCSR(sc, R_CSR_OPMODE); 1886 1887 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc->rxdscr_start)); 1888 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc->txdscr_start)); 1889 1890 if (sc->phy_type == MII) { 1891 if (sc->linkspeed == ETHER_SPEED_AUTO) 1892 mii_autonegotiate(sc); 1893 else 1894 mii_set_speed(sc, sc->linkspeed, 0); 1895 } 1896 else { 1897 /* XXX The 21140 requires a soft reset after changing PORTSEL. 1898 For now, remain committed to the SYM port (100 Mb/s) */ 1899 switch (sc->linkspeed) { 1900 default: 1901 sc->linkspeed = ETHER_SPEED_100HDX; /* for now */ 1902 /* fall through */ 1903 case ETHER_SPEED_100HDX: 1904 opmode |= M_CSR6_SPEED_100; 1905 break; 1906 case ETHER_SPEED_100FDX: 1907 opmode |= M_CSR6_SPEED_100 | M_CSR6_FULLDUPLEX; 1908 break; 1909 } 1910 1911 /* XXX Need to reset and reinitialize if we choose SPEED_10 above */ 1912 WRITECSR(sc, R_CSR_OPMODE, opmode); 1913 } 1914} 1915 1916 1917static void 1918dc21041_set_speed(tulip_softc *sc, int speed) 1919{ 1920 uint32_t opmode = 0; 1921 1922 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1923 1924 /* For now, always force 10BT, HDX (21041, Table 3-62) */ 1925 switch (speed) { 1926 case ETHER_SPEED_10HDX: 1927 default: 1928 WRITECSR(sc, R_CSR_SIAMODE1, 0x7F3F); 1929 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 1930 opmode = M_CSR6_SPEED_10; 1931 break; 1932 } 1933 1934 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | M_CSR13_CONN_NOT_RESET); 1935 cfe_sleep(CFE_HZ/10); 1936 1937 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 1938 WRITECSR(sc, R_CSR_OPMODE, opmode); 1939} 1940 1941static void 1942dc21041_set_loopback(tulip_softc *sc, int mode) 1943{ 1944 /* For now, always assume 10BT */ 1945 uint32_t mode0; 1946 1947 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1948 cfe_sleep(CFE_HZ/10); /* check this */ 1949 1950 /* Update the SIA registers */ 1951 if (mode == ETHER_LOOPBACK_EXT) { 1952 /* NB: this is really just internal but through the 10BT endec */ 1953 WRITECSR(sc, R_CSR_SIAMODE1, 0x7A3F); 1954 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 1955 mode0 = 0; 1956 } 1957 else if (mode == ETHER_LOOPBACK_INT) { 1958 /* MAC internal loopback, no SIA */ 1959 WRITECSR(sc, R_CSR_SIAMODE1, 0x0000); 1960 WRITECSR(sc, R_CSR_SIAMODE2, 0x000E); 1961 mode0 = M_CSR13_CONN_AUI_10BT; 1962 } 1963 else { 1964 mode = ETHER_LOOPBACK_OFF; 1965 WRITECSR(sc, R_CSR_SIAMODE1, 0x7F3F); 1966 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 1967 mode0 = 0; 1968 } 1969 1970 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | mode0 | M_CSR13_CONN_NOT_RESET ); 1971 1972 sc->loopback = mode; 1973} 1974 1975static void 1976dc21041_hwinit(tulip_softc *sc, uint8_t srom[]) 1977{ 1978 uint32_t v; 1979 1980 sc->phy_type = SRL; 1981 1982 /* CSR0 - bus mode */ 1983 v = V_CSR0_SKIPLEN(0) | 1984 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 1985 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 1986#if ENDIAN_BIG 1987 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 1988#endif 1989 WRITECSR(sc, R_CSR_BUSMODE, v); 1990 1991 WRITECSR(sc, R_CSR_INTMASK, 0); 1992 1993 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc->rxdscr_start)); 1994 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc->txdscr_start)); 1995 1996 /* For now, always force 10BT, HDX (21041, Table 3-62) */ 1997 dc21041_set_speed(sc, ETHER_SPEED_10HDX); 1998} 1999 2000 2001static void 2002dc21040_set_speed(tulip_softc *sc, int speed) 2003{ 2004 uint32_t opmode = 0; 2005 2006 WRITECSR(sc, R_CSR_SIAMODE0, 0); 2007 2008 /* For now, force 10BT, HDX unless FDX requested (21040, Table 3-53) */ 2009 switch (speed) { 2010 case ETHER_SPEED_10HDX: 2011 default: 2012 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFF); 2013 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2014 opmode = 0; 2015 break; 2016 case ETHER_SPEED_10FDX: 2017 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFD); 2018 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2019 opmode = M_CSR6_FULLDUPLEX; 2020 break; 2021 } 2022 2023 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | M_CSR13_CONN_NOT_RESET); 2024 cfe_sleep(CFE_HZ/10); 2025 2026 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 2027 WRITECSR(sc, R_CSR_OPMODE, opmode); 2028} 2029 2030static void 2031dc21040_set_loopback(tulip_softc *sc, int mode) 2032{ 2033 WRITECSR(sc, R_CSR_SIAMODE0, 0); 2034 cfe_sleep(CFE_HZ/10); /* check this */ 2035 2036 /* Update the SIA registers */ 2037 if (mode == ETHER_LOOPBACK_EXT) { 2038 /* NB: this is on-chip loopback through the 10BT endec */ 2039 WRITECSR(sc, R_CSR_SIAMODE1, 0xFEFB); 2040 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 2041 } 2042 else if (mode == ETHER_LOOPBACK_INT) { 2043 /* MAC internal loopback, no SIA */ 2044 WRITECSR(sc, R_CSR_SIAMODE1, 0x0000); 2045 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2046 } 2047 else { 2048 mode = ETHER_LOOPBACK_OFF; 2049 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFF); 2050 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2051 } 2052 2053 WRITECSR(sc, R_CSR_SIAMODE0, 0x8F00 | M_CSR13_CONN_NOT_RESET ); 2054 2055 sc->loopback = mode; 2056} 2057 2058static void 2059dc21040_hwinit(tulip_softc *sc, uint8_t srom[]) 2060{ 2061 uint32_t v; 2062 2063 sc->phy_type = SRL; 2064 2065 /* CSR0 - bus mode */ 2066 v = V_CSR0_SKIPLEN(0) | 2067 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 2068 V_CSR0_BURSTLEN(K_CSR0_BURST32); 2069#if ENDIAN_BIG 2070 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 2071#endif 2072 WRITECSR(sc, R_CSR_BUSMODE, v); 2073 2074 WRITECSR(sc, R_CSR_INTMASK, 0); 2075 2076 dc21040_set_speed(sc, sc->linkspeed); 2077} 2078 2079 2080static void 2081tulip_hwinit(tulip_softc *sc) 2082{ 2083 if (sc->state == eth_state_uninit) { 2084 uint8_t srom[SROM_SIZE]; 2085 2086 /* Wake-on-LAN apparently powers up with PORTSEL = 1 */ 2087 WRITECSR(sc, R_CSR_OPMODE, 2088 READCSR(sc, R_CSR_OPMODE) &~ M_CSR6_PORTSEL); 2089 2090 RESET_ADAPTER(sc); 2091 sc->state = eth_state_off; 2092 sc->bus_errors = 0; 2093 2094 rom_read_all(sc, srom); /* XXX read just once? */ 2095 rom_dump(srom); 2096 2097 switch (sc->device) { 2098 case K_PCI_ID_DC21040: 2099 dc21040_hwinit(sc, srom); 2100 break; 2101 case K_PCI_ID_DC21041: 2102 dc21041_hwinit(sc, srom); 2103 break; 2104 case K_PCI_ID_DC21140: 2105 dc21140_hwinit(sc, srom); 2106 break; 2107 case K_PCI_ID_DC21143: 2108 dc21143_hwinit(sc, srom); 2109 break; 2110 default: 2111 break; 2112 } 2113 } 2114} 2115 2116static void 2117tulip_setaddr(tulip_softc *sc) 2118{ 2119 int idx; 2120 tulip_cam *cam; 2121 eth_pkt_t *pkt; 2122 2123 pkt = eth_alloc_pkt(sc); 2124 if (pkt) { 2125 pkt->length = CAM_SETUP_BUFFER_SIZE; 2126 cam = (tulip_cam *) pkt->buffer; 2127 2128#if ENDIAN_BIG 2129 cam->p.physical[0][0] = (((uint32_t) sc->hwaddr[0] << 8) | 2130 (uint32_t) sc->hwaddr[1]) << 16; 2131 cam->p.physical[0][1] = (((uint32_t) sc->hwaddr[2] << 8) | 2132 (uint32_t) sc->hwaddr[3]) << 16; 2133 cam->p.physical[0][2] = (((uint32_t) sc->hwaddr[4] << 8) | 2134 (uint32_t) sc->hwaddr[5]) << 16; 2135 for (idx = 1; idx < CAM_PERFECT_ENTRIES; idx++) { 2136 cam->p.physical[idx][0] = 0xFFFF0000; 2137 cam->p.physical[idx][1] = 0xFFFF0000; 2138 cam->p.physical[idx][2] = 0xFFFF0000; 2139 } 2140#else 2141 cam->p.physical[0][0] = ((uint32_t) sc->hwaddr[0]) | 2142 (((uint32_t) sc->hwaddr[1]) << 8); 2143 cam->p.physical[0][1] = ((uint32_t) sc->hwaddr[2]) | 2144 (((uint32_t) sc->hwaddr[3]) << 8); 2145 cam->p.physical[0][2] = ((uint32_t) sc->hwaddr[4]) | 2146 (((uint32_t) sc->hwaddr[5]) << 8); 2147 for (idx = 1; idx < CAM_PERFECT_ENTRIES; idx++) { 2148 cam->p.physical[idx][0] = 0x0000FFFF; 2149 cam->p.physical[idx][1] = 0x0000FFFF; 2150 cam->p.physical[idx][2] = 0x0000FFFF; 2151 } 2152#endif 2153 2154 pkt->flags |= ETH_TX_SETUP; 2155 sc->state = eth_state_setup; 2156 2157 CACHE_DMA_SYNC(pkt->buffer, pkt->length); 2158 if (tulip_transmit(sc, pkt) != 0) { 2159 xprintf("%s: failed setup\n", tulip_devname(sc)); 2160 dumpstat(sc); 2161 eth_free_pkt(sc, pkt); 2162 } 2163 } 2164} 2165 2166static void 2167tulip_setspeed(tulip_softc *sc, int speed) 2168{ 2169 switch (sc->device) { 2170 case K_PCI_ID_DC21040: 2171 dc21040_set_speed(sc, speed); 2172 break; 2173 case K_PCI_ID_DC21041: 2174 dc21041_set_speed(sc, speed); 2175 break; 2176 case K_PCI_ID_DC21140: 2177 dc21140_set_speed(sc, speed, 0); 2178 break; 2179 case K_PCI_ID_DC21143: 2180 dc21143_set_speed(sc, speed); 2181 break; 2182 default: 2183 break; 2184 } 2185} 2186 2187static void 2188tulip_setloopback(tulip_softc *sc, int mode) 2189{ 2190 switch (sc->device) { 2191 case K_PCI_ID_DC21040: 2192 dc21040_set_loopback(sc, mode); 2193 break; 2194 case K_PCI_ID_DC21041: 2195 dc21041_set_loopback(sc, mode); 2196 break; 2197 case K_PCI_ID_DC21140: 2198 dc21140_set_loopback(sc, mode); 2199 break; 2200 case K_PCI_ID_DC21143: 2201 dc21143_set_loopback(sc, mode); 2202 break; 2203 default: 2204 break; 2205 } 2206 cfe_sleep(CFE_HZ/10); 2207} 2208 2209 2210static void 2211tulip_isr(void *arg) 2212{ 2213 uint32_t status; 2214 uint32_t csr5; 2215 tulip_softc *sc = (tulip_softc *)arg; 2216 2217#if IPOLL 2218 sc->interrupts++; 2219#endif 2220 2221 for (;;) { 2222 2223 /* Read the interrupt status. */ 2224 csr5 = READCSR(sc, R_CSR_STATUS); 2225 status = csr5 & ( 2226 M_CSR5_RXINT | M_CSR5_RXBUFUNAVAIL | 2227 M_CSR5_TXINT | M_CSR5_TXUNDERFLOW | 2228 M_CSR5_FATALBUSERROR); 2229 2230 /* if there are no more interrupts, leave now. */ 2231 if (status == 0) break; 2232 2233 /* Clear the pending interrupt. */ 2234 WRITECSR(sc, R_CSR_STATUS, status); 2235 2236 /* Now, test each unmasked bit in the interrupt register and 2237 handle each interrupt type appropriately. */ 2238 2239 if (status & M_CSR5_FATALBUSERROR) { 2240 WRITECSR(sc, R_CSR_INTMASK, 0); 2241 2242 xprintf("%s: bus error %02x\n", 2243 tulip_devname(sc), G_CSR5_ERRORBITS(csr5)); 2244 dumpstat(sc); 2245 sc->bus_errors++; 2246 if (sc->bus_errors >= 2) { 2247 dumpcsrs(sc); 2248 RESET_ADAPTER(sc); 2249 sc->state = eth_state_off; 2250 sc->bus_errors = 0; 2251 } 2252#if IPOLL 2253 else 2254 WRITECSR(sc, R_CSR_INTMASK, sc->intmask); 2255#endif 2256 } 2257 2258 if (status & M_CSR5_RXINT) { 2259#if IPOLL 2260 sc->rx_interrupts++; 2261#endif 2262 tulip_procrxring(sc); 2263 } 2264 2265 if (status & M_CSR5_TXINT) { 2266#if IPOLL 2267 sc->tx_interrupts++; 2268#endif 2269 tulip_proctxring(sc); 2270 } 2271 2272 if (status & (M_CSR5_TXUNDERFLOW | M_CSR5_RXBUFUNAVAIL)) { 2273 if (status & M_CSR5_TXUNDERFLOW) { 2274 xprintf("%s: tx underrun, %08x\n", tulip_devname(sc), csr5); 2275 /* Try to restart */ 2276 WRITECSR(sc, R_CSR_TXPOLL, 1); 2277 } 2278 if (status & M_CSR5_RXBUFUNAVAIL) { 2279 /* Try to restart */ 2280 WRITECSR(sc, R_CSR_RXPOLL, 1); 2281 } 2282 } 2283 } 2284} 2285 2286 2287static void 2288tulip_start(tulip_softc *sc) 2289{ 2290 uint32_t opmode; 2291 2292 tulip_hwinit(sc); 2293 2294 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc->rxdscr_start)); 2295 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc->txdscr_start)); 2296 2297 opmode = READCSR(sc, R_CSR_OPMODE); 2298 opmode &=~ M_CSR6_OPMODE; /* no loopback */ 2299 if (sc->loopback != ETHER_LOOPBACK_OFF) { 2300 opmode &=~ M_CSR6_FULLDUPLEX; 2301 opmode |= M_CSR6_PORTSEL; 2302 if (sc->loopback == ETHER_LOOPBACK_EXT) 2303 opmode |= M_CSR6_EXTLOOPBACK; 2304 else 2305 opmode |= M_CSR6_INTLOOPBACK; 2306 } 2307 2308 sc->intmask = 0; 2309 WRITECSR(sc, R_CSR_INTMASK, 0); /* no interrupts */ 2310 WRITECSR(sc, R_CSR_STATUS, 0x1FFFF); /* clear any pending */ 2311 READCSR(sc, R_CSR_STATUS); /* push the write */ 2312 2313 sc->interrupts = 0; 2314 sc->rx_interrupts = sc->tx_interrupts = 0; 2315 2316#if IPOLL 2317 cfe_request_irq(sc->irq, tulip_isr, sc, CFE_IRQ_FLAGS_SHARED, 0); 2318 2319 sc->intmask = M_CSR7_RXINT | M_CSR7_TXINT | 2320 M_CSR7_NORMALINT; 2321 sc->intmask |= M_CSR7_FATALBUSERROR | M_CSR7_TXUNDERFLOW | 2322 M_CSR7_ABNORMALINT; 2323 WRITECSR(sc, R_CSR_INTMASK, sc->intmask); 2324#endif 2325 2326 if (sc->loopback == ETHER_LOOPBACK_OFF) { 2327 opmode |= M_CSR6_TXSTART; 2328 WRITECSR(sc, R_CSR_OPMODE, opmode); 2329 tulip_setaddr(sc); 2330 } 2331 else { 2332 opmode |= M_CSR6_TXSTART | M_CSR6_RXSTART; 2333 WRITECSR(sc, R_CSR_OPMODE, opmode); 2334 } 2335} 2336 2337static void 2338tulip_stop(tulip_softc *sc) 2339{ 2340 uint32_t opmode; 2341 uint32_t status; 2342 int count; 2343 2344 WRITECSR(sc, R_CSR_INTMASK, 0); 2345 sc->intmask = 0; 2346#if IPOLL 2347 cfe_free_irq(sc->irq, 0); 2348#endif 2349 WRITECSR(sc, R_CSR_STATUS, 0x1FFFF); 2350 opmode = READCSR(sc, R_CSR_OPMODE); 2351 opmode &=~ (M_CSR6_TXSTART | M_CSR6_RXSTART); 2352 WRITECSR(sc, R_CSR_OPMODE, opmode); 2353 2354 /* wait for any DMA activity to terminate */ 2355 for (count = 0; count <= 13; count++) { 2356 status = READCSR(sc, R_CSR_STATUS); 2357 if ((status & (M_CSR5_RXPROCSTATE | M_CSR5_TXPROCSTATE)) == 0) 2358 break; 2359 cfe_sleep(CFE_HZ/10); 2360 } 2361 if (count > 13) { 2362 xprintf("%s: idle state not achieved\n", tulip_devname(sc)); 2363 dumpstat(sc); 2364 RESET_ADAPTER(sc); 2365 sc->state = eth_state_uninit; 2366#if 1 2367 sc->linkspeed = ETHER_SPEED_AUTO; 2368#endif 2369 } 2370 else if (sc->loopback != ETHER_LOOPBACK_OFF) { 2371 tulip_setloopback(sc, ETHER_LOOPBACK_OFF); 2372 opmode &=~ M_CSR6_OPMODE; 2373 WRITECSR(sc, R_CSR_OPMODE, opmode); 2374 } 2375 2376 if (sc->outpkts > 1) { 2377 /* heuristic: suppress stats for initial mode changes */ 2378 xprintf("%s: %d sent, %d received, %d interrupts\n", 2379 tulip_devname(sc), sc->outpkts, sc->inpkts, sc->interrupts); 2380 if (IPOLL) { 2381 xprintf(" %d rx interrupts, %d tx interrupts\n", 2382 sc->rx_interrupts, sc->tx_interrupts); 2383 } 2384 } 2385} 2386 2387 2388/* ********************************************************************* 2389 * Declarations for CFE Device Driver Interface routines 2390 ********************************************************************* */ 2391 2392static int tulip_ether_open(cfe_devctx_t *ctx); 2393static int tulip_ether_read(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 2394static int tulip_ether_inpstat(cfe_devctx_t *ctx,iocb_inpstat_t *inpstat); 2395static int tulip_ether_write(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 2396static int tulip_ether_ioctl(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 2397static int tulip_ether_close(cfe_devctx_t *ctx); 2398#if 0 2399static void tulip_ether_reset(void *softc); 2400#endif 2401 2402/* ********************************************************************* 2403 * CFE Device Driver dispatch structure 2404 ********************************************************************* */ 2405 2406const static cfe_devdisp_t tulip_ether_dispatch = { 2407 tulip_ether_open, 2408 tulip_ether_read, 2409 tulip_ether_inpstat, 2410 tulip_ether_write, 2411 tulip_ether_ioctl, 2412 tulip_ether_close, 2413 NULL, /* tulip_ether_poll */ 2414 NULL /* tulip_ether_reset */ 2415}; 2416 2417/* ********************************************************************* 2418 * CFE Device Driver descriptor 2419 ********************************************************************* */ 2420 2421const cfe_driver_t tulipdrv = { 2422 "DC21x4x Ethernet", 2423 "eth", 2424 CFE_DEV_NETWORK, 2425 &tulip_ether_dispatch, 2426 tulip_ether_probe 2427}; 2428 2429 2430static int 2431tulip_ether_attach(cfe_driver_t *drv, pcitag_t tag, uint8_t hwaddr[]) 2432{ 2433 tulip_softc *sc; 2434 uint32_t device; 2435 uint32_t class; 2436 uint32_t reg; 2437 phys_addr_t pa; 2438 const char *devname; 2439 char descr[100]; 2440 uint8_t romaddr[ENET_ADDR_LEN]; 2441 2442 device = pci_conf_read(tag, R_CFG_CFID); 2443 class = pci_conf_read(tag, R_CFG_CFRV); 2444 2445 reg = pci_conf_read(tag, R_CFG_CPMS); 2446 2447 reg = pci_conf_read(tag, R_CFG_CFDD); 2448 pci_conf_write(tag, R_CFG_CFDD, 0); 2449 reg = pci_conf_read(tag, R_CFG_CFDD); 2450 2451#if 1 2452 /* Use memory space for the CSRs */ 2453 pci_map_mem(tag, R_CFG_CBMA, PCI_MATCH_BITS, &pa); 2454#else 2455 /* Use i/o space for the CSRs */ 2456 pci_map_io(tag, R_CFG_CBIO, PCI_MATCH_BITS, &pa); 2457#endif 2458 2459 sc = (tulip_softc *) KMALLOC(sizeof(tulip_softc), 0); 2460 if (sc == NULL) { 2461 xprintf("DC21x4x: No memory to complete probe\n"); 2462 return 0; 2463 } 2464 memset(sc, 0, sizeof(*sc)); 2465 2466 sc->membase = (uint32_t)pa; 2467 sc->irq = pci_conf_read(tag, R_CFG_CFIT) & 0xFF; 2468 2469 sc->tag = tag; 2470 sc->device = PCI_PRODUCT(device); 2471 sc->revision = PCI_REVISION(class); 2472 sc->devctx = NULL; 2473 2474#if 1 2475 sc->linkspeed = ETHER_SPEED_AUTO; /* select autonegotiation */ 2476#else 2477 sc->linkspeed = ETHER_SPEED_100FDX; /* 100 Mbps, full duplex */ 2478#endif 2479 sc->loopback = ETHER_LOOPBACK_OFF; 2480 memcpy(sc->hwaddr, hwaddr, ENET_ADDR_LEN); 2481 2482 tulip_init(sc); 2483 2484 /* Prefer address in srom */ 2485 if (rom_read_addr(sc, romaddr) == 0) { 2486 memcpy(sc->hwaddr, romaddr, ENET_ADDR_LEN); 2487 } 2488 2489 sc->state = eth_state_uninit; 2490 2491 switch (sc->device) { 2492 case K_PCI_ID_DC21040: 2493 devname = "DC21040"; break; 2494 case K_PCI_ID_DC21041: 2495 devname = "DC21041"; break; 2496 case K_PCI_ID_DC21140: 2497 devname = "DC21140"; break; 2498 case K_PCI_ID_DC21143: 2499 devname = "DC21143"; break; 2500 default: 2501 devname = "DC21x4x"; break; 2502 } 2503 2504 xsprintf(descr, "%s Ethernet at 0x%X (%02X-%02X-%02X-%02X-%02X-%02X)", 2505 devname, sc->membase, 2506 sc->hwaddr[0], sc->hwaddr[1], sc->hwaddr[2], 2507 sc->hwaddr[3], sc->hwaddr[4], sc->hwaddr[5]); 2508 2509 cfe_attach(drv, sc, NULL, descr); 2510 return 1; 2511} 2512 2513 2514/* ********************************************************************* 2515 * TULIP_ETHER_PROBE(drv,probe_a,probe_b,probe_ptr) 2516 * 2517 * Probe and install drivers for all DC21x4x Ethernet controllers. 2518 * For each, create a context structure and attach to the 2519 * specified network device. 2520 * 2521 * Input parameters: 2522 * drv - driver descriptor 2523 * probe_a - not used 2524 * probe_b - not used 2525 * probe_ptr - string pointer to hardware address for the first 2526 * MAC, in the form xx:xx:xx:xx:xx:xx 2527 * 2528 * Return value: 2529 * nothing 2530 ********************************************************************* */ 2531static void 2532tulip_ether_probe(cfe_driver_t *drv, 2533 unsigned long probe_a, unsigned long probe_b, 2534 void *probe_ptr) 2535{ 2536 int index; 2537 uint8_t hwaddr[ENET_ADDR_LEN]; 2538 2539 if (probe_ptr) 2540 enet_parse_hwaddr((char *) probe_ptr, hwaddr); 2541 else { 2542 /* use default address 02-00-00-10-11-11 */ 2543 hwaddr[0] = 0x02; hwaddr[1] = 0x00; hwaddr[2] = 0x00; 2544 hwaddr[3] = 0x10; hwaddr[4] = 0x11; hwaddr[5] = 0x11; 2545 } 2546 2547 index = 0; 2548 for (;;) { 2549 pcitag_t tag; 2550 pcireg_t device; 2551 2552 if (pci_find_class(PCI_CLASS_NETWORK, index, &tag) != 0) 2553 break; 2554 2555 index++; 2556 2557 device = pci_conf_read(tag, R_CFG_CFID); 2558 if (PCI_VENDOR(device) == K_PCI_VENDOR_DEC) { 2559#if 0 /* this currently (2.1.1) generates a bad code in PIC mode */ 2560 switch (PCI_PRODUCT(device)) { 2561 case K_PCI_ID_DC21040: 2562 case K_PCI_ID_DC21041: 2563 case K_PCI_ID_DC21140: 2564 case K_PCI_ID_DC21143: 2565 tulip_ether_attach(drv, tag, hwaddr); 2566 enet_incr_hwaddr(hwaddr, 1); 2567 break; 2568 default: 2569 break; 2570 } 2571#else 2572 if (PCI_PRODUCT(device) == K_PCI_ID_DC21040 || 2573 PCI_PRODUCT(device) == K_PCI_ID_DC21041 || 2574 PCI_PRODUCT(device) == K_PCI_ID_DC21140 || 2575 PCI_PRODUCT(device) == K_PCI_ID_DC21143) { 2576 2577 tulip_ether_attach(drv, tag, hwaddr); 2578 enet_incr_hwaddr(hwaddr, 1); 2579 } 2580#endif 2581 } 2582 } 2583} 2584 2585 2586/* The functions below are called via the dispatch vector for the 21x4x. */ 2587 2588/* ********************************************************************* 2589 * TULIP_ETHER_OPEN(ctx) 2590 * 2591 * Open the Ethernet device. The MAC is reset, initialized, and 2592 * prepared to receive and send packets. 2593 * 2594 * Input parameters: 2595 * ctx - device context (includes ptr to our softc) 2596 * 2597 * Return value: 2598 * status, 0 = ok 2599 ********************************************************************* */ 2600static int 2601tulip_ether_open(cfe_devctx_t *ctx) 2602{ 2603 tulip_softc *sc = ctx->dev_softc; 2604 2605 if (sc->state == eth_state_on) 2606 tulip_stop(sc); 2607 2608 sc->devctx = ctx; 2609 tulip_start(sc); 2610 2611#if XPOLL 2612 tulip_isr(sc); 2613#endif 2614 2615 return 0; 2616} 2617 2618/* ********************************************************************* 2619 * TULIP_ETHER_READ(ctx,buffer) 2620 * 2621 * Read a packet from the Ethernet device. If no packets are 2622 * available, the read will succeed but return 0 bytes. 2623 * 2624 * Input parameters: 2625 * ctx - device context (includes ptr to our softc) 2626 * buffer - pointer to buffer descriptor. 2627 * 2628 * Return value: 2629 * status, 0 = ok 2630 ********************************************************************* */ 2631static int 2632tulip_ether_read(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 2633{ 2634 tulip_softc *sc = ctx->dev_softc; 2635 eth_pkt_t *pkt; 2636 int blen; 2637 2638#if XPOLL 2639 tulip_isr(sc); 2640#endif 2641 2642 if (sc->state != eth_state_on) return -1; 2643 2644 CS_ENTER(sc); 2645 pkt = (eth_pkt_t *) q_deqnext(&(sc->rxqueue)); 2646 CS_EXIT(sc); 2647 2648 if (pkt == NULL) { 2649 buffer->buf_retlen = 0; 2650 return 0; 2651 } 2652 2653 blen = buffer->buf_length; 2654 if (blen > pkt->length) blen = pkt->length; 2655 2656 CACHE_DMA_INVAL(pkt->buffer, blen); 2657 hs_memcpy_to_hs(buffer->buf_ptr, pkt->buffer, blen); 2658 buffer->buf_retlen = blen; 2659 2660 eth_free_pkt(sc, pkt); 2661 tulip_fillrxring(sc); 2662 2663#if XPOLL 2664 tulip_isr(sc); 2665#endif 2666 2667 return 0; 2668} 2669 2670/* ********************************************************************* 2671 * TULIP_ETHER_INPSTAT(ctx,inpstat) 2672 * 2673 * Check for received packets on the Ethernet device 2674 * 2675 * Input parameters: 2676 * ctx - device context (includes ptr to our softc) 2677 * inpstat - pointer to input status structure 2678 * 2679 * Return value: 2680 * status, 0 = ok 2681 ********************************************************************* */ 2682static int 2683tulip_ether_inpstat(cfe_devctx_t *ctx, iocb_inpstat_t *inpstat) 2684{ 2685 tulip_softc *sc = ctx->dev_softc; 2686 2687#if XPOLL 2688 tulip_isr(sc); 2689#endif 2690 2691 if (sc->state != eth_state_on) return -1; 2692 2693 /* We avoid an interlock here because the result is a hint and an 2694 interrupt cannot turn a non-empty queue into an empty one. */ 2695 inpstat->inp_status = (q_isempty(&(sc->rxqueue))) ? 0 : 1; 2696 2697 return 0; 2698} 2699 2700/* ********************************************************************* 2701 * TULIP_ETHER_WRITE(ctx,buffer) 2702 * 2703 * Write a packet to the Ethernet device. 2704 * 2705 * Input parameters: 2706 * ctx - device context (includes ptr to our softc) 2707 * buffer - pointer to buffer descriptor. 2708 * 2709 * Return value: 2710 * status, 0 = ok 2711 ********************************************************************* */ 2712static int 2713tulip_ether_write(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 2714{ 2715 tulip_softc *sc = ctx->dev_softc; 2716 eth_pkt_t *pkt; 2717 int blen; 2718 2719#if XPOLL 2720 tulip_isr(sc); 2721#endif 2722 2723 if (sc->state != eth_state_on) return -1; 2724 2725 pkt = eth_alloc_pkt(sc); 2726 if (!pkt) return CFE_ERR_NOMEM; 2727 2728 blen = buffer->buf_length; 2729 if (blen > pkt->length) blen = pkt->length; 2730 2731 hs_memcpy_from_hs(pkt->buffer, buffer->buf_ptr, blen); 2732 pkt->length = blen; 2733 2734 CACHE_DMA_SYNC(pkt->buffer, blen); 2735 if (tulip_transmit(sc, pkt) != 0) { 2736 eth_free_pkt(sc,pkt); 2737 return CFE_ERR_IOERR; 2738 } 2739 2740#if XPOLL 2741 tulip_isr(sc); 2742#endif 2743 2744 return 0; 2745} 2746 2747/* ********************************************************************* 2748 * TULIP_ETHER_IOCTL(ctx,buffer) 2749 * 2750 * Do device-specific I/O control operations for the device 2751 * 2752 * Input parameters: 2753 * ctx - device context (includes ptr to our softc) 2754 * buffer - pointer to buffer descriptor. 2755 * 2756 * Return value: 2757 * status, 0 = ok 2758 ********************************************************************* */ 2759static int 2760tulip_ether_ioctl(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 2761{ 2762 tulip_softc *sc = ctx->dev_softc; 2763 int mode; 2764 int speed; 2765 2766 switch ((int)buffer->buf_ioctlcmd) { 2767 case IOCTL_ETHER_GETHWADDR: 2768 hs_memcpy_to_hs(buffer->buf_ptr, sc->hwaddr, sizeof(sc->hwaddr)); 2769 return 0; 2770 2771 case IOCTL_ETHER_SETHWADDR: 2772 return -1; /* not supported */ 2773 2774 case IOCTL_ETHER_GETSPEED: 2775 mode = sc->linkspeed; 2776 hs_memcpy_to_hs(buffer->buf_ptr,&mode,sizeof(int)); 2777 return 0; 2778 2779 case IOCTL_ETHER_SETSPEED: 2780 tulip_stop(sc); 2781 tulip_resetrings(sc); 2782 hs_memcpy_from_hs(&speed,buffer->buf_ptr,sizeof(int)); 2783 tulip_setspeed(sc, speed); 2784 tulip_start(sc); 2785 sc->state = eth_state_on; 2786 return 0; 2787 2788 case IOCTL_ETHER_GETLINK: 2789 mode = sc->linkspeed; 2790 hs_memcpy_to_hs(buffer->buf_ptr,&mode,sizeof(int)); 2791 return 0; 2792 2793 case IOCTL_ETHER_GETLOOPBACK: 2794 mode = sc->loopback; 2795 hs_memcpy_to_hs(buffer->buf_ptr,&mode,sizeof(int)); 2796 return 0; 2797 2798 case IOCTL_ETHER_SETLOOPBACK: 2799 tulip_stop(sc); 2800 tulip_resetrings(sc); 2801 hs_memcpy_from_hs(&mode,buffer->buf_ptr,sizeof(int)); 2802 sc->loopback = ETHER_LOOPBACK_OFF; /* default */ 2803 if (mode == ETHER_LOOPBACK_INT || mode == ETHER_LOOPBACK_EXT) { 2804 tulip_setloopback(sc, mode); 2805 } 2806 tulip_start(sc); 2807 sc->state = eth_state_on; 2808 return 0; 2809 2810 default: 2811 return -1; 2812 } 2813} 2814 2815/* ********************************************************************* 2816 * TULIP_ETHER_CLOSE(ctx) 2817 * 2818 * Close the Ethernet device. 2819 * 2820 * Input parameters: 2821 * ctx - device context (includes ptr to our softc) 2822 * 2823 * Return value: 2824 * status, 0 = ok 2825 ********************************************************************* */ 2826static int 2827tulip_ether_close(cfe_devctx_t *ctx) 2828{ 2829 tulip_softc *sc = ctx->dev_softc; 2830 2831 sc->state = eth_state_off; 2832 tulip_stop(sc); 2833 2834 /* resynchronize descriptor rings */ 2835 tulip_resetrings(sc); 2836 2837 sc->devctx = NULL; 2838 return 0; 2839} 2840 2841 2842#if 0 2843/* ********************************************************************* 2844 * TULIP_ETHER_POLL(ctx,ticks) 2845 * 2846 * TBD 2847 * 2848 * Input parameters: 2849 * ctx - device context (includes ptr to our softc) 2850 * ticks- current time in ticks 2851 * 2852 * Return value: 2853 * nothing 2854 ********************************************************************* */ 2855 2856static void 2857tulip_ether_poll(cfe_devctx_t *ctx, int64_t ticks) 2858{ 2859} 2860 2861/* ********************************************************************* 2862 * TULIP_ETHER_RESET(softc) 2863 * 2864 * This routine is called when CFE is restarted after a 2865 * program exits. We can clean up pending I/Os here. 2866 * 2867 * Input parameters: 2868 * softc - pointer to tulip_softc 2869 * 2870 * Return value: 2871 * nothing 2872 ********************************************************************* */ 2873 2874static void 2875tulip_ether_reset(void *softc) 2876{ 2877 tulip_softc *sc = (tulip_softc *)softc; 2878 2879 /* Turn off the Ethernet interface. */ 2880 2881 RESET_ADAPTER(sc); 2882} 2883#endif 2884