1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * DC21x4x Ethernet Driver File: dev_tulip.c 5 * 6 * Author: Ed Satterthwaite 7 * 8 ********************************************************************* 9 * 10 * Copyright 2000,2001,2002,2003 11 * Broadcom Corporation. All rights reserved. 12 * 13 * This software is furnished under license and may be used and 14 * copied only in accordance with the following terms and 15 * conditions. Subject to these conditions, you may download, 16 * copy, install, use, modify and distribute modified or unmodified 17 * copies of this software in source and/or binary form. No title 18 * or ownership is transferred hereby. 19 * 20 * 1) Any source code used, modified or distributed must reproduce 21 * and retain this copyright notice and list of conditions 22 * as they appear in the source file. 23 * 24 * 2) No right is granted to use any trade name, trademark, or 25 * logo of Broadcom Corporation. The "Broadcom Corporation" 26 * name may not be used to endorse or promote products derived 27 * from this software without the prior written permission of 28 * Broadcom Corporation. 29 * 30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 42 * THE POSSIBILITY OF SUCH DAMAGE. 43 ********************************************************************* */ 44 45#include "cfe.h" 46#include "lib_physio.h" 47#ifdef CPUCFG_MEMCPY 48#error "this doesn't work yet." 49extern void *CPUCFG_MEMCPY(void *dest, const void *src, size_t cnt); 50#define blockcopy CPUCFG_MEMCPY 51#else 52#define blockcopy memcpy 53#endif 54 55#include "cfe_irq.h" 56 57#include "net_enet.h" 58 59#include "pcivar.h" 60#include "pcireg.h" 61 62#include "tulip.h" 63#include "mii.h" 64 65/* This is a driver for specific configurations of the DC21040, DC21041, 66 DC21140A and DC21143, not a generic Tulip driver. The prefix 67 "tulip_" is used to indicate generic Tulip functions, while 68 "dc21040_", "dc21041_", "dc21140_" or "dc21143_" indicates functions 69 specific to a chip variant. 70 71 The 21041 driver assumes a 10BT HD interface, since autonegotiation 72 is known to be broken in the early revisons of that chip. Example 73 cards come from DEC and SMC. Essentially the same driver is used 74 for 21040 cards. 75 76 The 21140 driver assumes that the PHY uses a standard MII interface 77 for both 100BT and 10BT. Example cards come from DEC (National DP83840 78 plus Twister PHY) and Netgear (Level One PHY). 79 80 Some early 21140 boards are exceptions and use SYM plus SRL 81 with different PHY chips for 10 and 100 (limited support). 82 83 The 21143 driver assumes by default that the PHY uses the SYM ("5 84 wire") interface for 100BT with pass-through for 10BT. Example 85 cards come from DEC (MicroLinear ML6694 PHY) and Znyx (QS6611 or 86 Kendin KS8761 PHY). It also supports an MII interface for 87 recognized adapters. An example card comes from Adaptec (National 88 DP83840A and Twister PHY). There is no support for AUI interfaces. 89 90 The Davicom 9102(A) is a chip with an integrated PHY that is almost 91 compatible with the 21140 and is in current production. 92 93 This SB1250 version takes advantage of DMA coherence and uses 94 "preserve bit lanes" addresses for all accesses that cross the 95 ZBbus-PCI bridge. */ 96 97#ifndef TULIP_DEBUG 98#define TULIP_DEBUG 0 99#endif 100 101#if ((ENDIAN_BIG + ENDIAN_LITTLE) != 1) 102#error "dev_tulip: system endian not set" 103#endif 104 105/* Temporary, until configs supply MATCH_BYTES */ 106#if defined(_MOUSSE_) || defined(_BCM98245CPCI_) /* any PPC */ 107#define MATCH_BYTES 1 108#else 109#define MATCH_BYTES 0 110#endif 111 112/* Set IPOLL to drive processing through the pseudo-interrupt 113 dispatcher. Set XPOLL to drive processing by an external polling 114 agent. Setting both is ok. */ 115 116#ifndef IPOLL 117#define IPOLL 0 118#endif 119#ifndef XPOLL 120#define XPOLL 1 121#endif 122 123#define MAX_ETHER_PACK (ENET_MAX_PKT+ENET_CRC_SIZE) /* size of max packet */ 124 125/* Packet buffers. For tulip, the packet must be aligned to a 32-bit 126 word boundary, and we would like it aligned to a cache line 127 boundary for performance. */ 128 129#define CACHE_ALIGN 32 130 131typedef struct eth_pkt_s { 132 queue_t next; /* 8 */ 133 uint8_t *buffer; /* 4 */ 134 uint32_t flags; /* 4 */ 135 int32_t length; /* 4 */ 136 uint32_t unused[3]; /* 12 */ 137 uint8_t data[MAX_ETHER_PACK]; 138} eth_pkt_t; 139 140#define ETH_PKTBUF_LINES ((sizeof(eth_pkt_t) + (CACHE_ALIGN-1))/CACHE_ALIGN) 141#define ETH_PKTBUF_SIZE (ETH_PKTBUF_LINES*CACHE_ALIGN) 142#define ETH_PKTBUF_OFFSET (offsetof(eth_pkt_t, data)) 143 144#define ETH_PKT_BASE(data) ((eth_pkt_t *)((data) - ETH_PKTBUF_OFFSET)) 145 146/* packet flags */ 147#define ETH_TX_SETUP 1 /* assumes Perfect Filtering format */ 148 149static void 150show_packet(char c, eth_pkt_t *pkt) 151{ 152 int i; 153 int n = (pkt->length < 32 ? pkt->length : 32); 154 155 xprintf("%c[%4d]:", c, pkt->length); 156 for (i = 0; i < n; i++) { 157 if (i % 4 == 0) 158 xprintf(" "); 159 xprintf("%02x", pkt->buffer[i]); 160 } 161 xprintf("\n"); 162} 163 164 165/* Descriptor structures */ 166 167typedef struct rx_dscr { 168 uint32_t rxd_flags; 169 uint32_t rxd_bufsize; 170 pci_addr_t rxd_bufaddr1; 171 pci_addr_t rxd_bufaddr2; 172} rx_dscr; 173 174typedef struct tx_dscr { 175 uint32_t txd_flags; 176 uint32_t txd_bufsize; 177 pci_addr_t txd_bufaddr1; 178 pci_addr_t txd_bufaddr2; 179} tx_dscr; 180 181/* CAM structure */ 182 183typedef union { 184 struct { 185 uint32_t physical[CAM_PERFECT_ENTRIES][3]; 186 } p; 187 struct { 188 uint32_t hash[32]; 189 uint32_t mbz[7]; 190 uint32_t physical[3]; 191 } h; 192} tulip_cam; 193 194 195/* Driver data structures */ 196 197typedef enum { 198 K_CHIP_UNKNOWN, 199 K_CHIP_DC21040, 200 K_CHIP_DC21041, 201 K_CHIP_DC21140, 202 K_CHIP_DC21143, 203 K_CHIP_DM9102, 204 K_CHIP_82C169 205} tulip_chip_t; 206 207typedef enum { 208 eth_state_uninit, 209 eth_state_setup, 210 eth_state_off, 211 eth_state_on, 212 eth_state_broken 213} eth_state_t; 214 215#define ETH_PKTPOOL_SIZE 32 216#define ETH_PKT_SIZE MAX_ETHER_PACK 217 218typedef struct tulip_softc_s tulip_softc; 219 220struct tulip_softc_s { 221 uint32_t membase; 222 uint8_t irq; /* interrupt mapping (used if IPOLL) */ 223 pcitag_t tag; /* tag for configuration registers */ 224 225 uint8_t hwaddr[ENET_ADDR_LEN]; 226 227 uint16_t device; /* chip device code */ 228 uint8_t revision; /* chip revision and step (Table 3-7) */ 229 230 /* current state */ 231 eth_state_t state; 232 233 /* These fields are the chip startup values. */ 234// uint16_t media; /* media type */ 235 uint32_t opmode; /* operating mode */ 236 uint32_t intmask; /* interrupt mask */ 237 uint32_t gpdata; /* output bits for csr15 (21143) */ 238 239 /* These fields are the summary of byte swapping requirements */ 240 int swap; /* Swap bytes in descriptors */ 241 uint32_t endian; /* Prefix bits for byte lane swapping */ 242 243 /* These fields are set before calling dc21x4x_hwinit */ 244 int linkspeed; /* encodings from cfe_ioctl */ 245 int loopback; 246 247 /* Packet free list */ 248 queue_t freelist; 249 uint8_t *pktpool; 250 queue_t rxqueue; 251 252 /* The descriptor tables */ 253 uint8_t *rxdscrmem; /* receive descriptors */ 254 uint8_t *txdscrmem; /* transmit descriptors */ 255 256 /* These fields keep track of where we are in tx/rx processing */ 257 volatile rx_dscr *rxdscr_start; /* beginning of ring */ 258 volatile rx_dscr *rxdscr_end; /* end of ring */ 259 volatile rx_dscr *rxdscr_remove; /* next one we expect tulip to use */ 260 volatile rx_dscr *rxdscr_add; /* next place to put a buffer */ 261 int rxdscr_onring; 262 263 volatile tx_dscr *txdscr_start; /* beginning of ring */ 264 volatile tx_dscr *txdscr_end; /* end of ring */ 265 volatile tx_dscr *txdscr_remove; /* next one we will use for tx */ 266 volatile tx_dscr *txdscr_add; /* next place to put a buffer */ 267 268 /* The descriptor options */ 269 uint32_t rxdscr_owned; /* RDES0_OWNADAP in proper byte order */ 270 uint32_t rxdscr_ctrl; /* RDES1 control bits (chaining) */ 271 uint32_t txdscr_owned; /* TDES0 OWNADAP in proper byte order */ 272 uint32_t txdscr_ctrl; /* TDES1 control bits */ 273 274 cfe_devctx_t *devctx; 275 276 /* These fields describe the PHY */ 277 enum {NONE, SRL, MII, SYM} phy_type; 278 int phy_addr; 279 uint32_t phy_vendor; 280 uint16_t phy_device; 281 uint16_t (*mii_read_register)(tulip_softc *sc, unsigned int index); 282 void (*mii_write_register)(tulip_softc *sc, unsigned int index, 283 uint16_t value); 284 285 /* Statistics */ 286 uint32_t inpkts; 287 uint32_t outpkts; 288 uint32_t interrupts; 289 uint32_t rx_interrupts; 290 uint32_t tx_interrupts; 291 uint32_t bus_errors; 292}; 293 294 295/* Entry to and exit from critical sections (currently relative to 296 interrupts only, not SMP) */ 297 298#if CFG_INTERRUPTS 299#define CS_ENTER(sc) cfe_disable_irq(sc->irq) 300#define CS_EXIT(sc) cfe_enable_irq(sc->irq) 301#else 302#define CS_ENTER(sc) ((void)0) 303#define CS_EXIT(sc) ((void)0) 304#endif 305 306 307/* Driver parameterization */ 308 309#define MAXRXDSCR 32 310#define MAXTXDSCR 32 311#define MINRXRING 8 312 313#define MEDIA_UNKNOWN 0 314#define MEDIA_AUI 1 315#define MEDIA_BNC 2 316#define MEDIA_UTP_FULL_DUPLEX 3 317#define MEDIA_UTP_NO_LINK_TEST 4 318#define MEDIA_UTP 5 319 320/* Prototypes */ 321 322static void tulip_ether_probe(cfe_driver_t *drv, 323 unsigned long probe_a, unsigned long probe_b, 324 void *probe_ptr); 325 326 327/* Byte swap utilities. */ 328 329#if ENDIAN_BIG 330 331static uint32_t 332swap4(uint32_t x) 333{ 334 uint32_t t; 335 336 t = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); 337 return (t >> 16) | ((t & 0xFFFF) << 16); 338} 339 340#define DMA_SWAP(sc,x) ((sc)->swap ? swap4(x) : (x)) 341#else 342#define DMA_SWAP(sc,x) (x) 343#endif 344 345 346/* Address mapping macros */ 347 348/* Byte lane swapping is controlled by prefix bits of the PCI address. */ 349#define M_ENDIAN_BIT 0x20000000 350#define M_MATCH_BITS (M_ENDIAN_BIT) 351#define M_MATCH_BYTES (0x00000000) 352 353/* Note that PTR_TO_PHYS only works with 32-bit addresses, but then 354 so does the Tulip. */ 355#define PTR_TO_PHYS(x) (PHYSADDR((uintptr_t)(x))) 356#define PHYS_TO_PTR(a) ((uint8_t *)KERNADDR(a)) 357 358/* Not all tulip clones can do big-endian DMA, so we cannot use the 359 default definitions of PHYS_TO_PCI and PCI_TO_PHYS, which assume 360 that capability. */ 361#undef PHYS_TO_PCI 362#undef PCI_TO_PHYS 363#define PHYS_TO_PCI(sc,a) ((uint32_t) (a) | (sc)->endian) 364#define PCI_TO_PHYS(sc,a) ((uint32_t) (a) & ~M_ENDIAN_BIT) 365 366#define PCI_TO_PTR(sc,a) (PHYS_TO_PTR(PCI_TO_PHYS((sc),(a)))) 367#define PTR_TO_PCI(sc,x) (PHYS_TO_PCI((sc),PTR_TO_PHYS(x))) 368 369#if (ENDIAN_BIG && MATCH_BYTES) 370#define CSR_MATCH_MODE PCI_MATCH_BYTES 371#define READCSR(sc,csr) (phys_read32_swapped((sc)->membase + (csr))) 372#define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val))) 373#else 374#define CSR_MATCH_MODE PCI_MATCH_BITS 375#define READCSR(sc,csr) (phys_read32((sc)->membase + (csr))) 376#define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) 377#endif 378 379#define RESET_ADAPTER(sc) \ 380 { \ 381 WRITECSR((sc), R_CSR_BUSMODE, M_CSR0_SWRESET); \ 382 cfe_sleep(CFE_HZ/10); \ 383 } 384 385 386/* Debugging */ 387 388static void 389dumpstat(tulip_softc *sc) 390{ 391 xprintf("-- CSR 5 = %08X CSR 6 = %08x\n", 392 READCSR(sc, R_CSR_STATUS), READCSR(sc, R_CSR_OPMODE)); 393} 394 395static void 396dumpcsrs(tulip_softc *sc) 397{ 398 int idx; 399 400 xprintf("-------------\n"); 401 for (idx = 0; idx < 16; idx++) { 402 xprintf("CSR %2d = %08X\n", idx, READCSR(sc, idx*8)); 403 } 404 xprintf("-------------\n"); 405 406} 407 408 409/* Packet management */ 410 411/* ********************************************************************* 412 * ETH_ALLOC_PKT(sc) 413 * 414 * Allocate a packet from the free list. 415 * 416 * Input parameters: 417 * sc - eth structure 418 * 419 * Return value: 420 * pointer to packet structure, or NULL if none available 421 ********************************************************************* */ 422static eth_pkt_t * 423eth_alloc_pkt(tulip_softc *sc) 424{ 425 eth_pkt_t *pkt; 426 427 CS_ENTER(sc); 428 pkt = (eth_pkt_t *) q_deqnext(&sc->freelist); 429 CS_EXIT(sc); 430 if (!pkt) return NULL; 431 432 pkt->buffer = pkt->data; 433 pkt->length = ETH_PKT_SIZE; 434 pkt->flags = 0; 435 436 return pkt; 437} 438 439 440/* ********************************************************************* 441 * ETH_FREE_PKT(sc,pkt) 442 * 443 * Return a packet to the free list 444 * 445 * Input parameters: 446 * sc - sbmac structure 447 * pkt - packet to return 448 * 449 * Return value: 450 * nothing 451 ********************************************************************* */ 452static void 453eth_free_pkt(tulip_softc *sc, eth_pkt_t *pkt) 454{ 455 CS_ENTER(sc); 456 q_enqueue(&sc->freelist, &pkt->next); 457 CS_EXIT(sc); 458} 459 460 461/* ********************************************************************* 462 * ETH_INITFREELIST(sc) 463 * 464 * Initialize the buffer free list for this mac. The memory 465 * allocated to the free list is carved up and placed on a linked 466 * list of buffers for use by the mac. 467 * 468 * Input parameters: 469 * sc - eth structure 470 * 471 * Return value: 472 * nothing 473 ********************************************************************* */ 474static void 475eth_initfreelist(tulip_softc *sc) 476{ 477 int idx; 478 uint8_t *ptr; 479 eth_pkt_t *pkt; 480 481 q_init(&sc->freelist); 482 483 ptr = sc->pktpool; 484 for (idx = 0; idx < ETH_PKTPOOL_SIZE; idx++) { 485 pkt = (eth_pkt_t *) ptr; 486 eth_free_pkt(sc, pkt); 487 ptr += ETH_PKTBUF_SIZE; 488 } 489} 490 491 492/* Utilities */ 493 494static const char * 495tulip_devname(tulip_softc *sc) 496{ 497 return (sc->devctx != NULL ? cfe_device_name(sc->devctx) : "eth?"); 498} 499 500 501/* Descriptor ring management */ 502 503static int 504tulip_add_rcvbuf(tulip_softc *sc, eth_pkt_t *pkt) 505{ 506 volatile rx_dscr *rxd; 507 volatile rx_dscr *nextrxd; 508 uint32_t ctrl; 509 510 rxd = sc->rxdscr_add; 511 ctrl = sc->rxdscr_ctrl; 512 513 /* Figure out where the next descriptor will go */ 514 nextrxd = rxd+1; 515 if (nextrxd == sc->rxdscr_end) { 516 nextrxd = sc->rxdscr_start; 517 ctrl = M_RDES1_ENDOFRING; 518 } 519 520 /* If the next one is the same as our remove pointer, the ring is 521 considered full. */ 522 if (nextrxd == sc->rxdscr_remove) return -1; 523 524 rxd->rxd_bufsize = DMA_SWAP(sc, V_RDES1_BUF1SIZE(1520) | ctrl); 525 rxd->rxd_bufaddr1 = DMA_SWAP(sc, PTR_TO_PCI(sc,pkt->buffer)); 526 rxd->rxd_flags = sc->rxdscr_owned; 527 528 /* success, advance the pointer */ 529 sc->rxdscr_add = nextrxd; 530 531 return 0; 532} 533 534static void 535tulip_fillrxring(tulip_softc *sc) 536{ 537 eth_pkt_t *pkt; 538 539 CS_ENTER(sc); 540 while (1) { 541 if (sc->rxdscr_onring >= MINRXRING) { 542 CS_EXIT(sc); 543 break; 544 } 545 CS_EXIT(sc); 546 pkt = eth_alloc_pkt(sc); 547 if (pkt == NULL) { 548 /* could not allocate a buffer */ 549 break; 550 } 551 if (tulip_add_rcvbuf(sc, pkt) != 0) { 552 /* could not add buffer to ring */ 553 eth_free_pkt(sc, pkt); 554 break; 555 } 556 CS_ENTER(sc); 557 sc->rxdscr_onring++; 558 } 559} 560 561 562/* ********************************************************************* 563 * TULIP_RX_CALLBACK(sc, pkt) 564 * 565 * Receive callback routine. This routine is invoked when a 566 * buffer queued for receives is filled. In this simple driver, 567 * all we do is add the packet to a per-MAC queue for later 568 * processing, and try to put a new packet in the place of the one 569 * that was removed from the queue. 570 * 571 * Input parameters: 572 * sc - interface 573 * ptk - packet context (eth_pkt structure) 574 * 575 * Return value: 576 * nothing 577 ********************************************************************* */ 578static void 579tulip_rx_callback(tulip_softc *sc, eth_pkt_t *pkt) 580{ 581 if (TULIP_DEBUG) show_packet('>', pkt); /* debug */ 582 583 CS_ENTER(sc); 584 q_enqueue(&sc->rxqueue, &pkt->next); 585 CS_EXIT(sc); 586 sc->inpkts++; 587} 588 589 590static void 591tulip_procrxring(tulip_softc *sc) 592{ 593 volatile rx_dscr *rxd; 594 eth_pkt_t *pkt; 595 eth_pkt_t *newpkt; 596 uint32_t flags; 597 598 for (;;) { 599 rxd = sc->rxdscr_remove; 600 601 flags = rxd->rxd_flags; 602 if (flags & sc->rxdscr_owned) { 603 /* end of ring, no more packets */ 604 break; 605 } 606 flags = DMA_SWAP(sc, flags); 607 608 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, DMA_SWAP(sc, rxd->rxd_bufaddr1))); 609 610 /* Drop error packets */ 611 if (flags & M_RDES0_ERRORSUM) { 612 xprintf("%s: rx error %04X\n", tulip_devname(sc), flags & 0xFFFF); 613 newpkt = pkt; /* recycle the buffer */ 614 } 615 else { 616 /* Pass up the packet */ 617 pkt->length = G_RDES0_FRAMELEN(flags) - ENET_CRC_SIZE; 618 tulip_rx_callback(sc, pkt); 619 620 /* put a buffer back on the ring to replace this one */ 621 newpkt = eth_alloc_pkt(sc); 622 } 623 624 /* update the pointer, accounting for buffer wrap. */ 625 rxd++; 626 if (rxd == sc->rxdscr_end) 627 rxd = sc->rxdscr_start; 628 sc->rxdscr_remove = rxd; 629 630 if (newpkt) { 631 /* The ring must have space now. */ 632 tulip_add_rcvbuf(sc, newpkt); 633 } 634 else { 635 CS_ENTER(sc); 636 sc->rxdscr_onring--; 637 CS_EXIT(sc); 638 } 639 } 640} 641 642 643static int 644tulip_add_txbuf(tulip_softc *sc, eth_pkt_t *pkt) 645{ 646 volatile tx_dscr *txd; 647 volatile tx_dscr *nexttxd; 648 uint32_t bufsize; 649 650 txd = sc->txdscr_add; 651 bufsize = sc->txdscr_ctrl; 652 653 /* Figure out where the next descriptor will go */ 654 nexttxd = (txd+1); 655 if (nexttxd == sc->txdscr_end) { 656 nexttxd = sc->txdscr_start; 657 bufsize = M_TDES1_ENDOFRING; 658 } 659 660 /* If the next one is the same as our remove pointer, 661 the ring is considered full. (it actually has room for 662 one more, but we reserve the remove == add case for "empty") */ 663 664 if (nexttxd == sc->txdscr_remove) return -1; 665 666 bufsize |= V_TDES1_BUF1SIZE(pkt->length) | 667 M_TDES1_FIRSTSEG | M_TDES1_LASTSEG | M_TDES1_INTERRUPT; 668 if (pkt->flags & ETH_TX_SETUP) { 669 /* For a setup packet, FIRSTSEG and LASTSEG should be clear (!) */ 670 bufsize ^= M_TDES1_SETUP | M_TDES1_FIRSTSEG | M_TDES1_LASTSEG; 671 } 672 txd->txd_bufsize = DMA_SWAP(sc, bufsize); 673 txd->txd_bufaddr1 = DMA_SWAP(sc, PTR_TO_PCI(sc, pkt->buffer)); 674 txd->txd_flags = sc->txdscr_owned; 675 676 /* success, advance the pointer */ 677 sc->txdscr_add = nexttxd; 678 679 return 0; 680} 681 682 683static int 684tulip_transmit(tulip_softc *sc,eth_pkt_t *pkt) 685{ 686 int rv; 687 688 if (TULIP_DEBUG) show_packet('<', pkt); /* debug */ 689 690 rv = tulip_add_txbuf(sc, pkt); 691 sc->outpkts++; 692 693 WRITECSR(sc, R_CSR_TXPOLL, 1); 694 return rv; 695} 696 697 698static void 699tulip_proctxring(tulip_softc *sc) 700{ 701 volatile tx_dscr *txd; 702 eth_pkt_t *pkt; 703 uint32_t flags; 704 705 for (;;) { 706 txd = sc->txdscr_remove; 707 708 if (txd == sc->txdscr_add) { 709 /* ring is empty, no buffers to process */ 710 break; 711 } 712 713 flags = txd->txd_flags; 714 if (flags & sc->txdscr_owned) { 715 /* Reached a packet still being transmitted */ 716 break; 717 } 718 719 flags = DMA_SWAP(sc, flags); 720 721 /* Check for a completed setup packet */ 722 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, DMA_SWAP(sc, txd->txd_bufaddr1))); 723 if (pkt->flags & ETH_TX_SETUP) { 724 if (sc->state == eth_state_setup) { 725 uint32_t opmode; 726 727 /* check flag bits */ 728 opmode = READCSR(sc, R_CSR_OPMODE); 729 opmode |= M_CSR6_RXSTART; 730 WRITECSR(sc, R_CSR_OPMODE, opmode); 731 sc->inpkts = sc->outpkts = 0; 732 sc->state = eth_state_on; 733 } 734 pkt->flags &=~ ETH_TX_SETUP; 735 } 736 737 /* Just free the packet */ 738 eth_free_pkt(sc, pkt); 739 740 /* update the pointer, accounting for buffer wrap. */ 741 txd++; 742 if (txd == sc->txdscr_end) 743 txd = sc->txdscr_start; 744 745 sc->txdscr_remove = txd; 746 } 747} 748 749 750static void 751tulip_initrings(tulip_softc *sc) 752{ 753 volatile tx_dscr *txd, *txn; 754 volatile rx_dscr *rxd, *rxn; 755 756 /* Claim ownership of all descriptors for the driver */ 757 758 for (txd = sc->txdscr_start; txd != sc->txdscr_end; txd++) { 759 txn = txd + 1; 760 if (txn == sc->txdscr_end) txn = sc->txdscr_start; 761 txd->txd_flags = 0; 762 txd->txd_bufsize = DMA_SWAP(sc, sc->txdscr_ctrl); 763 if (sc->txdscr_ctrl & M_TDES1_CHAINED) 764 txd->txd_bufaddr2 = DMA_SWAP(sc, PTR_TO_PCI(sc, txn)); 765 else 766 txd->txd_bufaddr2 = 0; 767 } 768 769 for (rxd = sc->rxdscr_start; rxd != sc->rxdscr_end; rxd++) { 770 rxn = rxd + 1; 771 if (rxn == sc->rxdscr_end) rxn = sc->rxdscr_start; 772 rxd->rxd_flags = 0; 773 rxd->rxd_bufsize = DMA_SWAP(sc, sc->rxdscr_ctrl); 774 if (sc->rxdscr_ctrl & M_RDES1_CHAINED) 775 rxd->rxd_bufaddr2 = DMA_SWAP(sc, PTR_TO_PCI(sc, rxn)); 776 else 777 rxd->rxd_bufaddr2 = 0; 778 } 779 780 /* Init the ring pointers */ 781 782 sc->txdscr_add = sc->txdscr_remove = sc->txdscr_start; 783 sc->rxdscr_add = sc->rxdscr_remove = sc->rxdscr_start; 784 sc->rxdscr_onring = 0; 785 786 /* Add stuff to the receive ring */ 787 788 tulip_fillrxring(sc); 789} 790 791 792static int 793tulip_init(tulip_softc *sc) 794{ 795 /* Allocate descriptor rings */ 796 sc->rxdscrmem = KMALLOC(MAXRXDSCR*sizeof(rx_dscr), sizeof(rx_dscr)); 797 sc->txdscrmem = KMALLOC(MAXTXDSCR*sizeof(tx_dscr), sizeof(tx_dscr)); 798 799 /* Allocate buffer pool */ 800 sc->pktpool = KMALLOC(ETH_PKTPOOL_SIZE*ETH_PKTBUF_SIZE, CACHE_ALIGN); 801 eth_initfreelist(sc); 802 q_init(&sc->rxqueue); 803 804 /* Fill in pointers to the rings */ 805 sc->rxdscr_start = (volatile rx_dscr *) (sc->rxdscrmem); 806 sc->rxdscr_end = sc->rxdscr_start + MAXRXDSCR; 807 sc->rxdscr_add = sc->rxdscr_start; 808 sc->rxdscr_remove = sc->rxdscr_start; 809 sc->rxdscr_onring = 0; 810 811 sc->txdscr_start = (volatile tx_dscr *) (sc->txdscrmem); 812 sc->txdscr_end = sc->txdscr_start + MAXTXDSCR; 813 sc->txdscr_add = sc->txdscr_start; 814 sc->txdscr_remove = sc->txdscr_start; 815 816 tulip_initrings(sc); 817 818 return 0; 819} 820 821 822static void 823tulip_resetrings(tulip_softc *sc) 824{ 825 volatile tx_dscr *txd; 826 volatile rx_dscr *rxd; 827 eth_pkt_t *pkt; 828 829 /* Free already-sent descriptors and buffers */ 830 tulip_proctxring(sc); 831 832 /* Free any pending but unsent */ 833 txd = sc->txdscr_remove; 834 while (txd != sc->txdscr_add) { 835 836 txd->txd_flags &=~ sc->txdscr_owned; 837 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, DMA_SWAP(sc, txd->txd_bufaddr1))); 838 eth_free_pkt(sc, pkt); 839 840 txd++; 841 if (txd == sc->txdscr_end) 842 txd = sc->txdscr_start; 843 } 844 sc->txdscr_add = sc->txdscr_remove; 845 846 /* Discard any received packets as well as all free buffers */ 847 rxd = sc->rxdscr_remove; 848 while (rxd != sc->rxdscr_add) { 849 rxd->rxd_flags &=~ sc->rxdscr_owned; 850 pkt = ETH_PKT_BASE(PCI_TO_PTR(sc, DMA_SWAP(sc, rxd->rxd_bufaddr1))); 851 eth_free_pkt(sc, pkt); 852 853 rxd++; 854 if (rxd == sc->rxdscr_end) 855 rxd = sc->rxdscr_start; 856 CS_ENTER(sc); 857 sc->rxdscr_onring--; 858 CS_EXIT(sc); 859 } 860 861 /* Reestablish the initial state. */ 862 tulip_initrings(sc); 863} 864 865 866/* CRCs */ 867 868static uint32_t 869tulip_crc32(const uint8_t *databuf, unsigned int datalen) 870{ 871 unsigned int idx, bit, data; 872 uint32_t crc; 873 874 crc = 0xFFFFFFFFUL; 875 for (idx = 0; idx < datalen; idx++) 876 for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1) 877 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? ENET_CRC32_POLY : 0); 878 return crc; 879} 880 881#define tulip_mchash(mca) (tulip_crc32((mca), 6) & 0x1FF) 882 883 884/* Serial ROM access */ 885 886/* 887 * Delays below (nsec) are chosen to meet specs for NS93C46 (slow M variant). 888 * Current parts are faster. 889 * Reference: NS Memory Data Book, 1994 890 */ 891 892#define SROM_SIZE 128 893#define SROM_MAX_CYCLES 32 894 895#define SROM_CMD_BITS 3 896#define SROM_ADDR_BITS 6 897 898#define K_SROM_READ_CMD 06 899#define K_SROM_WRITE_CMD 05 900#define K_SROM_WEN_CMD 04 /* WEN, WDS, also WRAL, ERAL */ 901 902#define SROM_VENDOR_INDEX 0x00 903#define SROM_FORMAT_INDEX 0x12 904#define SROM_ADDR_INDEX 0x14 905 906#define SROM_DEVICE0_INDEX 0x1A 907#define SROM_LEAF0_OFFSET_INDEX 0x1B 908 909#define SROM_CRC_INDEX (SROM_SIZE-2) 910/* Note recent chips supporting wake-on-lan have CRC in bytes 94, 95 */ 911 912#define SROM_WORD(rom,offset) ((rom)[offset] | ((rom)[offset+1] << 8)) 913 914static void 915srom_idle_state(tulip_softc *sc) 916{ 917 uint32_t csr9; 918 unsigned int i; 919 920 csr9 = READCSR(sc, R_CSR_ROM_MII); 921 922 csr9 |= M_CSR9_SROMCHIPSEL; 923 WRITECSR(sc, R_CSR_ROM_MII, csr9); 924 cfe_nsleep(100); /* CS setup (Tcss=100) */ 925 926 /* Run the clock through the maximum number of pending read cycles */ 927 for (i = 0; i < SROM_MAX_CYCLES*2; i++) { 928 csr9 ^= M_CSR9_SROMCLOCK; 929 WRITECSR(sc, R_CSR_ROM_MII, csr9); 930 cfe_nsleep(1000); /* SK period (Fsk=0.5MHz) */ 931 } 932 933 /* Deassert SROM Chip Select */ 934 csr9 &=~ M_CSR9_SROMCHIPSEL; 935 WRITECSR(sc, R_CSR_ROM_MII, csr9); 936 cfe_nsleep(50); /* CS recovery (Tsks=50) */ 937} 938 939static void 940srom_write_bit(tulip_softc *sc, unsigned int data) 941{ 942 uint32_t csr9; 943 944 csr9 = READCSR(sc, R_CSR_ROM_MII); 945 946 /* Place the data bit on the bus */ 947 if (data == 1) 948 csr9 |= M_CSR9_SROMDATAIN; 949 else 950 csr9 &=~ M_CSR9_SROMDATAIN; 951 952 WRITECSR(sc, R_CSR_ROM_MII, csr9); 953 cfe_nsleep(360); /* setup: Tdis=200 */ 954 955 /* Now clock the data into the SROM */ 956 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK); 957 cfe_nsleep(900); /* clock high, Tskh=500 */ 958 WRITECSR(sc, R_CSR_ROM_MII, csr9); 959 cfe_nsleep(450); /* clock low, Tskl=250 */ 960 961 /* Now clear the data bit */ 962 csr9 &=~ M_CSR9_SROMDATAIN; /* data invalid, Tidh=20 for SK^ */ 963 WRITECSR(sc, R_CSR_ROM_MII, csr9); 964 cfe_nsleep(270); /* min cycle, 1/Fsk=2000 */ 965} 966 967static uint16_t 968srom_read_bit(tulip_softc *sc) 969{ 970 uint32_t csr9; 971 972 csr9 = READCSR(sc, R_CSR_ROM_MII); 973 974 /* Generate a clock cycle before doing a read */ 975 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK); /* rising edge */ 976 cfe_nsleep(1000); /* clock high, Tskh=500, Tpd=1000 */ 977 WRITECSR(sc, R_CSR_ROM_MII, csr9); /* falling edge */ 978 cfe_nsleep(1000); /* clock low, 1/Fsk=2000 */ 979 980 csr9 = READCSR(sc, R_CSR_ROM_MII); 981 return ((csr9 & M_CSR9_SROMDATAOUT) != 0 ? 1 : 0); 982} 983 984#define CMD_BIT_MASK (1 << (SROM_CMD_BITS+SROM_ADDR_BITS-1)) 985 986static uint16_t 987srom_read_word(tulip_softc *sc, unsigned int index) 988{ 989 uint16_t command, word; 990 uint32_t csr9; 991 unsigned int i; 992 993 csr9 = READCSR(sc, R_CSR_ROM_MII) | M_CSR9_SROMCHIPSEL; 994 995 /* Assert the SROM CS line */ 996 WRITECSR(sc, R_CSR_ROM_MII, csr9); 997 cfe_nsleep(100); /* CS setup, Tcss = 100 */ 998 999 /* Send the read command to the SROM */ 1000 command = (K_SROM_READ_CMD << SROM_ADDR_BITS) | index; 1001 for (i = 0; i < SROM_CMD_BITS+SROM_ADDR_BITS; i++) { 1002 srom_write_bit(sc, (command & CMD_BIT_MASK) != 0 ? 1 : 0); 1003 command <<= 1; 1004 } 1005 1006 /* Now read the bits from the SROM (MSB first) */ 1007 word = 0; 1008 for (i = 0; i < 16; ++i) { 1009 word <<= 1; 1010 word |= srom_read_bit(sc); 1011 } 1012 1013 /* Clear the SROM CS Line, CS hold, Tcsh = 0 */ 1014 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL); 1015 1016 return word; 1017} 1018 1019static void 1020srom_set_enable(tulip_softc *sc, int enable) 1021{ 1022 uint16_t command; 1023 uint32_t csr9; 1024 unsigned int i; 1025 unsigned int bits = (enable ? 0x3F : 0x00); 1026 1027 csr9 = READCSR(sc, R_CSR_ROM_MII) | M_CSR9_SROMCHIPSEL; 1028 1029 /* Assert the SROM CS line */ 1030 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1031 cfe_nsleep(100); /* CS setup, Tcss = 100 */ 1032 1033 /* Send the enable command to the SROM */ 1034 command = (K_SROM_WEN_CMD << SROM_ADDR_BITS) | bits; 1035 for (i = 0; i < SROM_CMD_BITS+SROM_ADDR_BITS; i++) { 1036 srom_write_bit(sc, (command & CMD_BIT_MASK) != 0 ? 1 : 0); 1037 command <<= 1; 1038 } 1039 1040 /* Clear the SROM CS Line, CS hold, Tcsh = 0 */ 1041 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL); 1042} 1043 1044static int 1045srom_write_word(tulip_softc *sc, unsigned int index, uint16_t word) 1046{ 1047 uint16_t command; 1048 uint32_t csr9; 1049 unsigned int i; 1050 1051 csr9 = READCSR(sc, R_CSR_ROM_MII) | M_CSR9_SROMCHIPSEL; 1052 1053 /* Assert the SROM CS line */ 1054 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1055 cfe_nsleep(100); /* CS setup, Tcss = 100 */ 1056 1057 /* Send the write command to the SROM */ 1058 command = (K_SROM_WRITE_CMD << SROM_ADDR_BITS) | index; 1059 for (i = 0; i < SROM_CMD_BITS+SROM_ADDR_BITS; i++) { 1060 srom_write_bit(sc, (command & CMD_BIT_MASK) != 0 ? 1 : 0); 1061 command <<= 1; 1062 } 1063 1064 /* Now write the bits to the SROM (MSB first) */ 1065 for (i = 0; i < 16; ++i) { 1066 srom_write_bit(sc, (word & 0x8000) != 0 ? 1 : 0); 1067 word <<= 1; 1068 } 1069 1070 /* Clear and reassert the SROM CS Line */ 1071 csr9 = READCSR(sc, R_CSR_ROM_MII); 1072 csr9 &= ~(M_CSR9_SROMCHIPSEL | M_CSR9_SROMCLOCK | M_CSR9_SROMDATAIN); 1073 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1074 cfe_nsleep(500); 1075 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCHIPSEL); 1076 cfe_nsleep(500); 1077 1078 /* Wait while busy */ 1079 for (i = 1000; i > 0; --i) { 1080 csr9 = READCSR(sc, R_CSR_ROM_MII); 1081 if ((csr9 & M_CSR9_SROMDATAOUT) != 0) 1082 break; 1083 cfe_usleep(1000); /* Wait 1 ms. */ 1084 } 1085 1086 /* Clear the SROM CS Line, CS hold, Tcsh = 0 */ 1087 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL); 1088 1089 return (i > 0) ? 0 : -1; /* Fail on timeout */ 1090} 1091 1092 1093/**************************************************************************** 1094 * srom_calc_crc() 1095 * 1096 * Calculate the CRC of the SROM and return it. We compute the 1097 * CRC per Appendix A of the 21140A ROM/external register data 1098 * sheet (EC-QPQWA-TE). 1099 ***************************************************************************/ 1100 1101static uint16_t 1102srom_calc_crc(tulip_softc *sc, uint8_t srom[], int length) 1103{ 1104 uint32_t crc = tulip_crc32(srom, length) ^ 0xFFFFFFFF; 1105 1106 return (uint16_t)(crc & 0xFFFF); 1107} 1108 1109/**************************************************************************** 1110 * srom_read_all(sc, uint8_t dest) 1111 * 1112 * Read the entire SROM into the srom array 1113 * 1114 * Input parameters: 1115 * sc - tulip state 1116 ***************************************************************************/ 1117 1118static int 1119srom_read_all(tulip_softc *sc, uint8_t dest[]) 1120{ 1121 int i; 1122 uint16_t crc, temp; 1123 1124 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMREAD); 1125 1126 srom_idle_state(sc); 1127 1128 for (i = 0; i < SROM_SIZE/2; i++) { 1129 temp = srom_read_word(sc, i); 1130 dest[2*i] = temp & 0xFF; 1131 dest[2*i+1] =temp >> 8; 1132 } 1133 1134 WRITECSR(sc, R_CSR_ROM_MII, 0); /* CS hold, Tcsh=0 */ 1135 1136 crc = srom_calc_crc(sc, dest, SROM_CRC_INDEX); 1137 if (crc != SROM_WORD(dest, SROM_CRC_INDEX)) { 1138 crc = srom_calc_crc(sc, dest, 94); /* "alternative" */ 1139 if (crc != SROM_WORD(dest, 94)) { 1140 xprintf("%s: Invalid SROM CRC, calc %04x, stored %04x\n", 1141 tulip_devname(sc), crc, SROM_WORD(dest, 94)); 1142 return -1; 1143 } 1144 } 1145 return 0; 1146} 1147 1148static int 1149srom_read_addr(tulip_softc *sc, uint8_t buf[]) 1150{ 1151 uint8_t srom[SROM_SIZE]; 1152 1153 if (srom_read_all(sc, srom) == 0) { 1154 memcpy(buf, &srom[SROM_ADDR_INDEX], ENET_ADDR_LEN); 1155 return 0; 1156 } 1157 1158 return -1; 1159} 1160 1161 1162/**************************************************************************** 1163 * earom_read_all(sc, uint8_t dest) 1164 * 1165 * Read the entire Ethernet address ROM into the srom array (21040 only) 1166 * 1167 * Input parameters: 1168 * sc - tulip state 1169 ***************************************************************************/ 1170 1171static int 1172earom_read_all(tulip_softc *sc, uint8_t dest[]) 1173{ 1174 int i; 1175 uint32_t csr9; 1176 1177 WRITECSR(sc, R_CSR_ROM_MII, 0); /* reset pointer */ 1178 1179 for (i = 0; i < SROM_SIZE; i++) { 1180 for (;;) { 1181 csr9 = READCSR(sc, R_CSR_ROM_MII); 1182 if ((csr9 & M_CSR9_DATANOTVALID) == 0) 1183 break; 1184 POLL(); /* XXX need a timeout */ 1185 } 1186 dest[i] = G_CSR9_ROMDATA(csr9); 1187 } 1188 1189 return 0; 1190} 1191 1192static int 1193earom_read_addr(tulip_softc *sc, uint8_t buf[]) 1194{ 1195 uint8_t srom[SROM_SIZE]; 1196 1197 if (earom_read_all(sc, srom) == 0) { 1198 memcpy(buf, &srom[0], ENET_ADDR_LEN); 1199 return 0; 1200 } 1201 1202 return -1; 1203} 1204 1205 1206/**************************************************************************** 1207 * pnic_read_all(sc, uint8_t dest) 1208 * 1209 * Read the entire Ethernet address ROM into the srom array (PNIC only) 1210 * 1211 * Input parameters: 1212 * sc - tulip state 1213 ***************************************************************************/ 1214 1215static int 1216pnic_read_all(tulip_softc *sc, uint8_t dest[]) 1217{ 1218 int i; 1219 uint32_t csr9, csr19; 1220 uint32_t cmd; 1221 uint16_t data; 1222 1223 csr19 = READCSR(sc, R_CSR_ROMCTL); 1224 1225 for (i = 0; i < SROM_SIZE/2; i++) { 1226 cmd = M_CSR19_BUSY 1227 | V_CSR19_OPCODE(K_CSR19_OPCODE_READ) 1228 | V_CSR19_ADDR(i); 1229 WRITECSR(sc, R_CSR_ROMCTL, cmd); 1230 for (;;) { 1231 csr9 = READCSR(sc, R_CSR_ROMDATA); 1232 if ((csr9 & M_CSR9_BUSY) == 0) 1233 break; 1234 POLL(); /* XXX need a timeout */ 1235 } 1236 data = G_CSR9_SROMDATA(csr9); 1237 dest[2*i] = data >> 8; 1238 dest[2*i+1] = data & 0xFF; 1239 } 1240 1241 WRITECSR(sc, R_CSR_ROMCTL, csr19); 1242 return 0; 1243} 1244 1245static int 1246pnic_read_addr(tulip_softc *sc, uint8_t buf[]) 1247{ 1248 uint8_t srom[SROM_SIZE]; 1249 1250 if (pnic_read_all(sc, srom) == 0) { 1251 memcpy(buf, &srom[0], ENET_ADDR_LEN); 1252 return 0; 1253 } 1254 1255 return -1; 1256} 1257 1258 1259static int 1260rom_read_all(tulip_softc *sc, uint8_t buf[]) 1261{ 1262 switch (sc->device) { 1263 case K_CHIP_DC21040: 1264 return earom_read_all(sc, buf); 1265 case K_CHIP_82C169: 1266 return pnic_read_all(sc, buf); 1267 default: 1268 return srom_read_all(sc, buf); 1269 } 1270} 1271 1272static int 1273rom_read_addr(tulip_softc *sc, uint8_t buf[]) 1274{ 1275 switch (sc->device) { 1276 case K_CHIP_DC21040: 1277 return earom_read_addr(sc, buf); 1278 case K_CHIP_82C169: 1279 return pnic_read_addr(sc, buf); 1280 default: 1281 return srom_read_addr(sc, buf); 1282 } 1283} 1284 1285#if 0 1286static void 1287rom_dump(uint8_t srom[]) 1288{ 1289 int i; 1290 1291 xprintf("DC21x4x: SROM data:"); 1292 for (i = 0; i < SROM_SIZE; i++) { 1293 if (i % 16 == 0) 1294 xprintf("\n %02x: ", i); 1295 xprintf(" %02x", srom[i]); 1296 } 1297 xprintf("\n"); 1298} 1299#else 1300#define rom_dump(srom) 1301#endif 1302 1303 1304/**************************************************************************** 1305 * MII access utility routines 1306 ***************************************************************************/ 1307 1308/* MII clock limited to 2.5 MHz, transactions end with MDIO tristated */ 1309 1310static void 1311mii_write_bits(tulip_softc *sc, uint32_t data, unsigned int count) 1312{ 1313 uint32_t csr9; 1314 uint32_t bitmask; 1315 1316 csr9 = READCSR(sc, R_CSR_ROM_MII) &~ (M_CSR9_MDC | M_CSR9_MIIMODE); 1317 1318 for (bitmask = 1 << (count-1); bitmask != 0; bitmask >>= 1) { 1319 csr9 &=~ M_CSR9_MDO; 1320 if ((data & bitmask) != 0) csr9 |= M_CSR9_MDO; 1321 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1322 1323 cfe_nsleep(2000); /* setup */ 1324 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC); 1325 cfe_nsleep(2000); /* hold */ 1326 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1327 } 1328} 1329 1330static void 1331mii_turnaround(tulip_softc *sc) 1332{ 1333 uint32_t csr9; 1334 1335 csr9 = READCSR(sc, R_CSR_ROM_MII) | M_CSR9_MIIMODE; 1336 1337 /* stop driving data */ 1338 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1339 cfe_nsleep(2000); /* setup */ 1340 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC); 1341 cfe_nsleep(2000); /* clock high */ 1342 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1343 1344 /* read back and check for 0 here? */ 1345} 1346 1347/**************************************************************************** 1348 * mii_read_register 1349 * 1350 * This routine reads a register from the PHY chip using the MII 1351 * serial management interface. 1352 * 1353 * Input parameters: 1354 * index - index of register to read (0-31) 1355 * 1356 * Return value: 1357 * word read from register 1358 ***************************************************************************/ 1359 1360static uint16_t 1361mii_read_register(tulip_softc *sc, unsigned int index) 1362{ 1363 /* Send the command and address to the PHY. The sequence is 1364 a synchronization sequence (32 1 bits) 1365 a "start" command (2 bits) 1366 a "read" command (2 bits) 1367 the PHY addr (5 bits) 1368 the register index (5 bits) 1369 */ 1370 uint32_t csr9; 1371 uint16_t word; 1372 int i; 1373 1374 mii_write_bits(sc, 0xFF, 8); 1375 mii_write_bits(sc, 0xFFFFFFFF, 32); 1376 mii_write_bits(sc, MII_COMMAND_START, 2); 1377 mii_write_bits(sc, MII_COMMAND_READ, 2); 1378 mii_write_bits(sc, sc->phy_addr, 5); 1379 mii_write_bits(sc, index, 5); 1380 1381 mii_turnaround(sc); 1382 1383 csr9 = (READCSR(sc, R_CSR_ROM_MII) &~ M_CSR9_MDC) | M_CSR9_MIIMODE; 1384 word = 0; 1385 1386 for (i = 0; i < 16; i++) { 1387 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1388 cfe_nsleep(2000); /* clock width low */ 1389 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC); 1390 cfe_nsleep(2000); /* clock width high */ 1391 WRITECSR(sc, R_CSR_ROM_MII, csr9); 1392 cfe_nsleep(1000); /* output delay */ 1393 word <<= 1; 1394 if ((READCSR(sc, R_CSR_ROM_MII) & M_CSR9_MDI) != 0) 1395 word |= 0x0001; 1396 } 1397 1398 return word; 1399 1400 /* reset to output mode? */ 1401} 1402 1403/**************************************************************************** 1404 * mii_write_register 1405 * 1406 * This routine writes a register in the PHY chip using the MII 1407 * serial management interface. 1408 * 1409 * Input parameters: 1410 * index - index of register to write (0-31) 1411 * value - word to write 1412 ***************************************************************************/ 1413 1414static void 1415mii_write_register(tulip_softc *sc, unsigned int index, uint16_t value) 1416{ 1417 mii_write_bits(sc, 0xFF, 8); 1418 mii_write_bits(sc, 0xFFFFFFFF, 32); 1419 mii_write_bits(sc, MII_COMMAND_START, 2); 1420 mii_write_bits(sc, MII_COMMAND_WRITE, 2); 1421 mii_write_bits(sc, sc->phy_addr, 5); 1422 mii_write_bits(sc, index, 5); 1423 mii_write_bits(sc, MII_COMMAND_ACK, 2); 1424 mii_write_bits(sc, value, 16); 1425 1426 /* reset to input mode? */ 1427} 1428 1429 1430static int 1431mii_probe(tulip_softc *sc) 1432{ 1433 int i; 1434 uint16_t id1, id2; 1435 1436 for (i = 0; i < 32; i++) { 1437 sc->phy_addr = i; 1438 id1 = (*sc->mii_read_register)(sc, MII_PHYIDR1); 1439 id2 = (*sc->mii_read_register)(sc, MII_PHYIDR2); 1440 if ((id1 != 0x0000 && id1 != 0xFFFF) || 1441 (id2 != 0x0000 && id2 != 0xFFFF)) { 1442 sc->phy_vendor = ((uint32_t)id1 << 6) | ((id2 >> 10) & 0x3F); 1443 sc->phy_device = (id2 >> 4) & 0x3F; 1444 xprintf("%s: PHY %d, vendor: %06x, device %02x\n", 1445 tulip_devname(sc), 1446 sc->phy_addr, sc->phy_vendor, sc->phy_device); 1447 return 0; 1448 } 1449 } 1450 return -1; 1451} 1452 1453#define OUI_NAT_SEMI 0x080017 1454#define DEV_DP83840 0x00 1455 1456#if 0 1457static void 1458mii_dump(tulip_softc *sc, const char *label) 1459{ 1460 int i; 1461 uint16_t r; 1462 1463 xprintf("%s\n", label); 1464 for (i = 0; i <= 6; ++i) { 1465 r = (*sc->mii_read_register)(sc, i); 1466 xprintf("MII_REG%02x: %04x\n", i, r); 1467 } 1468 xprintf("OUI: %08x, Part %02x\n", sc->phy_vendor, sc->phy_device); 1469} 1470#else 1471#define mii_dump(sc,label) 1472#endif 1473 1474 1475/* The following functions are suitable for all tulips with MII 1476 interfaces. */ 1477 1478static void 1479mii_set_speed(tulip_softc *sc, int speed, int autoneg) 1480{ 1481 uint16_t control; 1482 uint32_t opmode = 0; 1483 1484 if (sc->phy_vendor == OUI_NAT_SEMI && sc->phy_device == DEV_DP83840) { 1485 uint16_t pcr; 1486 1487 /* Work-around for NS DP83840/A from ???. Needed? */ 1488 pcr = (*sc->mii_read_register)(sc, 0x17); 1489 pcr |= (0x400|0x100|0x40|0x20); 1490 (*sc->mii_write_register)(sc, 0x17, pcr); 1491 } 1492 1493 control = (*sc->mii_read_register)(sc, MII_BMCR); 1494 1495 if (!autoneg) { 1496 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1497 (*sc->mii_write_register)(sc, MII_BMCR, control); 1498 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX); 1499 } 1500 1501 switch (speed) { 1502 case ETHER_SPEED_10HDX: 1503 default: 1504 opmode = M_CSR6_SPEED_10_MII; 1505 break; 1506 case ETHER_SPEED_10FDX: 1507 control |= BMCR_DUPLEX; 1508 opmode = M_CSR6_SPEED_10_MII | M_CSR6_FULLDUPLEX; 1509 break; 1510 case ETHER_SPEED_100HDX: 1511 control |= BMCR_SPEED100; 1512 opmode = M_CSR6_SPEED_100_MII; 1513 break; 1514 case ETHER_SPEED_100FDX: 1515 control |= BMCR_SPEED100 | BMCR_DUPLEX ; 1516 opmode = M_CSR6_SPEED_100_MII | M_CSR6_FULLDUPLEX; 1517 break; 1518 } 1519 1520 if (!autoneg) 1521 (*sc->mii_write_register)(sc, MII_BMCR, control); 1522 1523 opmode |= M_CSR6_MBO; 1524 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 1525 WRITECSR(sc, R_CSR_OPMODE, opmode); 1526 mii_dump(sc, "setspeed PHY"); 1527} 1528 1529static void 1530mii_autonegotiate(tulip_softc *sc) 1531{ 1532 uint16_t control, status, cap; 1533 unsigned int timeout; 1534 int linkspeed; 1535 int autoneg; 1536 1537 linkspeed = ETHER_SPEED_UNKNOWN; 1538 1539 /* Read twice to clear latching bits */ 1540 status = (*sc->mii_read_register)(sc, MII_BMSR); 1541 status = (*sc->mii_read_register)(sc, MII_BMSR); 1542 mii_dump(sc, "query PHY"); 1543 1544 if ((status & (BMSR_AUTONEG | BMSR_LINKSTAT)) == 1545 (BMSR_AUTONEG | BMSR_LINKSTAT)) 1546 control = (*sc->mii_read_register)(sc, MII_BMCR); 1547 else { 1548 /* reset the PHY */ 1549 (*sc->mii_write_register)(sc, MII_BMCR, BMCR_RESET); 1550 timeout = 3000; 1551 for (;;) { 1552 control = (*sc->mii_read_register)(sc, MII_BMCR); 1553 if ((control && BMCR_RESET) == 0) break; 1554 cfe_sleep(CFE_HZ/2); 1555 timeout -= 500; 1556 if (timeout <= 0) break; 1557 } 1558 if ((control & BMCR_RESET) != 0) { 1559 xprintf("%s: PHY reset failed\n", tulip_devname(sc)); 1560 return; 1561 } 1562 1563 status = (*sc->mii_read_register)(sc, MII_BMSR); 1564 cap = ((status >> 6) & (ANAR_TXFD | ANAR_TXHD | ANAR_10FD | ANAR_10HD)) 1565 | PSB_802_3; 1566 (*sc->mii_write_register)(sc, MII_ANAR, cap); 1567 control |= (BMCR_ANENABLE | BMCR_RESTARTAN); 1568 (*sc->mii_write_register)(sc, MII_BMCR, control); 1569 1570 timeout = 3000; 1571 for (;;) { 1572 status = (*sc->mii_read_register)(sc, MII_BMSR); 1573 if ((status & BMSR_ANCOMPLETE) != 0) break; 1574 cfe_sleep(CFE_HZ/2); 1575 timeout -= 500; 1576 if (timeout <= 0) break; 1577 } 1578 mii_dump(sc, "done PHY"); 1579 } 1580 1581 xprintf("%s: Link speed: ", tulip_devname(sc)); 1582 if ((status & BMSR_ANCOMPLETE) != 0) { 1583 /* A link partner was negogiated... */ 1584 1585 uint16_t remote = (*sc->mii_read_register)(sc, MII_ANLPAR); 1586 1587 autoneg = 1; 1588 if ((remote & ANLPAR_TXFD) != 0) { 1589 xprintf("100BaseT FDX"); 1590 linkspeed = ETHER_SPEED_100FDX; 1591 } 1592 else if ((remote & ANLPAR_TXHD) != 0) { 1593 xprintf("100BaseT HDX"); 1594 linkspeed = ETHER_SPEED_100HDX; 1595 } 1596 else if ((remote & ANLPAR_10FD) != 0) { 1597 xprintf("10BaseT FDX"); 1598 linkspeed = ETHER_SPEED_10FDX; 1599 } 1600 else if ((remote & ANLPAR_10HD) != 0) { 1601 xprintf("10BaseT HDX"); 1602 linkspeed = ETHER_SPEED_10HDX; 1603 } 1604 xprintf("\n"); 1605 } 1606 else { 1607 /* no link partner negotiation */ 1608 1609 autoneg = 0; 1610 xprintf("Unknown, assuming 10BaseT\n"); 1611 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1612 (*sc->mii_write_register)(sc, MII_BMCR, control); 1613 linkspeed = ETHER_SPEED_10HDX; 1614 } 1615 1616 if ((status & BMSR_LINKSTAT) == 0) 1617 (*sc->mii_write_register)(sc, MII_BMCR, control); 1618 mii_set_speed(sc, linkspeed, autoneg); 1619 1620 status = (*sc->mii_read_register)(sc, MII_BMSR); /* clear latching bits */ 1621 mii_dump(sc, "final PHY"); 1622} 1623 1624 1625/* Chip specific code */ 1626 1627/* For the 21140 and 21143, we support only the MII (10/100) and SYM 1628 (100) interfaces. We attempt to discover the appropriate interface 1629 and port settings by scanning the vendor ROMs, but some are 1630 sufficiently confused or quirky to require special case code. */ 1631 1632/* Known vendors with cards requiring special initialization. */ 1633#define K_PCI_VENDOR_COGENT 0x1109 /* inherited by Adaptec */ 1634#define K_PCI_VENDOR_ZNYX 0x110D 1635#define K_PCI_VENDOR_PHOBOS 0x13D8 1636 1637static void 1638dc21143_set_speed(tulip_softc *sc, int speed) 1639{ 1640 uint32_t opmode = 0; 1641 1642 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1643 1644 switch (speed) { 1645 case ETHER_SPEED_AUTO: 1646 break; 1647 case ETHER_SPEED_10HDX: 1648 default: 1649 WRITECSR(sc, R_CSR_SIAMODE1, M_CSR14_10BT_HD); 1650 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1651 opmode = M_CSR6_SPEED_10; 1652 break; 1653 case ETHER_SPEED_10FDX: 1654 WRITECSR(sc, R_CSR_SIAMODE1, M_CSR14_10BT_FD); 1655 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1656 opmode = M_CSR6_SPEED_10 | M_CSR6_FULLDUPLEX; 1657 break; 1658 case ETHER_SPEED_100HDX: 1659 WRITECSR(sc, R_CSR_SIAMODE1, 0); 1660 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1661 opmode = M_CSR6_SPEED_100; 1662 break; 1663 case ETHER_SPEED_100FDX: 1664 WRITECSR(sc, R_CSR_SIAMODE1, 0); 1665 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1666 opmode = M_CSR6_SPEED_100 | M_CSR6_FULLDUPLEX; 1667 break; 1668 } 1669 1670 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1671 1672 opmode |= M_CSR6_MBO; 1673 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 1674 WRITECSR(sc, R_CSR_OPMODE, opmode); 1675} 1676 1677static void 1678dc21143_autonegotiate(tulip_softc *sc) 1679{ 1680 uint32_t opmode; 1681 uint32_t tempword; 1682 int count; 1683 int linkspeed; 1684 1685 linkspeed = ETHER_SPEED_UNKNOWN; 1686 1687 /* Program the media setup into the CSRs. */ 1688 /* reset SIA */ 1689 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1690 1691 /* set to speed_10, fullduplex to start_nway */ 1692 opmode = 1693 M_CSR6_SPEED_10 | 1694 M_CSR6_FULLDUPLEX | 1695 M_CSR6_MBO; 1696 WRITECSR(sc, R_CSR_OPMODE, opmode); 1697 1698 /* Choose advertised capabilities */ 1699 tempword = 1700 M_CSR14_100BASETHALFDUP | 1701 M_CSR14_100BASETFULLDUP | 1702 M_CSR14_HALFDUPLEX10BASET; 1703 WRITECSR(sc, R_CSR_SIAMODE1, tempword); 1704 1705 /* Enable autonegotiation */ 1706 tempword |= M_CSR14_AUTONEGOTIATE | 0xFFFF; 1707 WRITECSR(sc, R_CSR_SIAMODE1, tempword); 1708 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1709 WRITECSR(sc, R_CSR_OPMODE, opmode); 1710 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1711 1712 /* STATE check nway, poll until a valid 10/100mbs signal seen */ 1713 WRITECSR(sc, R_CSR_STATUS, M_CSR5_LINKPASS); /* try to clear this... */ 1714 1715 /* (Re)start negotiation */ 1716 tempword = READCSR(sc, R_CSR_SIASTATUS); 1717 tempword &=~ M_CSR12_AUTONEGARBIT; 1718 tempword |= V_CSR12_AUTONEGARBIT(0x1); 1719 1720 for (count = 0; count <= 13; count++) { 1721 tempword = READCSR(sc, R_CSR_STATUS); 1722 if (tempword & M_CSR5_LINKPASS) 1723 break; 1724 cfe_sleep(CFE_HZ/10); 1725 } 1726 1727 if (count > 13) 1728 xprintf("%s: Link autonegotiation failed\n", tulip_devname(sc)); 1729 1730 /* STATE configure nway, check to see if any abilities common to us. 1731 If they do, set to highest mode, if not, we will see if the partner 1732 will do 100mb or 10mb - then set it */ 1733 1734 tempword = READCSR(sc, R_CSR_SIASTATUS); 1735 /* clear the autonegogiate complete bit */ 1736 WRITECSR(sc, R_CSR_STATUS, M_CSR5_LINKPASS); 1737 1738 if (tempword & M_CSR12_LINKPARTNEG) { 1739 /* A link partner was negogiated... */ 1740 1741 xprintf("%s: Link speed: ", tulip_devname(sc)); 1742 if (tempword & 0x01000000) { /* 100FD */ 1743 xprintf("100BaseT FDX"); 1744 linkspeed = ETHER_SPEED_100FDX; 1745 } 1746 else if (tempword & 0x00800000) { /* 100HD */ 1747 xprintf("100BaseT HDX"); 1748 linkspeed = ETHER_SPEED_100HDX; 1749 } 1750 else if (tempword & 0x00400000) { /* 10FD */ 1751 xprintf("10BaseT FDX"); 1752 linkspeed = ETHER_SPEED_10FDX; 1753 } 1754 else if (tempword & 0x00200000) { /* 10HD */ 1755 xprintf("10BaseT HDX"); 1756 linkspeed = ETHER_SPEED_10HDX; 1757 } 1758 xprintf("\n"); 1759 } 1760 else { 1761 /* no link partner negotiation */ 1762 /* disable link for 1.3 seconds to break any existing connections */ 1763 1764 xprintf("%s: ", tulip_devname(sc)); 1765 dc21143_set_speed(sc, ETHER_SPEED_10HDX); 1766 cfe_sleep(CFE_HZ/8); 1767 1768 tempword = READCSR(sc, R_CSR_SIASTATUS); 1769 1770 if ((tempword & 0x02) == 0) { 1771 /* 100 mb signal present set to 100mb */ 1772 xprintf("No link partner... setting to 100BaseT HDX\n"); 1773 linkspeed = ETHER_SPEED_100HDX; 1774 } 1775 else if ((tempword & 0x04) == 0) { 1776 /* 10 mb signal present */ 1777 xprintf("No link partner... setting to 10BaseT HDX\n"); 1778 linkspeed = ETHER_SPEED_10HDX; 1779 } 1780 else { 1781 /* couldn't determine line speed, so set to 10mbs */ 1782 xprintf("Unknown; defaulting to 10BaseT HDX\n"); 1783 linkspeed = ETHER_SPEED_10HDX; 1784 } 1785 } 1786 1787 dc21143_set_speed(sc, linkspeed); 1788} 1789 1790static void 1791dc21143_set_loopback(tulip_softc *sc, int mode) 1792{ 1793 uint32_t v; 1794 1795 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1796 if (mode == ETHER_LOOPBACK_EXT) { 1797 /* deal with CSRs 13-15 */ 1798 } 1799 cfe_sleep(CFE_HZ/10); /* check this */ 1800 1801 /* Update the SIA registers */ 1802 v = READCSR(sc, R_CSR_SIAMODE0); 1803 WRITECSR(sc, R_CSR_SIAMODE0, v &~ 0xFFFF); 1804 v = READCSR(sc, R_CSR_SIAMODE1); 1805 WRITECSR(sc, R_CSR_SIAMODE1, v &~ 0xFFFF); 1806 v = READCSR(sc, R_CSR_SIAMODE2); 1807 WRITECSR(sc, R_CSR_SIAMODE2, v | 0xC000); /* WC of HCKR, RMP */ 1808 if (mode == ETHER_LOOPBACK_OFF) 1809 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata); 1810 else 1811 WRITECSR(sc, R_CSR_SIAMODE2, (v &~ 0xFFFF) | M_CSR15_GP_AUIBNC); 1812 1813 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1814 1815 sc->loopback = mode; 1816} 1817 1818static void 1819dc21143_hwinit(tulip_softc *sc, uint8_t srom[]) 1820{ 1821 uint16_t vendor; 1822 uint16_t leaf, block, info; 1823 uint8_t i; 1824 uint16_t gpr_control; 1825 uint32_t v; 1826 uint32_t csr6word, csr14word; 1827 1828 vendor = SROM_WORD(srom, SROM_VENDOR_INDEX); 1829 sc->phy_type = NONE; 1830 info = 0; 1831 1832 if (srom[SROM_FORMAT_INDEX] != 0 && srom[SROM_FORMAT_INDEX] <= 4) { 1833 leaf = SROM_WORD(srom, SROM_LEAF0_OFFSET_INDEX); 1834 block = leaf + 3; 1835 1836 /* Note that blocks are arranged by increasing preference. */ 1837 for (i = 0; i < srom[leaf+2]; i++) { 1838 switch (srom[block+1]) { 1839 case 0x03: 1840 sc->phy_type = MII; 1841 info = block; 1842 break; 1843 case 0x04: 1844 sc->phy_type = SYM; 1845 info = block; 1846 break; 1847 } 1848 block += (srom[block+0] & 0x7F); 1849 } 1850 } 1851#if defined(_MOUSSE_) || defined(_BCM98245CPCI_) 1852 else if (srom[SROM_FORMAT_INDEX] == 0xFF) 1853 { 1854 /* The Mousse board has no srom and returns all 1's for reads. */ 1855 sc->phy_type = MII; 1856 vendor = 0xFFFF; 1857 } 1858#endif 1859 1860 if (sc->phy_type == MII) { 1861 sc->gpdata = 0; 1862 if (vendor == K_PCI_VENDOR_COGENT) { 1863 /* Cogent/Adaptec MII (ANA-6911A). */ 1864 WRITECSR(sc, R_CSR_SIAMODE2, 0x0821 << 16); 1865 WRITECSR(sc, R_CSR_SIAMODE2, 0x0001 << 16); 1866 cfe_sleep(CFE_HZ/10); 1867 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000 << 16); 1868 cfe_sleep(CFE_HZ/2); 1869 sc->gpdata = 0; 1870 } 1871 else if (vendor == K_PCI_VENDOR_PHOBOS) { 1872 /* Phobos 430TX quad card. The advertised values appear 1873 not to work. Note that Phobos also neglects to set the 1874 0x80 bit on the block length. */ 1875#if 0 /* per EEPROM */ 1876 WRITECSR(sc, R_CSR_SIAMODE2, 0x080E << 16); 1877 WRITECSR(sc, R_CSR_SIAMODE2, 0x000E << 16); 1878 cfe_sleep(CFE_HZ/10); 1879 sc->gpdata = 0x0E; 1880#else /* following Adaptec 21143 with MII interface */ 1881 WRITECSR(sc, R_CSR_SIAMODE2, 0x0821 << 16); 1882 WRITECSR(sc, R_CSR_SIAMODE2, 0x0001 << 16); 1883 cfe_sleep(CFE_HZ/10); 1884 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000 << 16); 1885 cfe_sleep(CFE_HZ/2); 1886 sc->gpdata = 0; 1887#endif 1888 } 1889#if defined(_MOUSSE_) || defined(_BCM98245CPCI_) 1890 else if (vendor == 0xFFFF) { 1891 WRITECSR(sc, R_CSR_SIAMODE2, 0x080F << 16); 1892 sc->gpdata = 0x0; 1893 } 1894#endif 1895 mii_probe(sc); 1896 } 1897 else if (sc->phy_type == SYM) { 1898 gpr_control = SROM_WORD(srom, info+3) << 16; 1899 if (vendor == K_PCI_VENDOR_ZNYX) { 1900 /* Znyz 34xQ family of adapters */ 1901 1902 /* The ZX345Q with wake-on-LAN enabled apparently clears 1903 ANE and TAS on power up (but not cold reset) */ 1904 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFFFFFF); 1905 1906 /* The following is a reset workaround for QS/Kendin PHYs 1907 as suggested by an Intel app note. Bit 0x40000 is the 1908 PHY reset (low true) on Znyx cards. */ 1909 WRITECSR(sc, R_CSR_SIAMODE2, gpr_control | M_CSR15_GP_AUIBNC); 1910 cfe_sleep(CFE_HZ/5); 1911 WRITECSR(sc, R_CSR_SIAMODE2, 0x40000); /* release reset */ 1912 cfe_sleep(CFE_HZ/5); 1913 sc->gpdata = 0x40000; 1914 } 1915 else { 1916 WRITECSR(sc, R_CSR_SIAMODE2, gpr_control); 1917 sc->gpdata = 0; 1918 } 1919 sc->gpdata |= (SROM_WORD(srom, info+5) << 16) | M_CSR15_GP_AUIBNC; 1920 } 1921 else { 1922 /* Most 21143 cards use SYM. Match the DEC reference design. */ 1923 sc->phy_type = SYM; 1924 WRITECSR(sc, R_CSR_SIAMODE2, M_CSR15_CONFIG_GEPS_LEDS); 1925 sc->gpdata = M_CSR15_DEFAULT_VALUE; 1926 } 1927 1928 /* CSR0 - bus mode */ 1929 v = V_CSR0_SKIPLEN(0) | 1930 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 1931 M_CSR0_READMULTENAB | M_CSR0_READLINEENAB | 1932 M_CSR0_WRITEINVALENAB | 1933 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 1934#if ENDIAN_BIG 1935 if (!sc->swap) 1936 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 1937#endif 1938 WRITECSR(sc, R_CSR_BUSMODE, v); 1939 1940 /* CSR6 - operation mode */ 1941 v = M_CSR6_PORTSEL | 1942 V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72) | 1943 M_CSR6_MBO; 1944 if (sc->phy_type == SYM) 1945 v |= M_CSR6_PCSFUNC |M_CSR6_SCRAMMODE; 1946 WRITECSR(sc, R_CSR_OPMODE, v); 1947 1948 /* About to muck with the SIA, reset it.(?) */ 1949 /* WRITECSR(sc, R_CSR_SIASTATUS, 0); */ 1950 1951 /* Must shut off all transmit/receive in order to attempt to 1952 achieve Full Duplex */ 1953 csr6word = READCSR(sc, R_CSR_OPMODE); 1954 WRITECSR(sc, R_CSR_OPMODE, csr6word &~ (M_CSR6_TXSTART | M_CSR6_RXSTART)); 1955 csr6word = READCSR(sc, R_CSR_OPMODE); 1956 1957 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start)); 1958 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start)); 1959 1960 if (sc->phy_type == MII) { 1961 if (sc->linkspeed == ETHER_SPEED_AUTO) 1962 mii_autonegotiate(sc); 1963 else 1964 mii_set_speed(sc, sc->linkspeed, 0); 1965 } 1966 else { 1967 if (sc->linkspeed == ETHER_SPEED_AUTO) { 1968 dc21143_autonegotiate(sc); 1969 } 1970 else { 1971 /* disable autonegotiate so we can set full duplex to on */ 1972 WRITECSR(sc, R_CSR_SIAMODE0, 0); 1973 csr14word = READCSR(sc, R_CSR_SIAMODE1); 1974 csr14word &=~ M_CSR14_AUTONEGOTIATE; 1975 WRITECSR(sc, R_CSR_SIAMODE1, csr14word); 1976 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET); 1977 1978 dc21143_set_speed(sc, sc->linkspeed); 1979 } 1980 } 1981} 1982 1983 1984static void 1985dc21140_set_speed(tulip_softc *sc, int speed, int autoneg) 1986{ 1987 mii_set_speed(sc, speed, autoneg); 1988} 1989 1990static void 1991dc21140_set_loopback(tulip_softc *sc, int mode) 1992{ 1993 if (mode == ETHER_LOOPBACK_EXT) { 1994 xprintf("%s: external loopback mode NYI\n", tulip_devname(sc)); 1995 mode = ETHER_LOOPBACK_OFF; 1996 } 1997 else if (mode != ETHER_LOOPBACK_INT) 1998 mode = ETHER_LOOPBACK_OFF; 1999 2000 sc->loopback = mode; 2001} 2002 2003static void 2004dc21140_hwinit(tulip_softc *sc, uint8_t srom[]) 2005{ 2006 uint16_t vendor; 2007 uint16_t leaf, block; 2008 uint8_t i; 2009 uint8_t gpr_control, gpr_data; 2010 uint32_t v; 2011 uint32_t opmode; 2012 2013 /* Assume that we will use an MII or a SYM interface for 100 Mbps 2014 operation and default to MII, the most common arrangement for 2015 21140 boards. */ 2016 2017 vendor = SROM_WORD(srom, SROM_VENDOR_INDEX); 2018 if (srom[SROM_FORMAT_INDEX] == 0 || srom[SROM_FORMAT_INDEX] > 4) { 2019 /* Most 21140 cards use MII. Match the DEC reference design. */ 2020 gpr_control = 0x1F; 2021 gpr_data = 0x00; 2022 sc->phy_type = MII; 2023 } 2024 else if (srom[SROM_ADDR_INDEX+0] == 0x00 && srom[SROM_ADDR_INDEX+1] == 0xC0 2025 && srom[SROM_ADDR_INDEX+2] == 0x95) { 2026 /* Znyx 34x 21140 cards implement only an MII interface but 2027 the ROM uses version 1 encoding, which has no provision for 2028 MII blocks. Also, an additional copy of the MAC address 2029 appears at the usual location for the vendor id; 00-C0-95 2030 is Znyx' IEEE OUI. */ 2031 gpr_control = 0x00; /* All inputs, per Znyx docs */ 2032 gpr_data = 0x00; 2033 sc->phy_type = MII; 2034 } 2035 else { 2036 leaf = SROM_WORD(srom, SROM_LEAF0_OFFSET_INDEX); 2037 gpr_control = srom[leaf+2]; 2038 gpr_data = 0; 2039 block = leaf + 4; 2040 sc->phy_type = NONE; 2041 2042 /* Note that blocks are arranged by increasing preference. */ 2043 for (i = 0; i < srom[leaf+3]; i++) { 2044 if ((srom[block] & 0x80) == 0) { 2045 if (srom[block] == 0x03 || srom[block] == 0x05) { 2046 gpr_data = srom[block+1]; 2047 sc->phy_type = SYM; 2048 } 2049 block += 4; 2050 } 2051 else { 2052 if (srom[block+1] == 0x01) { 2053 gpr_data = 0x00; 2054 sc->phy_type = MII; 2055 } 2056 else if (srom[block+1] == 0x00 && 2057 (srom[block+2] == 0x03 || srom[block+2] == 0x05)) { 2058 gpr_data = srom[block+3]; 2059 sc->phy_type = SYM; 2060 } 2061 block += (srom[block] & 0x7F) + 1; 2062 } 2063 if (sc->phy_type == NONE) { 2064 sc->phy_type = MII; /* Try MII */ 2065 } 2066 } 2067 } 2068 2069 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL); 2070 RESET_ADAPTER(sc); 2071 2072 WRITECSR(sc, R_CSR_GENPORT, M_CSR12_CONTROL | gpr_control); 2073 cfe_nsleep(100); /* CS setup (Tcss=100) */ 2074 WRITECSR(sc, R_CSR_GENPORT, gpr_data); /* setup PHY */ 2075 2076 if (sc->phy_type == MII) { 2077 mii_probe(sc); 2078 } 2079 2080 /* CSR0 - bus mode */ 2081 v = V_CSR0_SKIPLEN(0) | 2082 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 2083 M_CSR0_READMULTENAB | M_CSR0_READLINEENAB | 2084 M_CSR0_WRITEINVALENAB | 2085 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 2086#if ENDIAN_BIG 2087 if (!sc->swap) 2088 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 2089#endif 2090 WRITECSR(sc, R_CSR_BUSMODE, v); 2091 2092 /* CSR6 - operation mode */ 2093 v = M_CSR6_PORTSEL | 2094 V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72) | 2095 M_CSR6_MBO; 2096 WRITECSR(sc, R_CSR_OPMODE, v); 2097 2098 /* Must shut off all transmit/receive in order to attempt to 2099 achieve Full Duplex */ 2100 opmode = READCSR(sc, R_CSR_OPMODE); 2101 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART)); 2102 opmode = READCSR(sc, R_CSR_OPMODE); 2103 2104 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start)); 2105 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start)); 2106 2107 if (sc->phy_type == MII) { 2108 if (sc->linkspeed == ETHER_SPEED_AUTO) 2109 mii_autonegotiate(sc); 2110 else 2111 mii_set_speed(sc, sc->linkspeed, 0); 2112 } 2113 else { 2114 /* XXX The 21140 requires a soft reset after changing PORTSEL. 2115 For now, remain committed to the SYM port (100 Mb/s) */ 2116 switch (sc->linkspeed) { 2117 default: 2118 sc->linkspeed = ETHER_SPEED_100HDX; /* for now */ 2119 /* fall through */ 2120 case ETHER_SPEED_100HDX: 2121 opmode |= M_CSR6_SPEED_100; 2122 break; 2123 case ETHER_SPEED_100FDX: 2124 opmode |= M_CSR6_SPEED_100 | M_CSR6_FULLDUPLEX; 2125 break; 2126 } 2127 2128 /* XXX Need to reset and reinitialize if we choose SPEED_10 above */ 2129 WRITECSR(sc, R_CSR_OPMODE, opmode); 2130 } 2131} 2132 2133 2134static void 2135dc21041_set_speed(tulip_softc *sc, int speed) 2136{ 2137 uint32_t opmode = 0; 2138 2139 WRITECSR(sc, R_CSR_SIAMODE0, 0); 2140 2141 /* For now, always force 10BT, HDX (21041, Table 3-62) */ 2142 switch (speed) { 2143 case ETHER_SPEED_10HDX: 2144 default: 2145 WRITECSR(sc, R_CSR_SIAMODE1, 0x7F3F); 2146 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 2147 opmode = M_CSR6_SPEED_10; 2148 break; 2149 } 2150 2151 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | M_CSR13_CONN_NOT_RESET); 2152 cfe_sleep(CFE_HZ/10); 2153 2154 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 2155 WRITECSR(sc, R_CSR_OPMODE, opmode); 2156} 2157 2158static void 2159dc21041_set_loopback(tulip_softc *sc, int mode) 2160{ 2161 /* For now, always assume 10BT */ 2162 uint32_t mode0; 2163 2164 WRITECSR(sc, R_CSR_SIAMODE0, 0); 2165 cfe_sleep(CFE_HZ/10); /* check this */ 2166 2167 /* Update the SIA registers */ 2168 if (mode == ETHER_LOOPBACK_EXT) { 2169 /* NB: this is really just internal but through the 10BT endec */ 2170 WRITECSR(sc, R_CSR_SIAMODE1, 0x7A3F); 2171 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 2172 mode0 = 0; 2173 } 2174 else if (mode == ETHER_LOOPBACK_INT) { 2175 /* MAC internal loopback, no SIA */ 2176 WRITECSR(sc, R_CSR_SIAMODE1, 0x0000); 2177 WRITECSR(sc, R_CSR_SIAMODE2, 0x000E); 2178 mode0 = M_CSR13_CONN_AUI_10BT; 2179 } 2180 else { 2181 mode = ETHER_LOOPBACK_OFF; 2182 WRITECSR(sc, R_CSR_SIAMODE1, 0x7F3F); 2183 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 2184 mode0 = 0; 2185 } 2186 2187 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | mode0 | M_CSR13_CONN_NOT_RESET ); 2188 2189 sc->loopback = mode; 2190} 2191 2192static void 2193dc21041_hwinit(tulip_softc *sc, uint8_t srom[]) 2194{ 2195 uint32_t v; 2196 2197 sc->phy_type = SRL; 2198 2199 /* CSR0 - bus mode */ 2200 v = V_CSR0_SKIPLEN(0) | 2201 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 2202 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 2203#if ENDIAN_BIG 2204 if (!sc->swap) 2205 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 2206#endif 2207 WRITECSR(sc, R_CSR_BUSMODE, v); 2208 2209 WRITECSR(sc, R_CSR_INTMASK, 0); 2210 2211 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start)); 2212 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start)); 2213 2214 /* For now, always force 10BT, HDX (21041, Table 3-62) */ 2215 dc21041_set_speed(sc, ETHER_SPEED_10HDX); 2216} 2217 2218 2219static void 2220dc21040_set_speed(tulip_softc *sc, int speed) 2221{ 2222 uint32_t opmode = 0; 2223 2224 WRITECSR(sc, R_CSR_SIAMODE0, 0); 2225 2226 /* For now, force 10BT, HDX unless FDX requested (21040, Table 3-53) */ 2227 switch (speed) { 2228 case ETHER_SPEED_10HDX: 2229 default: 2230 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFF); 2231 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2232 opmode = 0; 2233 break; 2234 case ETHER_SPEED_10FDX: 2235 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFD); 2236 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2237 opmode = M_CSR6_FULLDUPLEX; 2238 break; 2239 } 2240 2241 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | M_CSR13_CONN_NOT_RESET); 2242 cfe_sleep(CFE_HZ/10); 2243 2244 opmode |= V_CSR6_THRESHCONTROL(K_CSR6_TXTHRES_128_72); 2245 WRITECSR(sc, R_CSR_OPMODE, opmode); 2246} 2247 2248static void 2249dc21040_set_loopback(tulip_softc *sc, int mode) 2250{ 2251 WRITECSR(sc, R_CSR_SIAMODE0, 0); 2252 cfe_sleep(CFE_HZ/10); /* check this */ 2253 2254 /* Update the SIA registers */ 2255 if (mode == ETHER_LOOPBACK_EXT) { 2256 /* NB: this is on-chip loopback through the 10BT endec */ 2257 WRITECSR(sc, R_CSR_SIAMODE1, 0xFEFB); 2258 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008); 2259 } 2260 else if (mode == ETHER_LOOPBACK_INT) { 2261 /* MAC internal loopback, no SIA */ 2262 WRITECSR(sc, R_CSR_SIAMODE1, 0x0000); 2263 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2264 } 2265 else { 2266 mode = ETHER_LOOPBACK_OFF; 2267 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFF); 2268 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000); 2269 } 2270 2271 WRITECSR(sc, R_CSR_SIAMODE0, 0x8F00 | M_CSR13_CONN_NOT_RESET ); 2272 2273 sc->loopback = mode; 2274} 2275 2276static void 2277dc21040_hwinit(tulip_softc *sc, uint8_t srom[]) 2278{ 2279 uint32_t v; 2280 2281 sc->phy_type = SRL; 2282 2283 /* CSR0 - bus mode */ 2284 v = V_CSR0_SKIPLEN(0) | 2285 V_CSR0_CACHEALIGN(K_CSR0_ALIGN32) | 2286 V_CSR0_BURSTLEN(K_CSR0_BURSTANY); 2287#if ENDIAN_BIG 2288 if (!sc->swap) 2289 v |= M_CSR0_BIGENDIAN; /* big-endian data serialization */ 2290#endif 2291 WRITECSR(sc, R_CSR_BUSMODE, v); 2292 2293 WRITECSR(sc, R_CSR_INTMASK, 0); 2294 2295 dc21040_set_speed(sc, sc->linkspeed); 2296} 2297 2298 2299static void 2300dm9102_hwinit(tulip_softc *sc, uint8_t srom[]) 2301{ 2302 uint8_t gpr_control, gpr_data; 2303 uint32_t v; 2304 uint32_t opmode; 2305 2306 gpr_control = 0x80; 2307 gpr_data = 0x00; 2308 sc->phy_type = MII; /* DM9102(A) has built-in PHY with MII */ 2309 2310 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL); 2311 RESET_ADAPTER(sc); 2312 2313 WRITECSR(sc, R_CSR_GENPORT, M_CSR12_CONTROL | gpr_control); 2314 cfe_nsleep(100); /* CS setup (Tcss=100) */ 2315 WRITECSR(sc, R_CSR_GENPORT, gpr_data); /* setup PHY */ 2316 2317 mii_probe(sc); 2318 2319 /* CSR0 - bus mode. The DM9102(A) requires all bits clear. */ 2320 v = 0; 2321 WRITECSR(sc, R_CSR_BUSMODE, v); 2322 2323 /* CSR6 - operation mode. 9102 apparently requires store-and-forward */ 2324 v = M_CSR6_PORTSEL | 2325 M_CSR6_STOREFWD | 2326 M_CSR6_MBO; 2327 WRITECSR(sc, R_CSR_OPMODE, v); 2328 2329 /* Must shut off all transmit/receive in order to attempt to 2330 achieve Full Duplex */ 2331 opmode = READCSR(sc, R_CSR_OPMODE); 2332 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART)); 2333 opmode = READCSR(sc, R_CSR_OPMODE); 2334 2335 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start)); 2336 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start)); 2337 2338 if (sc->linkspeed == ETHER_SPEED_AUTO) 2339 mii_autonegotiate(sc); 2340 else 2341 mii_set_speed(sc, sc->linkspeed, 0); 2342} 2343 2344static void 2345dm9102_set_speed(tulip_softc *sc, int speed, int autoneg) 2346{ 2347 dc21140_set_speed(sc, speed, autoneg); 2348} 2349 2350static void 2351dm9102_set_loopback(tulip_softc *sc, int mode) 2352{ 2353 dc21140_set_loopback(sc, mode); 2354} 2355 2356 2357static uint16_t 2358pnic_mii_read_register(tulip_softc *sc, unsigned int index) 2359{ 2360 uint32_t cmd, csr20; 2361 uint16_t data; 2362 2363 cmd = M_CSR20_BUSY 2364 | V_CSR20_OPCODE(K_CSR20_OPCODE_READ) 2365 | V_CSR20_PHYADDR(sc->phy_addr) 2366 | V_CSR20_REGADDR(index) 2367 | M_CSR20_MBO; 2368 WRITECSR(sc, R_CSR_MIIM, cmd); 2369 for (;;) { 2370 csr20 = READCSR(sc, R_CSR_MIIM); 2371 if ((csr20 & M_CSR20_BUSY) == 0) 2372 break; 2373 POLL(); /* XXX need a timeout */ 2374 } 2375 data = G_CSR20_DATA(csr20); 2376 2377 return data; 2378} 2379 2380 2381static void 2382pnic_mii_write_register(tulip_softc *sc, unsigned int index, uint16_t value) 2383{ 2384 uint32_t cmd, csr20; 2385 2386 cmd = M_CSR20_BUSY 2387 | V_CSR20_OPCODE(K_CSR20_OPCODE_WRITE) 2388 | V_CSR20_PHYADDR(sc->phy_addr) 2389 | V_CSR20_REGADDR(index) 2390 | V_CSR20_DATA(value) 2391 | M_CSR20_MBO; 2392 WRITECSR(sc, R_CSR_MIIM, cmd); 2393 for (;;) { 2394 csr20 = READCSR(sc, R_CSR_MIIM); 2395 if ((csr20 & M_CSR20_BUSY) == 0) 2396 break; 2397 POLL(); /* XXX need a timeout */ 2398 } 2399} 2400 2401static void 2402pnic_hwinit(tulip_softc *sc, uint8_t srom[]) 2403{ 2404 uint8_t gpr_control; 2405 uint32_t v; 2406 uint32_t opmode; 2407 2408 sc->mii_read_register = pnic_mii_read_register; 2409 sc->mii_write_register = pnic_mii_write_register; 2410 2411 gpr_control = 0x32; /* XXX Correct ??? Make symbolic. */ 2412 sc->phy_type = MII; /* PNIC has built-in PHY with MII */ 2413 2414 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL); 2415 RESET_ADAPTER(sc); 2416 2417 /* from NetBSD tulip.c (maybe) */ 2418 WRITECSR(sc, R_CSR_GENPORT, gpr_control); 2419 WRITECSR(sc, R_CSR_ENDEC, M_CSR15_EG_JDIS); 2420 2421 mii_probe(sc); 2422 2423 /* CSR0 - bus mode. The PNIC requires a magic bit set. */ 2424 v = 0x04000000; 2425 WRITECSR(sc, R_CSR_BUSMODE, v); 2426 2427 /* CSR6 - operation mode. PNIC may require store-and-forward */ 2428 v = M_CSR6_PORTSEL | 2429 M_CSR6_STOREFWD | 2430 M_CSR6_MBO; 2431 WRITECSR(sc, R_CSR_OPMODE, v); 2432 2433 /* Must shut off all transmit/receive in order to attempt to 2434 achieve Full Duplex */ 2435 opmode = READCSR(sc, R_CSR_OPMODE); 2436 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART)); 2437 opmode = READCSR(sc, R_CSR_OPMODE); 2438 2439 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start)); 2440 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start)); 2441 2442 if (sc->linkspeed == ETHER_SPEED_AUTO) 2443 mii_autonegotiate(sc); 2444 else 2445 mii_set_speed(sc, sc->linkspeed, 0); 2446 2447 /* Empirically, PNIC requires store-and-forward at 100 Mbs */ 2448 opmode = READCSR(sc, R_CSR_OPMODE); 2449 opmode |= M_CSR6_STOREFWD; 2450 WRITECSR(sc, R_CSR_OPMODE, opmode); 2451} 2452 2453static void 2454pnic_set_speed(tulip_softc *sc, int speed, int autoneg) 2455{ 2456 dc21140_set_speed(sc, speed, autoneg); 2457} 2458 2459static void 2460pnic_set_loopback(tulip_softc *sc, int mode) 2461{ 2462 dc21140_set_loopback(sc, mode); 2463} 2464 2465 2466static void 2467tulip_hwinit(tulip_softc *sc) 2468{ 2469 if (sc->state == eth_state_uninit) { 2470 uint8_t srom[SROM_SIZE]; 2471 2472 /* Set default values */ 2473 sc->mii_read_register = mii_read_register; 2474 sc->mii_write_register = mii_write_register; 2475 2476 /* Wake-on-LAN apparently powers up with PORTSEL = 1 */ 2477 WRITECSR(sc, R_CSR_OPMODE, 2478 READCSR(sc, R_CSR_OPMODE) &~ M_CSR6_PORTSEL); 2479 2480 RESET_ADAPTER(sc); 2481 sc->state = eth_state_off; 2482 sc->bus_errors = 0; 2483 2484 rom_read_all(sc, srom); /* XXX read just once? */ 2485 rom_dump(srom); 2486 (void)srom_write_word; /* XXX suppress compiler warning */ 2487 2488 switch (sc->device) { 2489 case K_CHIP_DC21040: 2490 dc21040_hwinit(sc, srom); 2491 break; 2492 case K_CHIP_DC21041: 2493 dc21041_hwinit(sc, srom); 2494 break; 2495 case K_CHIP_DC21140: 2496 dc21140_hwinit(sc, srom); 2497 break; 2498 case K_CHIP_DC21143: 2499 dc21143_hwinit(sc, srom); 2500 break; 2501 case K_CHIP_DM9102: 2502 dm9102_hwinit(sc, srom); 2503 break; 2504 case K_CHIP_82C169: 2505 pnic_hwinit(sc, srom); 2506 default: 2507 break; 2508 } 2509 } 2510} 2511 2512static void 2513tulip_setaddr(tulip_softc *sc) 2514{ 2515 int idx; 2516 tulip_cam *cam; 2517 eth_pkt_t *pkt; 2518 2519 pkt = eth_alloc_pkt(sc); 2520 if (pkt) { 2521 pkt->length = CAM_SETUP_BUFFER_SIZE; 2522 cam = (tulip_cam *) pkt->buffer; 2523 2524#if ENDIAN_BIG 2525 cam->p.physical[0][0] = (((uint32_t) sc->hwaddr[0] << 8) | 2526 (uint32_t) sc->hwaddr[1]) << 16; 2527 cam->p.physical[0][1] = (((uint32_t) sc->hwaddr[2] << 8) | 2528 (uint32_t) sc->hwaddr[3]) << 16; 2529 cam->p.physical[0][2] = (((uint32_t) sc->hwaddr[4] << 8) | 2530 (uint32_t) sc->hwaddr[5]) << 16; 2531 for (idx = 1; idx < CAM_PERFECT_ENTRIES; idx++) { 2532 cam->p.physical[idx][0] = 0xFFFF0000; 2533 cam->p.physical[idx][1] = 0xFFFF0000; 2534 cam->p.physical[idx][2] = 0xFFFF0000; 2535 } 2536#else 2537 cam->p.physical[0][0] = ((uint32_t) sc->hwaddr[0]) | 2538 (((uint32_t) sc->hwaddr[1]) << 8); 2539 cam->p.physical[0][1] = ((uint32_t) sc->hwaddr[2]) | 2540 (((uint32_t) sc->hwaddr[3]) << 8); 2541 cam->p.physical[0][2] = ((uint32_t) sc->hwaddr[4]) | 2542 (((uint32_t) sc->hwaddr[5]) << 8); 2543 for (idx = 1; idx < CAM_PERFECT_ENTRIES; idx++) { 2544 cam->p.physical[idx][0] = 0x0000FFFF; 2545 cam->p.physical[idx][1] = 0x0000FFFF; 2546 cam->p.physical[idx][2] = 0x0000FFFF; 2547 } 2548#endif 2549 2550 pkt->flags |= ETH_TX_SETUP; 2551 sc->state = eth_state_setup; 2552 if (tulip_transmit(sc, pkt) != 0) { 2553 xprintf("%s: failed setup\n", tulip_devname(sc)); 2554 dumpstat(sc); 2555 eth_free_pkt(sc, pkt); 2556 } 2557 /* Note: the PNIC apparently will not signal TXINT for this setup 2558 packet, but will signal TXBUFUNAVAIL. */ 2559 } 2560} 2561 2562static void 2563tulip_setspeed(tulip_softc *sc, int speed) 2564{ 2565 switch (sc->device) { 2566 case K_CHIP_DC21040: 2567 dc21040_set_speed(sc, speed); 2568 break; 2569 case K_CHIP_DC21041: 2570 dc21041_set_speed(sc, speed); 2571 break; 2572 case K_CHIP_DC21140: 2573 dc21140_set_speed(sc, speed, 0); 2574 break; 2575 case K_CHIP_DC21143: 2576 dc21143_set_speed(sc, speed); 2577 break; 2578 case K_CHIP_DM9102: 2579 dm9102_set_speed(sc, speed, 0); 2580 break; 2581 case K_CHIP_82C169: 2582 pnic_set_speed(sc, speed, 0); 2583 break; 2584 default: 2585 break; 2586 } 2587} 2588 2589static void 2590tulip_setloopback(tulip_softc *sc, int mode) 2591{ 2592 switch (sc->device) { 2593 case K_CHIP_DC21040: 2594 dc21040_set_loopback(sc, mode); 2595 break; 2596 case K_CHIP_DC21041: 2597 dc21041_set_loopback(sc, mode); 2598 break; 2599 case K_CHIP_DC21140: 2600 dc21140_set_loopback(sc, mode); 2601 break; 2602 case K_CHIP_DC21143: 2603 dc21143_set_loopback(sc, mode); 2604 break; 2605 case K_CHIP_DM9102: 2606 dm9102_set_loopback(sc, mode); 2607 break; 2608 case K_CHIP_82C169: 2609 pnic_set_loopback(sc, mode); 2610 break; 2611 default: 2612 break; 2613 } 2614 cfe_sleep(CFE_HZ/10); 2615} 2616 2617 2618static void 2619tulip_isr(void *arg) 2620{ 2621 uint32_t status; 2622 uint32_t csr5; 2623 tulip_softc *sc = (tulip_softc *)arg; 2624 2625#if IPOLL 2626 sc->interrupts++; 2627#endif 2628 2629 for (;;) { 2630 2631 /* Read the interrupt status. */ 2632 csr5 = READCSR(sc, R_CSR_STATUS); 2633 status = csr5 & ( 2634 M_CSR5_RXINT | M_CSR5_TXINT | M_CSR5_TXBUFUNAVAIL | 2635 M_CSR5_RXBUFUNAVAIL | M_CSR5_TXUNDERFLOW | 2636 M_CSR5_FATALBUSERROR); 2637 2638 /* if there are no more interrupts, leave now. */ 2639 if (status == 0) break; 2640 2641 /* Clear the pending interrupt. */ 2642 WRITECSR(sc, R_CSR_STATUS, status); 2643 2644 /* Now, test each unmasked bit in the interrupt register and 2645 handle each interrupt type appropriately. */ 2646 2647 if (status & M_CSR5_FATALBUSERROR) { 2648 WRITECSR(sc, R_CSR_INTMASK, 0); 2649 2650 xprintf("%s: bus error %02x\n", 2651 tulip_devname(sc), G_CSR5_ERRORBITS(csr5)); 2652 dumpstat(sc); 2653 sc->bus_errors++; 2654 if (sc->bus_errors >= 2) { 2655 dumpcsrs(sc); 2656 RESET_ADAPTER(sc); 2657 sc->state = eth_state_off; 2658 sc->bus_errors = 0; 2659 status = 0; 2660 } 2661#if IPOLL 2662 else 2663 WRITECSR(sc, R_CSR_INTMASK, sc->intmask); 2664#endif 2665 } 2666 2667 if (status & M_CSR5_RXINT) { 2668#if IPOLL 2669 sc->rx_interrupts++; 2670#endif 2671 tulip_procrxring(sc); 2672 } 2673 2674 if (status & (M_CSR5_TXINT | M_CSR5_TXBUFUNAVAIL)) { 2675#if IPOLL 2676 sc->tx_interrupts++; 2677#endif 2678 tulip_proctxring(sc); 2679 } 2680 2681 if (status & (M_CSR5_TXUNDERFLOW | M_CSR5_RXBUFUNAVAIL)) { 2682 if (status & M_CSR5_TXUNDERFLOW) { 2683 xprintf("%s: tx underrun, %08x\n", tulip_devname(sc), csr5); 2684 /* Try to restart */ 2685 WRITECSR(sc, R_CSR_TXPOLL, 1); 2686 } 2687 if (status & M_CSR5_RXBUFUNAVAIL) { 2688 /* Try to restart */ 2689 WRITECSR(sc, R_CSR_RXPOLL, 1); 2690 } 2691 } 2692 } 2693} 2694 2695 2696static void 2697tulip_start(tulip_softc *sc) 2698{ 2699 uint32_t opmode; 2700 2701 tulip_hwinit(sc); 2702 2703 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start)); 2704 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start)); 2705 2706 opmode = READCSR(sc, R_CSR_OPMODE); 2707 opmode &=~ M_CSR6_OPMODE; /* no loopback */ 2708 if (sc->loopback != ETHER_LOOPBACK_OFF) { 2709 opmode &=~ M_CSR6_FULLDUPLEX; 2710 opmode |= M_CSR6_PORTSEL; 2711 if (sc->loopback == ETHER_LOOPBACK_EXT) 2712 opmode |= M_CSR6_EXTLOOPBACK; 2713 else 2714 opmode |= M_CSR6_INTLOOPBACK; 2715 } 2716 2717 sc->intmask = 0; 2718 WRITECSR(sc, R_CSR_INTMASK, 0); /* no interrupts */ 2719 WRITECSR(sc, R_CSR_STATUS, 0x1FFFF); /* clear any pending */ 2720 READCSR(sc, R_CSR_STATUS); /* push the write */ 2721 2722 sc->interrupts = 0; 2723 sc->rx_interrupts = sc->tx_interrupts = 0; 2724 2725#if IPOLL 2726 cfe_request_irq(sc->irq, tulip_isr, sc, CFE_IRQ_FLAGS_SHARED, 0); 2727 2728 sc->intmask = M_CSR7_RXINT | M_CSR7_TXINT | M_CSR7_TXBUFUNAVAIL | 2729 M_CSR7_NORMALINT; 2730 sc->intmask |= M_CSR7_FATALBUSERROR | M_CSR7_TXUNDERFLOW | 2731 M_CSR7_ABNORMALINT; 2732 WRITECSR(sc, R_CSR_INTMASK, sc->intmask); 2733#endif 2734 2735 if (sc->loopback == ETHER_LOOPBACK_OFF) { 2736 opmode |= M_CSR6_TXSTART; 2737 WRITECSR(sc, R_CSR_OPMODE, opmode); 2738 tulip_setaddr(sc); 2739 } 2740 else { 2741 opmode |= M_CSR6_TXSTART | M_CSR6_RXSTART; 2742 WRITECSR(sc, R_CSR_OPMODE, opmode); 2743 } 2744} 2745 2746static void 2747tulip_stop(tulip_softc *sc) 2748{ 2749 uint32_t opmode; 2750 uint32_t status; 2751 int count; 2752 2753 WRITECSR(sc, R_CSR_INTMASK, 0); 2754 sc->intmask = 0; 2755#if IPOLL 2756 cfe_free_irq(sc->irq, 0); 2757#endif 2758 WRITECSR(sc, R_CSR_STATUS, 0x1FFFF); 2759 opmode = READCSR(sc, R_CSR_OPMODE); 2760 opmode &=~ (M_CSR6_TXSTART | M_CSR6_RXSTART); 2761 WRITECSR(sc, R_CSR_OPMODE, opmode); 2762 2763 /* wait for any DMA activity to terminate */ 2764 for (count = 0; count <= 13; count++) { 2765 status = READCSR(sc, R_CSR_STATUS); 2766 if ((status & (M_CSR5_RXPROCSTATE | M_CSR5_TXPROCSTATE)) == 0) 2767 break; 2768 cfe_sleep(CFE_HZ/10); 2769 } 2770 if (count > 13) { 2771 xprintf("%s: idle state not achieved\n", tulip_devname(sc)); 2772 dumpstat(sc); 2773 RESET_ADAPTER(sc); 2774 sc->state = eth_state_uninit; 2775#if 1 2776 sc->linkspeed = ETHER_SPEED_AUTO; 2777#endif 2778 } 2779 else if (sc->loopback != ETHER_LOOPBACK_OFF) { 2780 tulip_setloopback(sc, ETHER_LOOPBACK_OFF); 2781 opmode &=~ M_CSR6_OPMODE; 2782 WRITECSR(sc, R_CSR_OPMODE, opmode); 2783 } 2784 2785 if (sc->outpkts > 1) { 2786 /* heuristic: suppress stats for initial mode changes */ 2787 xprintf("%s: %d sent, %d received, %d interrupts\n", 2788 tulip_devname(sc), sc->outpkts, sc->inpkts, sc->interrupts); 2789 xprintf(" %d rx interrupts, %d tx interrupts\n", 2790 sc->rx_interrupts, sc->tx_interrupts); 2791 } 2792} 2793 2794 2795/* ********************************************************************* 2796 * Declarations for CFE Device Driver Interface routines 2797 ********************************************************************* */ 2798 2799static int tulip_ether_open(cfe_devctx_t *ctx); 2800static int tulip_ether_read(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 2801static int tulip_ether_inpstat(cfe_devctx_t *ctx,iocb_inpstat_t *inpstat); 2802static int tulip_ether_write(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 2803static int tulip_ether_ioctl(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 2804static int tulip_ether_close(cfe_devctx_t *ctx); 2805static void tulip_ether_poll(cfe_devctx_t *ctx, int64_t ticks); 2806#if 0 2807static void tulip_ether_reset(void *softc); 2808#endif 2809 2810/* ********************************************************************* 2811 * CFE Device Driver dispatch structure 2812 ********************************************************************* */ 2813 2814const static cfe_devdisp_t tulip_ether_dispatch = { 2815 tulip_ether_open, 2816 tulip_ether_read, 2817 tulip_ether_inpstat, 2818 tulip_ether_write, 2819 tulip_ether_ioctl, 2820 tulip_ether_close, 2821 tulip_ether_poll, 2822 NULL /* tulip_ether_reset */ 2823}; 2824 2825/* ********************************************************************* 2826 * CFE Device Driver descriptor 2827 ********************************************************************* */ 2828 2829const cfe_driver_t tulipdrv = { 2830 "DC21x4x Ethernet", 2831 "eth", 2832 CFE_DEV_NETWORK, 2833 &tulip_ether_dispatch, 2834 tulip_ether_probe 2835}; 2836 2837 2838static int 2839tulip_ether_attach(cfe_driver_t *drv, 2840 pcitag_t tag, int index, uint8_t hwaddr[]) 2841{ 2842 tulip_softc *sc; 2843 uint32_t device; 2844 uint32_t class; 2845 uint32_t reg; 2846 phys_addr_t pa; 2847 const char *devname; 2848 char descr[100]; 2849 uint8_t romaddr[ENET_ADDR_LEN]; 2850 2851 device = pci_conf_read(tag, R_CFG_CFID); 2852 class = pci_conf_read(tag, R_CFG_CFRV); 2853 2854 reg = pci_conf_read(tag, R_CFG_CPMS); 2855 2856 reg = pci_conf_read(tag, R_CFG_CFDD); 2857 pci_conf_write(tag, R_CFG_CFDD, 0); 2858 reg = pci_conf_read(tag, R_CFG_CFDD); 2859 2860#if 1 2861 /* Use memory space for the CSRs */ 2862 pci_map_mem(tag, R_CFG_CBMA, CSR_MATCH_MODE, &pa); 2863#else 2864 /* Use i/o space for the CSRs */ 2865 pci_map_io(tag, R_CFG_CBIO, CSR_MATCH_MODE, &pa); 2866#endif 2867 2868 sc = (tulip_softc *) KMALLOC(sizeof(tulip_softc), 0); 2869 if (sc == NULL) { 2870 xprintf("DC21x4x: No memory to complete probe\n"); 2871 return 0; 2872 } 2873 memset(sc, 0, sizeof(*sc)); 2874 2875 sc->membase = (uint32_t)pa; 2876 sc->irq = pci_conf_read(tag, R_CFG_CFIT) & 0xFF; 2877 2878 sc->tag = tag; 2879 sc->device = K_CHIP_UNKNOWN; 2880 switch (PCI_VENDOR(device)) { 2881 case K_PCI_VENDOR_DEC: 2882 switch (PCI_PRODUCT(device)) { 2883 case K_PCI_ID_DC21040: 2884 sc->device = K_CHIP_DC21040; break; 2885 case K_PCI_ID_DC21041: 2886 sc->device = K_CHIP_DC21041; break; 2887 case K_PCI_ID_DC21140: 2888 sc->device = K_CHIP_DC21140; break; 2889 case K_PCI_ID_DC21143: 2890 sc->device = K_CHIP_DC21143; break; 2891 } 2892 break; 2893 case K_PCI_VENDOR_DAVICOM: 2894 switch (PCI_PRODUCT(device)) { 2895 case K_PCI_ID_DM9102: 2896 sc->device = K_CHIP_DM9102; break; 2897 } 2898 break; 2899 case K_PCI_VENDOR_LITEON: 2900 switch (PCI_PRODUCT(device)) { 2901 case K_PCI_ID_82C169: 2902 sc->device = K_CHIP_82C169; break; 2903 } 2904 break; 2905 } 2906 sc->revision = PCI_REVISION(class); 2907 sc->devctx = NULL; 2908 2909#if 1 2910 sc->linkspeed = ETHER_SPEED_AUTO; /* select autonegotiation */ 2911#else 2912 sc->linkspeed = ETHER_SPEED_100FDX; /* 100 Mbps, full duplex */ 2913#endif 2914 sc->loopback = ETHER_LOOPBACK_OFF; 2915 memcpy(sc->hwaddr, hwaddr, ENET_ADDR_LEN); 2916 2917 switch (sc->device) { 2918 case K_CHIP_DM9102: 2919 /* Davicom 9102 has no endian control bit */ 2920#if ENDIAN_BIG 2921 sc->swap = 1; 2922 sc->rxdscr_owned = swap4(M_RDES0_OWNADAP); 2923 sc->txdscr_owned = swap4(M_TDES0_OWNADAP); 2924#else 2925 sc->swap = 0; 2926 sc->rxdscr_owned = M_RDES0_OWNADAP; 2927 sc->txdscr_owned = M_TDES0_OWNADAP; 2928#endif 2929 sc->endian = M_MATCH_BYTES; 2930 /* ... and no ring mode */ 2931 sc->rxdscr_ctrl = M_RDES1_CHAINED; 2932 sc->txdscr_ctrl = M_TDES1_CHAINED; 2933 break; 2934 case K_CHIP_82C169: 2935 /* Empirically, LiteOn PNIC has a broken endian control bit. */ 2936#if ENDIAN_BIG 2937 sc->swap = 1; 2938 sc->rxdscr_owned = swap4(M_RDES0_OWNADAP); 2939 sc->txdscr_owned = swap4(M_TDES0_OWNADAP); 2940#else 2941 sc->swap = 0; 2942 sc->rxdscr_owned = M_RDES0_OWNADAP; 2943 sc->txdscr_owned = M_TDES0_OWNADAP; 2944#endif 2945 sc->endian = M_MATCH_BYTES; 2946 break; 2947 default: 2948#if (ENDIAN_BIG && MATCH_BYTES) 2949 sc->swap = 1; 2950 sc->rxdscr_owned = swap4(M_RDES0_OWNADAP); 2951 sc->txdscr_owned = swap4(M_TDES0_OWNADAP); 2952 sc->endian = M_MATCH_BYTES; 2953#else 2954 sc->swap = 0; 2955 sc->rxdscr_owned = M_RDES0_OWNADAP; 2956 sc->txdscr_owned = M_TDES0_OWNADAP; 2957 sc->endian = M_MATCH_BITS; 2958#endif 2959 sc->rxdscr_ctrl = sc->txdscr_ctrl = 0; 2960 break; 2961 } 2962 tulip_init(sc); 2963 2964 /* Prefer address in srom */ 2965 if (rom_read_addr(sc, romaddr) == 0) { 2966 memcpy(sc->hwaddr, romaddr, ENET_ADDR_LEN); 2967 } 2968 2969 sc->state = eth_state_uninit; 2970 2971 switch (sc->device) { 2972 case K_CHIP_DC21040: 2973 devname = "DC21040"; break; 2974 case K_CHIP_DC21041: 2975 devname = "DC21041"; break; 2976 case K_CHIP_DC21140: 2977 devname = "DC21140"; break; 2978 case K_CHIP_DC21143: 2979 devname = "DC21143"; break; 2980 case K_CHIP_DM9102: 2981 devname = "DM9102"; break; 2982 case K_CHIP_82C169: 2983 devname = "82C169"; break; 2984 default: 2985 devname = "DC21x4x"; break; 2986 } 2987 2988 xsprintf(descr, "%s Ethernet at 0x%X (%a)", 2989 devname, sc->membase, sc->hwaddr); 2990 2991 cfe_attach(drv, sc, NULL, descr); 2992 return 1; 2993} 2994 2995 2996/* ********************************************************************* 2997 * TULIP_ETHER_PROBE(drv,probe_a,probe_b,probe_ptr) 2998 * 2999 * Probe and install drivers for all DC21x4x Ethernet controllers. 3000 * For each, create a context structure and attach to the 3001 * specified network device. 3002 * 3003 * Input parameters: 3004 * drv - driver descriptor 3005 * probe_a - not used 3006 * probe_b - not used 3007 * probe_ptr - string pointer to hardware address for the first 3008 * MAC, in the form xx:xx:xx:xx:xx:xx 3009 * 3010 * Return value: 3011 * nothing 3012 ********************************************************************* */ 3013static void 3014tulip_ether_probe(cfe_driver_t *drv, 3015 unsigned long probe_a, unsigned long probe_b, 3016 void *probe_ptr) 3017{ 3018 int index; 3019 int n; 3020 uint8_t hwaddr[ENET_ADDR_LEN]; 3021 3022 if (probe_ptr) 3023 enet_parse_hwaddr((char *) probe_ptr, hwaddr); 3024 else { 3025 /* use default address 02-00-00-10-11-11 */ 3026 hwaddr[0] = 0x02; hwaddr[1] = 0x00; hwaddr[2] = 0x00; 3027 hwaddr[3] = 0x10; hwaddr[4] = 0x11; hwaddr[5] = 0x11; 3028 } 3029 3030 n = 0; 3031 index = 0; 3032 for (;;) { 3033 pcitag_t tag; 3034 pcireg_t device; 3035 3036 if (pci_find_class(PCI_CLASS_NETWORK, index, &tag) != 0) 3037 break; 3038 3039 index++; 3040 3041 device = pci_conf_read(tag, R_CFG_CFID); 3042 if (PCI_VENDOR(device) == K_PCI_VENDOR_DEC) { 3043#if 0 /* this currently (2.1.1) generates a bad code in PIC mode */ 3044 switch (PCI_PRODUCT(device)) { 3045 case K_PCI_ID_DC21040: 3046 case K_PCI_ID_DC21041: 3047 case K_PCI_ID_DC21140: 3048 case K_PCI_ID_DC21143: 3049 tulip_ether_attach(drv, tag, n, hwaddr); 3050 n++; 3051 enet_incr_hwaddr(hwaddr, 1); 3052 break; 3053 default: 3054 break; 3055 } 3056#else 3057 if (PCI_PRODUCT(device) == K_PCI_ID_DC21040 || 3058 PCI_PRODUCT(device) == K_PCI_ID_DC21041 || 3059 PCI_PRODUCT(device) == K_PCI_ID_DC21140 || 3060 PCI_PRODUCT(device) == K_PCI_ID_DC21143) { 3061 3062 tulip_ether_attach(drv, tag, n, hwaddr); 3063 n++; 3064 enet_incr_hwaddr(hwaddr, 1); 3065 } 3066#endif 3067 } 3068 else if (PCI_VENDOR(device) == K_PCI_VENDOR_DAVICOM) { 3069 if (PCI_PRODUCT(device) == K_PCI_ID_DM9102) { 3070 tulip_ether_attach(drv, tag, n, hwaddr); 3071 n++; 3072 enet_incr_hwaddr(hwaddr, 1); 3073 } 3074 } 3075 else if (PCI_VENDOR(device) == K_PCI_VENDOR_LITEON) { 3076 if (PCI_PRODUCT(device) == K_PCI_ID_82C169) { 3077 tulip_ether_attach(drv, tag, n, hwaddr); 3078 n++; 3079 enet_incr_hwaddr(hwaddr, 1); 3080 } 3081 } 3082 } 3083} 3084 3085 3086/* The functions below are called via the dispatch vector for the 21x4x. */ 3087 3088/* ********************************************************************* 3089 * TULIP_ETHER_OPEN(ctx) 3090 * 3091 * Open the Ethernet device. The MAC is reset, initialized, and 3092 * prepared to receive and send packets. 3093 * 3094 * Input parameters: 3095 * ctx - device context (includes ptr to our softc) 3096 * 3097 * Return value: 3098 * status, 0 = ok 3099 ********************************************************************* */ 3100static int 3101tulip_ether_open(cfe_devctx_t *ctx) 3102{ 3103 tulip_softc *sc = ctx->dev_softc; 3104 3105 if (sc->state == eth_state_on) 3106 tulip_stop(sc); 3107 3108 sc->devctx = ctx; 3109 tulip_start(sc); 3110 3111#if XPOLL 3112 tulip_isr(sc); 3113#endif 3114 3115 return 0; 3116} 3117 3118/* ********************************************************************* 3119 * TULIP_ETHER_READ(ctx,buffer) 3120 * 3121 * Read a packet from the Ethernet device. If no packets are 3122 * available, the read will succeed but return 0 bytes. 3123 * 3124 * Input parameters: 3125 * ctx - device context (includes ptr to our softc) 3126 * buffer - pointer to buffer descriptor. 3127 * 3128 * Return value: 3129 * status, 0 = ok 3130 ********************************************************************* */ 3131static int 3132tulip_ether_read(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 3133{ 3134 tulip_softc *sc = ctx->dev_softc; 3135 eth_pkt_t *pkt; 3136 int blen; 3137 3138#if XPOLL 3139 tulip_isr(sc); 3140#endif 3141 3142 if (sc->state != eth_state_on) return -1; 3143 3144 CS_ENTER(sc); 3145 pkt = (eth_pkt_t *) q_deqnext(&(sc->rxqueue)); 3146 CS_EXIT(sc); 3147 3148 if (pkt == NULL) { 3149 buffer->buf_retlen = 0; 3150 return 0; 3151 } 3152 3153 blen = buffer->buf_length; 3154 if (blen > pkt->length) blen = pkt->length; 3155 3156 hs_memcpy_to_hs(buffer->buf_ptr, pkt->buffer, blen); 3157 buffer->buf_retlen = blen; 3158 3159 eth_free_pkt(sc, pkt); 3160 tulip_fillrxring(sc); 3161 3162#if XPOLL 3163 tulip_isr(sc); 3164#endif 3165 3166 return 0; 3167} 3168 3169/* ********************************************************************* 3170 * TULIP_ETHER_INPSTAT(ctx,inpstat) 3171 * 3172 * Check for received packets on the Ethernet device 3173 * 3174 * Input parameters: 3175 * ctx - device context (includes ptr to our softc) 3176 * inpstat - pointer to input status structure 3177 * 3178 * Return value: 3179 * status, 0 = ok 3180 ********************************************************************* */ 3181static int 3182tulip_ether_inpstat(cfe_devctx_t *ctx, iocb_inpstat_t *inpstat) 3183{ 3184 tulip_softc *sc = ctx->dev_softc; 3185 3186#if XPOLL 3187 tulip_isr(sc); 3188#endif 3189 3190 if (sc->state != eth_state_on) return -1; 3191 3192 /* We avoid an interlock here because the result is a hint and an 3193 interrupt cannot turn a non-empty queue into an empty one. */ 3194 inpstat->inp_status = (q_isempty(&(sc->rxqueue))) ? 0 : 1; 3195 3196 return 0; 3197} 3198 3199/* ********************************************************************* 3200 * TULIP_ETHER_WRITE(ctx,buffer) 3201 * 3202 * Write a packet to the Ethernet device. 3203 * 3204 * Input parameters: 3205 * ctx - device context (includes ptr to our softc) 3206 * buffer - pointer to buffer descriptor. 3207 * 3208 * Return value: 3209 * status, 0 = ok 3210 ********************************************************************* */ 3211static int 3212tulip_ether_write(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 3213{ 3214 tulip_softc *sc = ctx->dev_softc; 3215 eth_pkt_t *pkt; 3216 int blen; 3217 3218#if XPOLL 3219 tulip_isr(sc); 3220#endif 3221 3222 if (sc->state != eth_state_on) return -1; 3223 3224 pkt = eth_alloc_pkt(sc); 3225 if (!pkt) return CFE_ERR_NOMEM; 3226 3227 blen = buffer->buf_length; 3228 if (blen > pkt->length) blen = pkt->length; 3229 3230 hs_memcpy_from_hs(pkt->buffer, buffer->buf_ptr, blen); 3231 pkt->length = blen; 3232 3233 if (tulip_transmit(sc, pkt) != 0) { 3234 eth_free_pkt(sc,pkt); 3235 return CFE_ERR_IOERR; 3236 } 3237 3238#if XPOLL 3239 tulip_isr(sc); 3240#endif 3241 3242 return 0; 3243} 3244 3245/* ********************************************************************* 3246 * TULIP_ETHER_IOCTL(ctx,buffer) 3247 * 3248 * Do device-specific I/O control operations for the device 3249 * 3250 * Input parameters: 3251 * ctx - device context (includes ptr to our softc) 3252 * buffer - pointer to buffer descriptor. 3253 * 3254 * Return value: 3255 * status, 0 = ok 3256 ********************************************************************* */ 3257static int 3258tulip_ether_ioctl(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 3259{ 3260 tulip_softc *sc = ctx->dev_softc; 3261 int *argp; 3262 int mode; 3263 int speed; 3264 3265 switch ((int)buffer->buf_ioctlcmd) { 3266 case IOCTL_ETHER_GETHWADDR: 3267 hs_memcpy_to_hs(buffer->buf_ptr, sc->hwaddr, sizeof(sc->hwaddr)); 3268 return 0; 3269 3270 case IOCTL_ETHER_SETHWADDR: 3271 return -1; /* not supported */ 3272 3273 case IOCTL_ETHER_GETSPEED: 3274 argp = (int *) buffer->buf_ptr; 3275 *argp = sc->linkspeed; 3276 return 0; 3277 3278 case IOCTL_ETHER_SETSPEED: 3279 tulip_stop(sc); 3280 tulip_resetrings(sc); 3281 speed = *((int *) buffer->buf_ptr); 3282 tulip_setspeed(sc, speed); 3283 tulip_start(sc); 3284 sc->state = eth_state_on; 3285 return 0; 3286 3287 case IOCTL_ETHER_GETLINK: 3288 argp = (int *) buffer->buf_ptr; 3289 *argp = sc->linkspeed; 3290 return 0; 3291 3292 case IOCTL_ETHER_GETLOOPBACK: 3293 *((int *) buffer) = sc->loopback; 3294 return 0; 3295 3296 case IOCTL_ETHER_SETLOOPBACK: 3297 tulip_stop(sc); 3298 tulip_resetrings(sc); 3299 mode = *((int *) buffer->buf_ptr); 3300 sc->loopback = ETHER_LOOPBACK_OFF; /* default */ 3301 if (mode == ETHER_LOOPBACK_INT || mode == ETHER_LOOPBACK_EXT) { 3302 tulip_setloopback(sc, mode); 3303 } 3304 tulip_start(sc); 3305 sc->state = eth_state_on; 3306 return 0; 3307 3308 default: 3309 return -1; 3310 } 3311} 3312 3313/* ********************************************************************* 3314 * TULIP_ETHER_CLOSE(ctx) 3315 * 3316 * Close the Ethernet device. 3317 * 3318 * Input parameters: 3319 * ctx - device context (includes ptr to our softc) 3320 * 3321 * Return value: 3322 * status, 0 = ok 3323 ********************************************************************* */ 3324static int 3325tulip_ether_close(cfe_devctx_t *ctx) 3326{ 3327 tulip_softc *sc = ctx->dev_softc; 3328 3329 sc->state = eth_state_off; 3330 tulip_stop(sc); 3331 3332 /* resynchronize descriptor rings */ 3333 tulip_resetrings(sc); 3334 3335 sc->devctx = NULL; 3336 return 0; 3337} 3338 3339 3340/* ********************************************************************* 3341 * TULIP_ETHER_POLL(ctx,ticks) 3342 * 3343 * TBD 3344 * 3345 * Input parameters: 3346 * ctx - device context (includes ptr to our softc) 3347 * ticks- current time in ticks 3348 * 3349 * Return value: 3350 * nothing 3351 ********************************************************************* */ 3352 3353static void 3354tulip_ether_poll(cfe_devctx_t *ctx, int64_t ticks) 3355{ 3356#if XPOLL 3357 tulip_softc *sc = ctx->dev_softc; 3358 3359 tulip_isr(sc); 3360#endif 3361} 3362 3363#if 0 3364/* ********************************************************************* 3365 * TULIP_ETHER_RESET(softc) 3366 * 3367 * This routine is called when CFE is restarted after a 3368 * program exits. We can clean up pending I/Os here. 3369 * 3370 * Input parameters: 3371 * softc - pointer to tulip_softc 3372 * 3373 * Return value: 3374 * nothing 3375 ********************************************************************* */ 3376 3377static void 3378tulip_ether_reset(void *softc) 3379{ 3380 tulip_softc *sc = (tulip_softc *)softc; 3381 3382 /* Turn off the Ethernet interface. */ 3383 3384 RESET_ADAPTER(sc); 3385} 3386#endif 3387 3388 3389 3390/* The functions below are for support of serial EEPROM manipulation. */ 3391 3392uint16_t tulip_srom_read(void *softc, unsigned int addr); 3393void tulip_srom_enable(void *softc, int enable); 3394int tulip_srom_write(void *softc, unsigned int addr, uint16_t word); 3395 3396uint16_t 3397tulip_srom_read(void *softc, unsigned int addr) 3398{ 3399 tulip_softc *sc = (tulip_softc *)softc; 3400 uint32_t csr9; 3401 uint16_t v; 3402 3403 if (sc->device == K_CHIP_DC21040) { 3404 xprintf("%s: SROM read not supported\n", tulip_devname(sc)); 3405 return 0xFFFF; 3406 } 3407 3408 csr9 = READCSR(sc, R_CSR_ROM_MII); 3409 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMREAD); 3410 srom_idle_state(sc); 3411 3412 v = srom_read_word(sc, addr); 3413 3414 WRITECSR(sc, R_CSR_ROM_MII, 0/*csr9*/); 3415 return v; 3416} 3417 3418void 3419tulip_srom_enable(void *softc, int enable) 3420{ 3421 tulip_softc *sc = (tulip_softc *)softc; 3422 uint32_t csr9; 3423 3424 if (sc->device == K_CHIP_DC21040) { 3425 xprintf("%s: SROM enable not supported\n", tulip_devname(sc)); 3426 return; 3427 } 3428 3429 csr9 = READCSR(sc, R_CSR_ROM_MII); 3430 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMWRITE); 3431 srom_idle_state(sc); 3432 3433 srom_set_enable(sc, enable); 3434 3435 WRITECSR(sc, R_CSR_ROM_MII, 0/*csr9*/); 3436} 3437 3438 3439int 3440tulip_srom_write(void *softc, unsigned int addr, uint16_t word) 3441{ 3442 tulip_softc *sc = (tulip_softc *)softc; 3443 uint32_t csr9; 3444 int rv; 3445 3446 if (sc->device == K_CHIP_DC21040) { 3447 xprintf("%s: SROM write not supported\n", tulip_devname(sc)); 3448 return -1; 3449 } 3450 3451 csr9 = READCSR(sc, R_CSR_ROM_MII); 3452 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMWRITE); 3453 srom_idle_state(sc); 3454 3455 rv = srom_write_word(sc, addr, word); 3456 3457 WRITECSR(sc, R_CSR_ROM_MII, 0/*csr9*/); 3458 return rv; 3459} 3460