1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * i8255x Ethernet Driver File: dev_i82559.c 5 * 6 * Author: Ed Satterthwaite 7 * 8 ********************************************************************* 9 * 10 * Copyright 2003 11 * Broadcom Corporation. All rights reserved. 12 * 13 * This software is furnished under license and may be used and 14 * copied only in accordance with the following terms and 15 * conditions. Subject to these conditions, you may download, 16 * copy, install, use, modify and distribute modified or unmodified 17 * copies of this software in source and/or binary form. No title 18 * or ownership is transferred hereby. 19 * 20 * 1) Any source code used, modified or distributed must reproduce 21 * and retain this copyright notice and list of conditions 22 * as they appear in the source file. 23 * 24 * 2) No right is granted to use any trade name, trademark, or 25 * logo of Broadcom Corporation. The "Broadcom Corporation" 26 * name may not be used to endorse or promote products derived 27 * from this software without the prior written permission of 28 * Broadcom Corporation. 29 * 30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 42 * THE POSSIBILITY OF SUCH DAMAGE. 43 ********************************************************************* */ 44 45#include "cfe.h" 46#include "lib_physio.h" 47 48#ifdef CPUCFG_MEMCPY 49#error "this is broken now." 50extern void *CPUCFG_MEMCPY(void *dest, const void *src, size_t cnt); 51#define blockcopy CPUCFG_MEMCPY 52#else 53#define blockcopy memcpy 54#endif 55#include "cfe_irq.h" 56 57#include "net_enet.h" 58 59#include "pcivar.h" 60#include "pcireg.h" 61 62#include "i82559.h" 63#include "mii.h" 64 65/* 66 This is a driver for specific configurations of the Intel 8255x 67 Ethernet controllers. The chip design evolved substantially over 68 time, and Intel uses a bewildering array of PCI product identifiers 69 for this series. The revision number appears to be a better guide 70 to chip features: 71 i82557 0x01 - 0x03 72 i82558 0x04 - 0x05 73 i82559 0x06 - 0x08 74 i82559S 0x09 75 i82559ER 0x09 76 i82550 0x0C - 0x0E 77 i82551 0x0F - 0x10 (+?) 78 The current version of this driver recognizes a limited number of 79 NICs (product ids) and mostly restricts itself to features in the 80 common subset. It has been tested with the i82557 (Rev 2), i82559 81 (Rev 8) and i82559S (Rev 9). 82 83 This SB1250 version takes advantage of DMA coherence. It uses 84 "preserve bit lanes" addresses for all accesses to PCI space and 85 CSRs, but "match byte lanes" must be used for all DMA accesses 86 mastered by the 8255x. */ 87 88#ifndef I82559_DEBUG 89#define I82559_DEBUG 0 90#endif 91 92#if ((ENDIAN_BIG + ENDIAN_LITTLE) != 1) 93#error "dev_i82559: system endian not set" 94#endif 95 96/* Set IPOLL to drive processing through the pseudo-interrupt 97 dispatcher. Set XPOLL to drive processing by an external polling 98 agent. Setting both is ok. */ 99 100#ifndef IPOLL 101#define IPOLL 0 102#endif 103#ifndef XPOLL 104#define XPOLL 1 105#endif 106 107#define CACHE_ALIGN 32 108#define ALIGN(n,align) (((n)+((align)-1)) & ~((align)-1)) 109 110#define MIN_ETHER_PACK (ENET_MIN_PKT+ENET_CRC_SIZE) /* size of min packet */ 111#define MAX_ETHER_PACK (ENET_MAX_PKT+ENET_CRC_SIZE) /* size of max packet */ 112 113 114/* i8255x Control Blocks as struct's. Since preserve-byte-lanes 115 addressing is used for all DMA, 16 bit fields have the same offset 116 in either endian mode, but the contents must be swapped if 117 big-endian. */ 118 119typedef struct cb_hdr_s { /* Common CB prefix (CU) */ 120 uint16_t cb_stat; 121 uint16_t cb_cmd; 122 uint32_t cb_link; 123 /* command specific fields follow here */ 124} cb_hdr_t; 125 126typedef struct tbd_s { /* Transmit Buffer Descriptor (TBD) */ 127 uint32_t tbd_addr; 128 uint32_t tbd_count; 129} tbd_t; 130 131/* Transmit Control Blocks are defined to allow flexible mode and to 132 accomodate extended TCBs. The i82557 does not support extended 133 TCBs, but the list of TBDs is still appended to the basic TCB. */ 134 135typedef struct tcb_s { /* Transmit CB (TCB, aka TxCB) */ 136 cb_hdr_t tcb_hdr; /* 8 */ 137 uint32_t tcb_tbdp; /* 4 */ 138 uint32_t tcb_count; /* 4 */ 139 tbd_t tcb_tbd[2]; /* 16 */ 140} tcb_t; 141 142#define TCB_STRIDE ALIGN(sizeof(tcb_t), CACHE_ALIGN) 143 144typedef struct rfd_s { /* RFD structure (RU) */ 145 uint16_t rfd_stat; 146 uint16_t rfd_cmd; 147 uint32_t rfd_link; 148 uint32_t rfd_rsvd; 149 uint32_t rfd_count; 150 /* data follows here */ 151} rfd_t; 152 153 154/* Packet buffers. For now, we use "simplified mode" for rx to 155 support pre-82550 chips. In that mode, the buffer immediately 156 follows the RFD. To allow sharing the buffer pool between rx and 157 tx, space for prefixed control is included in all packet buffers. */ 158 159#define ETH_PKTBUF_LEN ALIGN(MAX_ETHER_PACK, CACHE_ALIGN) 160 161typedef struct eth_pkt_s { 162 queue_t next; /* 8 */ 163 uint8_t *buffer; /* 4 */ 164 uint16_t flags; /* 2 */ 165 int16_t length; /* 2 */ 166 rfd_t rfd; /* 16 */ 167 uint8_t data[ETH_PKTBUF_LEN]; /* cache aligned */ 168} eth_pkt_t; 169 170#define ETH_PKTBUF_SIZE ALIGN(sizeof(eth_pkt_t), CACHE_ALIGN) 171#define ETH_PKTBUF_OFFSET (offsetof(eth_pkt_t, data)) 172#define ETH_PKTRFD_OFFSET (offsetof(eth_pkt_t, rfd)) 173 174#define BUF_PKT_BASE(data) ((eth_pkt_t *)((data) - ETH_PKTBUF_OFFSET)) 175#define RFD_PKT_BASE(rfd) ((eth_pkt_t *)((uint8_t *)(rfd) - ETH_PKTRFD_OFFSET)) 176 177static void 178show_packet(char c, eth_pkt_t *pkt) 179{ 180 int i; 181 int n = (pkt->length < 32 ? pkt->length : 32); 182 183 xprintf("%c[%4d]:", c, pkt->length); 184 for (i = 0; i < n; i++) { 185 if (i % 4 == 0) 186 xprintf(" "); 187 xprintf("%02x", pkt->buffer[i]); 188 } 189 xprintf("\n"); 190} 191 192 193/* Driver data structures */ 194 195typedef enum { 196 eth_state_uninit, 197 eth_state_off, 198 eth_state_on, 199 eth_state_broken 200} eth_state_t; 201 202typedef enum { 203 chip_i82557, 204 chip_i82558, 205 chip_i82559, 206 chip_i82550, 207 chip_i82551 208} chip_t; 209 210typedef struct i82559_softc_s i82559_softc; 211 212struct i82559_softc_s { 213 uint32_t membase; 214 uint8_t irq; /* interrupt mapping (used if IPOLL) */ 215 pcitag_t tag; /* tag for configuration registers */ 216 217 uint8_t hwaddr[ENET_ADDR_LEN]; 218 219 uint16_t device; /* chip device code */ 220 uint8_t revision; /* chip revision and step (Table 3-7) */ 221 chip_t chip; /* chip feature set */ 222 223 eth_state_t state; /* current state */ 224 uint8_t intmask; /* shadow interrupt mask */ 225 unsigned int tx_thresh; /* current transmit threshold */ 226 227 cfe_devctx_t *devctx; 228 229 /* These fields are set before calling i82559_hwinit */ 230 int linkspeed; /* encodings from cfe_ioctl */ 231 int loopback; 232 uint8_t linkstat; 233 234 /* Packet buffer lists */ 235 queue_t freelist; 236 queue_t rxqueue; 237 uint8_t *pktpool; 238 239 /* Head and tail pointers for the rx chain (of packet buffers). */ 240 volatile eth_pkt_t *rx_remove; 241 volatile eth_pkt_t *rx_add; 242 int rx_chained; 243 244 /* Head and tail pointers for the tx ring (of transmit control blocks). */ 245 volatile tcb_t *tx_add; 246 volatile tcb_t *tx_remove; 247 volatile tcb_t *tx_suspend; /* prev(tx_add) */ 248 uint8_t *tcbbase; 249 volatile tcb_t *tx_ring; 250 251 /* These fields describe the PHY */ 252 int phy_addr; 253 uint32_t phy_vendor; 254 uint16_t phy_device; 255 uint16_t (*mii_read_register)(i82559_softc *sc, unsigned int index); 256 void (*mii_write_register)(i82559_softc *sc, unsigned int index, 257 uint16_t value); 258 259 /* Statistics */ 260 uint32_t inpkts; 261 uint32_t outpkts; 262 uint32_t interrupts; 263 uint32_t rx_interrupts; 264 uint32_t tx_interrupts; 265}; 266 267 268/* Entry to and exit from critical sections (currently relative to 269 interrupts only, not SMP) */ 270 271#if CFG_INTERRUPTS 272#define CS_ENTER(sc) cfe_disable_irq(sc->irq) 273#define CS_EXIT(sc) cfe_enable_irq(sc->irq) 274#else 275#define CS_ENTER(sc) ((void)0) 276#define CS_EXIT(sc) ((void)0) 277#endif 278 279 280/* Driver parameterization */ 281 282#define MIN_RX_CHAIN 16 283#define TX_RING_SIZE 16 284#define ETH_PKTPOOL_SIZE (MIN_RX_CHAIN+16) 285 286 287/* Access macros */ 288 289/* Note that PTR_TO_PHYS only works with 32-bit addresses, but then 290 so does the i8255x. */ 291#define PTR_TO_PHYS(x) (PHYSADDR((uintptr_t)(x))) 292#define PHYS_TO_PTR(a) ((uint8_t *)KERNADDR(a)) 293 294/* The i8255x does not have a big-endian option for DMA transactions 295 that it masters. Since most such transactions have byte-oriented 296 data, "preserve byte lanes" addressing is used for such DMA. */ 297#undef PHYS_TO_PCI 298#undef PCI_TO_PHYS 299#define PHYS_TO_PCI(a) ((uint32_t) (a)) 300#define PCI_TO_PHYS(a) ((uint32_t) (a)) 301 302#define PCI_TO_PTR(a) (PHYS_TO_PTR(PCI_TO_PHYS(a))) 303#define PTR_TO_PCI(x) (PHYS_TO_PCI(PTR_TO_PHYS(x))) 304 305 306#define READCSR(sc,csr) (phys_read32((sc)->membase + (csr))) 307#define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) 308 309#if ENDIAN_BIG 310#define READCSR16(sc,csr) (phys_read16((sc)->membase + ((csr)^2))) 311#define WRITECSR16(sc,csr,val) (phys_write16((sc)->membase + ((csr)^2), (val))) 312 313#define READCSR8(sc,csr) (phys_read8((sc)->membase + ((csr)^3))) 314#define WRITECSR8(sc,csr,val) (phys_write8((sc)->membase + ((csr)^3), (val))) 315#else 316#define READCSR16(sc,csr) (phys_read16((sc)->membase + (csr))) 317#define WRITECSR16(sc,csr,val) (phys_write16((sc)->membase + (csr), (val))) 318 319#define READCSR8(sc,csr) (phys_read8((sc)->membase + (csr))) 320#define WRITECSR8(sc,csr,val) (phys_write8((sc)->membase + (csr), (val))) 321#endif 322 323 324/* Prototypes */ 325 326static void i82559_ether_probe(cfe_driver_t *drv, 327 unsigned long probe_a, unsigned long probe_b, 328 void *probe_ptr); 329 330 331/* Byte swap utilities. */ 332 333#if ENDIAN_BIG 334#define HTOL2(x) \ 335 ((((x) & 0xFF) << 8) | (((x) >> 8) & 0xFF)) 336 337static uint16_t 338htol2(uint16_t x) 339{ 340 return (uint16_t)((x >> 8) | (x << 8)); 341} 342 343#define HTOL4(x) \ 344 ((((x) & 0x00FF) << 24) | \ 345 (((x) & 0xFF00) << 8) | \ 346 (((x) >> 8) & 0xFF00) | \ 347 (((x) >> 24) & 0x00FF)) 348 349static uint32_t 350htol4(uint32_t x) 351{ 352 uint32_t t; 353 354 t = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); 355 return (t >> 16) | ((t & 0xFFFF) << 16); 356} 357#else 358#define HTOL2(x) (x) 359#define htol2(x) (x) 360#define HTOL4(x) (x) 361#define htol4(x) (x) 362#endif 363 364#define LTOH2 HTOL2 365#define ltoh2 htol2 366#define LTOH4 HTOL4 367#define ltoh4 htol4 368 369 370/* Packet management */ 371 372static eth_pkt_t * 373eth_alloc_pkt(i82559_softc *sc) 374{ 375 eth_pkt_t *pkt; 376 377 CS_ENTER(sc); 378 pkt = (eth_pkt_t *) q_deqnext(&sc->freelist); 379 CS_EXIT(sc); 380 if (!pkt) return NULL; 381 382 pkt->buffer = pkt->data; 383 pkt->length = ETH_PKTBUF_LEN; 384 pkt->flags = 0; 385 386 return pkt; 387} 388 389static void 390eth_free_pkt(i82559_softc *sc, eth_pkt_t *pkt) 391{ 392 CS_ENTER(sc); 393 q_enqueue(&sc->freelist, &pkt->next); 394 CS_EXIT(sc); 395} 396 397static void 398eth_initfreelist(i82559_softc *sc) 399{ 400 int idx; 401 uint8_t *ptr; 402 eth_pkt_t *pkt; 403 404 q_init(&sc->freelist); 405 406 ptr = sc->pktpool; 407 for (idx = 0; idx < ETH_PKTPOOL_SIZE; idx++) { 408 pkt = (eth_pkt_t *) ptr; 409 eth_free_pkt(sc, pkt); 410 ptr += ETH_PKTBUF_SIZE; 411 } 412} 413 414 415/* Utilities */ 416 417static const char * 418i82559_devname(i82559_softc *sc) 419{ 420 return (sc->devctx != NULL ? cfe_device_name(sc->devctx) : "eth?"); 421} 422 423static void 424i82559_scb_command0(i82559_softc *sc, uint8_t cmd) 425{ 426 uint8_t rv; 427 428 do { /* XXX Need a timeout. */ 429 rv = READCSR8(sc, R_SCB_CMD); 430 } while (rv != K_CMD_ACCEPTED); 431 WRITECSR8(sc, R_SCB_CMD, cmd); 432} 433 434static void 435i82559_scb_command1(i82559_softc *sc, uint8_t cmd, uint32_t arg) 436{ 437 uint8_t rv; 438 439 do { /* XXX Need a timeout. */ 440 rv = READCSR8(sc, R_SCB_CMD); 441 } while (rv != K_CMD_ACCEPTED); 442 WRITECSR(sc, R_SCB_PTR, arg); 443 WRITECSR8(sc, R_SCB_CMD, cmd); 444} 445 446 447/* Descriptor chain/ring management */ 448 449/* Note: Currently, receive descriptors are managed as a list (chain). 450 The manual is somewhat confusing about end-of-list state and 451 recovery. */ 452 453static int 454i82559_add_rcvbuf(i82559_softc *sc, eth_pkt_t *pkt) 455{ 456 rfd_t *rfd = &pkt->rfd; 457 458 rfd->rfd_cmd = HTOL2(M_RFD0_EL); 459 rfd->rfd_stat = 0; 460 rfd->rfd_link = HTOL4(NULL_LINK); 461 rfd->rfd_count = htol4(V_RFD3_SIZE(ETH_PKTBUF_LEN)); 462 463 if (sc->rx_add != NULL) { 464 volatile rfd_t *prev_rfd = &(sc->rx_add->rfd); 465 466 prev_rfd->rfd_link = htol4(PTR_TO_PCI(rfd)); 467 prev_rfd->rfd_cmd &= ~HTOL2(M_RFD0_EL); 468 sc->rx_add = pkt; 469 } 470 else { 471 sc->rx_remove = sc->rx_add = pkt; 472 } 473 474 return 0; 475} 476 477static void 478i82559_fillrxchain(i82559_softc *sc) 479{ 480 eth_pkt_t *pkt; 481 482 CS_ENTER(sc); 483 while (1) { 484 if (sc->rx_chained >= MIN_RX_CHAIN) { 485 CS_EXIT(sc); 486 break; 487 } 488 CS_EXIT(sc); 489 pkt = eth_alloc_pkt(sc); 490 if (pkt == NULL) { 491 /* Out of free packet buffers */ 492 break; 493 } 494 if (i82559_add_rcvbuf(sc, pkt) != 0) { 495 eth_free_pkt(sc, pkt); 496 break; 497 } 498 CS_ENTER(sc); 499 sc->rx_chained++; 500 } 501} 502 503static void 504i82559_rx_callback(i82559_softc *sc, eth_pkt_t *pkt) 505{ 506 if (I82559_DEBUG) show_packet('>', pkt); /* debug */ 507 508 CS_ENTER(sc); 509 q_enqueue(&sc->rxqueue, &pkt->next); 510 CS_EXIT(sc); 511 sc->inpkts++; 512} 513 514 515static void 516i82559_procrxchain(i82559_softc *sc) 517{ 518 volatile eth_pkt_t *rxp; 519 volatile rfd_t *rfd; 520 uint16_t stat; 521 uint32_t link; 522 eth_pkt_t *newpkt; 523 524 rxp = sc->rx_remove; 525 while (rxp != NULL) { 526 rfd = &rxp->rfd; 527 if ((rfd->rfd_stat & LTOH2(M_RFD0_C)) == 0) { 528 break; 529 } 530 531 stat = ltoh2(rfd->rfd_stat); 532 link = ltoh4(rfd->rfd_link); 533 534 /* Drop error packets */ 535 if ((stat & M_RFD0_OK) == 0) { 536 xprintf("%s: rx error %04x\n", 537 i82559_devname(sc), stat & M_RFD0_ERRS); 538 newpkt = (eth_pkt_t *)rxp; 539 } 540 else { 541 /* Pass up the packet */ 542 rxp->length = G_RFD3_COUNT(ltoh4(rfd->rfd_count)); 543 i82559_rx_callback(sc, (eth_pkt_t *)rxp); 544 545 /* add a buffer to the chain to replace this one */ 546 newpkt = eth_alloc_pkt(sc); 547 } 548 549 if (link == NULL_LINK) { 550 rxp = NULL; 551 sc->rx_add = sc->rx_remove = NULL; 552 } 553 else { 554 rxp = RFD_PKT_BASE(PCI_TO_PTR(link)); 555 sc->rx_remove = rxp; 556 } 557 558 if (newpkt) { 559 i82559_add_rcvbuf(sc, newpkt); 560 } 561 else { 562 CS_ENTER(sc); 563 sc->rx_chained--; 564 CS_EXIT(sc); 565 } 566 567 } 568} 569 570static void 571i82559_rx_restart(i82559_softc *sc) 572{ 573 if (sc->rx_remove != NULL) { 574 volatile rfd_t *rfd; 575 576 rfd = &sc->rx_remove->rfd; 577 i82559_scb_command1(sc, V_SCB_RUC(K_RUC_START), PTR_TO_PCI(rfd)); 578 } 579 /* else ??? XXX */ 580} 581 582 583static int 584i82559_add_txbuf(i82559_softc *sc, eth_pkt_t *pkt) 585{ 586 volatile tcb_t *tcbp, *tcb; 587 volatile tcb_t *tx_next; 588 589 tcb = sc->tx_add; 590 tx_next = (volatile tcb_t *)(PCI_TO_PTR(ltoh4(tcb->tcb_hdr.cb_link))); 591 if (tx_next == sc->tx_remove) 592 return -1; 593 594 tcb->tcb_hdr.cb_cmd = HTOL2(V_CB0_CMD(K_CB_TRANSMIT) | M_TCB0_SF | 595 M_CB0_S | M_CB0_I); 596 tcb->tcb_hdr.cb_stat &=~ HTOL2(M_CB0_OK | M_CB0_C); 597 598 tcb->tcb_count = htol4(V_TCB3_COUNT(0) | V_TCB3_TBDNUM(1) | 599 V_TCB3_THRESH(sc->tx_thresh)); 600 tcb->tcb_tbd[0].tbd_addr = htol4(PTR_TO_PCI(pkt->buffer)); 601 tcb->tcb_tbd[0].tbd_count = htol4(V_TBD1_COUNT(pkt->length) | M_TBD1_EL); 602 tcb->tcb_tbd[1].tbd_addr = tcb->tcb_tbd[0].tbd_addr; /* XXX NULL_LINK? */ 603 tcb->tcb_tbd[1].tbd_count = 0; 604 605 tcbp = sc->tx_suspend; 606 sc->tx_suspend = sc->tx_add; 607 sc->tx_add = tx_next; 608 609 tcbp->tcb_hdr.cb_cmd &= HTOL2(~M_CB0_S); 610 return 0; 611} 612 613static int 614i82559_transmit(i82559_softc *sc, eth_pkt_t *pkt) 615{ 616 int rv; 617 618 if (I82559_DEBUG) show_packet('<', pkt); 619 620 rv = i82559_add_txbuf(sc, pkt); 621 sc->outpkts++; 622 i82559_scb_command0(sc, V_SCB_CUC(K_CUC_RESUME)); 623 624 return rv; 625} 626 627 628static void 629i82559_proctxring(i82559_softc *sc) 630{ 631 volatile tcb_t *txp; 632 eth_pkt_t *pkt; 633 634 for (;;) { 635 txp = sc->tx_remove; 636 637 if (txp == sc->tx_add) 638 break; 639 if ((txp->tcb_hdr.cb_stat & HTOL2(M_CB0_C)) == 0) 640 break; 641 642 if (G_CB0_CMD(ltoh2(txp->tcb_hdr.cb_cmd)) == K_CB_TRANSMIT) { 643 pkt = BUF_PKT_BASE(PCI_TO_PTR(ltoh4(txp->tcb_tbd[0].tbd_addr))); 644 eth_free_pkt(sc, pkt); 645 } 646 647 txp = (volatile tcb_t *)(PCI_TO_PTR(ltoh4(txp->tcb_hdr.cb_link))); 648 649 sc->tx_remove = txp; 650 } 651} 652 653 654static void 655i82559_initrings(i82559_softc *sc) 656{ 657 volatile tcb_t *txp, *txn; 658 int i; 659 660 /* For tx, we make a permanent ring. */ 661 sc->tx_ring = (volatile tcb_t *)sc->tcbbase; 662 txp = NULL; 663 664 for (i = 0; i < TX_RING_SIZE; i++) { 665 txn = (volatile tcb_t *)(sc->tcbbase + i*TCB_STRIDE); 666 txn->tcb_hdr.cb_cmd = HTOL2(V_CB0_CMD(K_CB_NOP)); 667 txn->tcb_hdr.cb_stat = 0; 668 txn->tcb_count = HTOL4(V_TCB3_TBDNUM(1)); /* always one buffer */ 669 670 /* The following fields are never updated. */ 671 if (sc->chip == chip_i82557) { /* no Extended mode */ 672 txn->tcb_tbdp = htol4(PTR_TO_PCI(txn->tcb_tbd)); 673 } 674 else { /* Extended Mode TxCB */ 675 txn->tcb_tbdp = HTOL4(NULL_LINK); 676 } 677 txn->tcb_tbd[1].tbd_count = 0; 678 679 if (txp != NULL) 680 txp->tcb_hdr.cb_link = htol4(PTR_TO_PCI(txn)); 681 682 txp = txn; 683 } 684 txp->tcb_hdr.cb_link = htol4(PTR_TO_PCI(sc->tx_ring)); 685 686 sc->tx_add = sc->tx_ring; 687 sc->tx_remove = sc->tx_suspend = txp; 688 689 sc->rx_add = sc->rx_remove = NULL; 690 i82559_fillrxchain(sc); 691} 692 693 694static int 695i82559_init(i82559_softc *sc) 696{ 697 /* Allocate buffer pool */ 698 sc->pktpool = KMALLOC(ETH_PKTPOOL_SIZE*ETH_PKTBUF_SIZE, CACHE_ALIGN); 699 eth_initfreelist(sc); 700 q_init(&sc->rxqueue); 701 702 /* Allocate tx control blocks */ 703 sc->tcbbase = KMALLOC(TX_RING_SIZE*TCB_STRIDE, CACHE_ALIGN); 704 705 i82559_initrings(sc); 706 707 return 0; 708} 709 710 711static void 712i82559_resetrings(i82559_softc *sc) 713{ 714 /* NYI (XXX can leak rx packets) */ 715} 716 717 718/* Serial ROM (EEPROM) access */ 719 720/* 721 * Delays below (nsec) are chosen to meet specs for NS93C46 (slow M variant). 722 * Current parts are faster. 723 * Reference: NS Memory Data Book, 1994 724 */ 725 726#define EEPROM_SIZE 128 727#define EEPROM_MAX_CYCLES 32 728 729#define EEPROM_CMD_BITS 3 730#define EEPROM_ADDR_BITS 6 731 732#define K_EEPROM_READ_CMD 06 733#define K_EEPROM_WRITE_CMD 05 734#define K_EEPROM_ERASE_CMD 07 735#define K_EEPROM_EWEN_CMD 04 /* EWEN, EWDS, also WRAL, ERAL */ 736 737#define EEPROM_ADDR_INDEX 0 /* empirical */ 738 739#define EEPROM_WORD(rom,offset) ((rom)[offset] | ((rom)[offset+1] << 8)) 740 741static void 742srom_idle_state(i82559_softc *sc) 743{ 744 uint16_t eep; 745 unsigned int i; 746 747 eep = READCSR16(sc, R_EEPROM_CTL); 748 749 eep |= M_PROM_EECS; 750 WRITECSR16(sc, R_EEPROM_CTL, eep); 751 cfe_nsleep(100); /* CS setup (Tcss=100) */ 752 753 /* Run the clock through the maximum number of pending read cycles */ 754 for (i = 0; i < EEPROM_MAX_CYCLES*2; i++) { 755 eep ^= M_PROM_EESK; 756 WRITECSR16(sc, R_EEPROM_CTL, eep); 757 cfe_nsleep(1000); /* SK period (Fsk=0.5MHz) */ 758 } 759 760 /* Deassert SROM Chip Select */ 761 eep &=~ M_PROM_EECS; 762 WRITECSR16(sc, R_EEPROM_CTL, eep); 763 cfe_nsleep(50); /* CS recovery (Tsks=50) */ 764} 765 766static void 767srom_write_bit(i82559_softc *sc, unsigned int data) 768{ 769 uint16_t eep; 770 771 eep = READCSR16(sc, R_EEPROM_CTL); 772 773 /* Place the data bit on the bus */ 774 if (data == 1) 775 eep |= M_PROM_EEDI; 776 else 777 eep &=~ M_PROM_EEDI; 778 779 WRITECSR16(sc, R_EEPROM_CTL, eep); 780 cfe_nsleep(360); /* setup: Tdis=200 */ 781 782 /* Now clock the data into the SROM */ 783 WRITECSR16(sc, R_EEPROM_CTL, eep | M_PROM_EESK); 784 cfe_nsleep(900); /* clock high, Tskh=500 */ 785 WRITECSR16(sc, R_EEPROM_CTL, eep); 786 cfe_nsleep(450); /* clock low, Tskl=250 */ 787 788 /* Now clear the data bit */ 789 eep &=~ M_PROM_EEDI; /* data invalid, Tidh=20 for SK^ */ 790 WRITECSR16(sc, R_EEPROM_CTL, eep); 791 cfe_nsleep(270); /* min cycle, 1/Fsk=2000 */ 792} 793 794static uint16_t 795srom_read_bit(i82559_softc *sc) 796{ 797 uint16_t eep; 798 799 eep = READCSR16(sc, R_EEPROM_CTL); 800 801 /* Generate a clock cycle before doing a read */ 802 WRITECSR16(sc, R_EEPROM_CTL, eep | M_PROM_EESK); /* rising edge */ 803 cfe_nsleep(1000); /* clock high, Tskh=500, Tpd=1000 */ 804 WRITECSR16(sc, R_EEPROM_CTL, eep); /* falling edge */ 805 cfe_nsleep(1000); /* clock low, 1/Fsk=2000 */ 806 807 eep = READCSR16(sc, R_EEPROM_CTL); 808 return ((eep & M_PROM_EEDO) != 0 ? 1 : 0); 809} 810 811#define CMD_BIT_MASK (1 << (EEPROM_CMD_BITS+EEPROM_ADDR_BITS-1)) 812 813static uint16_t 814srom_read_word(i82559_softc *sc, unsigned int index) 815{ 816 uint16_t command, word; 817 uint16_t eep; 818 unsigned int i; 819 820 eep = READCSR16(sc, R_EEPROM_CTL) | M_PROM_EECS; 821 822 /* Assert the SROM CS line */ 823 WRITECSR16(sc, R_EEPROM_CTL, eep); 824 cfe_nsleep(100); /* CS setup, Tcss = 100 */ 825 826 /* Send the read command to the SROM */ 827 command = (K_EEPROM_READ_CMD << EEPROM_ADDR_BITS) | index; 828 for (i = 0; i < EEPROM_CMD_BITS+EEPROM_ADDR_BITS; i++) { 829 srom_write_bit(sc, (command & CMD_BIT_MASK) != 0 ? 1 : 0); 830 command <<= 1; 831 } 832 833 /* Now read the bits from the SROM (MSB first) */ 834 word = 0; 835 for (i = 0; i < 16; ++i) { 836 word <<= 1; 837 word |= srom_read_bit(sc); 838 } 839 840 /* Clear the SROM CS Line, CS hold, Tcsh = 0 */ 841 WRITECSR16(sc, R_EEPROM_CTL, eep &~ M_PROM_EECS); 842 843 return word; 844} 845 846 847/* Read the entire SROM into the srom array. 848 XXX Assumes a 64-word EEPROM. Size it dynamically (p 46)? */ 849 850static int 851srom_read_all(i82559_softc *sc, uint8_t dest[]) 852{ 853 int i; 854 uint16_t temp; 855 856 srom_idle_state(sc); 857 858 for (i = 0; i < EEPROM_SIZE/2; i++) { 859 temp = srom_read_word(sc, i); 860 dest[2*i] = temp & 0xFF; 861 dest[2*i+1] =temp >> 8; 862 } 863 864 WRITECSR16(sc, R_EEPROM_CTL, 0); /* CS hold, Tcsh=0 */ 865 866 return 0; 867} 868 869static void 870srom_dump(uint8_t srom[]) 871{ 872 int i; 873 874 xprintf("I82559: EEPROM data:"); 875 for (i = 0; i < EEPROM_SIZE; i++) { 876 if (i % 16 == 0) 877 xprintf("\n %02x: ", i); 878 xprintf(" %02x", srom[i]); 879 } 880 xprintf("\n"); 881} 882 883 884/* MII access */ 885 886static uint16_t 887mii_read(i82559_softc *sc, unsigned int reg) 888{ 889 uint32_t cmd, status; 890 uint32_t data; 891 int timeout; 892 893 cmd = (V_MDI_OP(K_MDI_OP_READ) | 894 V_MDI_PHYADD(sc->phy_addr) | V_MDI_REGADD(reg)); 895 WRITECSR(sc, R_MDI_CTL, cmd); 896 897 for (timeout = 5000; timeout > 0; timeout -= 100) { 898 status = READCSR(sc, R_MDI_CTL); 899 if ((status & M_MDI_R) != 0) 900 break; 901 cfe_usleep(100); 902 } 903 904 if (timeout <= 0) 905 return 0xFFFF; 906 907 data = G_MDI_DATA(READCSR(sc, R_MDI_CTL)); 908 return data; 909} 910 911static void 912mii_write(i82559_softc *sc, unsigned int reg, uint16_t value) 913{ 914 uint32_t cmd, status; 915 int timeout; 916 917 cmd = (V_MDI_OP(K_MDI_OP_WRITE) | 918 V_MDI_PHYADD(sc->phy_addr) | V_MDI_REGADD(reg) | 919 V_MDI_DATA(value)); 920 WRITECSR(sc, R_MDI_CTL, cmd); 921 922 for (timeout = 5000; timeout > 0; timeout -= 100) { 923 status = READCSR(sc, R_MDI_CTL); 924 if ((status & M_MDI_R) != 0) 925 break; 926 cfe_usleep(100); 927 } 928} 929 930static int 931mii_probe(i82559_softc *sc) 932{ 933 int i; 934 uint16_t id1, id2; 935 936 for (i = 1; i < 32; i++) { 937 sc->phy_addr = i; 938 id1 = (*sc->mii_read_register)(sc, MII_PHYIDR1); 939 id2 = (*sc->mii_read_register)(sc, MII_PHYIDR2); 940 if ((id1 != 0x0000 && id1 != 0xFFFF) || 941 (id2 != 0x0000 && id2 != 0xFFFF)) { 942 if (id1 != id2) { 943 sc->phy_vendor = ((uint32_t)id1 << 6) | ((id2 >> 10) & 0x3F); 944 sc->phy_device = (id2 >> 4) & 0x3F; 945 return 0; 946 } 947 } 948 } 949 xprintf("mii_probe: No PHY found\n"); 950 sc->phy_addr = 0x1; /* Try the default internal PHY */ 951 sc->phy_vendor = sc->phy_device = 0; 952 return -1; 953} 954 955#if I82559_DEBUG 956static void 957mii_dump(i82559_softc *sc, const char *label) 958{ 959 int i; 960 uint16_t r; 961 962 xprintf("%s\n", label); 963 xprintf("OUI: %08x, Part %02x\n", sc->phy_vendor, sc->phy_device); 964 for (i = 0; i <= 6; ++i) { 965 r = (*sc->mii_read_register)(sc, i); 966 xprintf("MII_REG%02x: %04x\n", i, r); 967 } 968 if (sc->phy_vendor == OUI_INTEL && sc->phy_device == DEV_I82555) { 969 r = (*sc->mii_read_register)(sc, 16); 970 xprintf("MII_REG16: %04x\n", r); 971 r = (*sc->mii_read_register)(sc, 27); 972 xprintf("MII_REG27: %04x\n", r); 973 } 974} 975#else 976#define mii_dump(sc,label) 977#endif 978 979static void 980mii_autonegotiate(i82559_softc *sc) 981{ 982 uint16_t control, status, cap; 983 unsigned int timeout; 984 int linkspeed; 985 int autoneg; 986 987 linkspeed = ETHER_SPEED_UNKNOWN; 988 989 /* Read twice to clear latching bits */ 990 status = (*sc->mii_read_register)(sc, MII_BMSR); 991 status = (*sc->mii_read_register)(sc, MII_BMSR); 992 if (I82559_DEBUG) mii_dump(sc, "query PHY"); 993 994 if ((status & (BMSR_AUTONEG | BMSR_LINKSTAT)) == 995 (BMSR_AUTONEG | BMSR_LINKSTAT)) 996 control = (*sc->mii_read_register)(sc, MII_BMCR); 997 else { 998 /* reset the PHY */ 999 (*sc->mii_write_register)(sc, MII_BMCR, BMCR_RESET); 1000 timeout = 3000; 1001 for (;;) { 1002 control = (*sc->mii_read_register)(sc, MII_BMCR); 1003 if ((control && BMCR_RESET) == 0) break; 1004 cfe_sleep(CFE_HZ/2); 1005 timeout -= 500; 1006 if (timeout <= 0) break; 1007 } 1008 if ((control & BMCR_RESET) != 0) { 1009 xprintf("%s: PHY reset failed\n", i82559_devname(sc)); 1010 return; 1011 } 1012 1013 status = (*sc->mii_read_register)(sc, MII_BMSR); 1014 cap = ((status >> 6) & (ANAR_TXFD | ANAR_TXHD | ANAR_10FD | ANAR_10HD)) 1015 | PSB_802_3; 1016 (*sc->mii_write_register)(sc, MII_ANAR, cap); 1017 control |= (BMCR_ANENABLE | BMCR_RESTARTAN); 1018 (*sc->mii_write_register)(sc, MII_BMCR, control); 1019 1020 timeout = 3000; 1021 for (;;) { 1022 status = (*sc->mii_read_register)(sc, MII_BMSR); 1023 if ((status & BMSR_ANCOMPLETE) != 0) break; 1024 cfe_sleep(CFE_HZ/2); 1025 timeout -= 500; 1026 if (timeout <= 0) break; 1027 } 1028 if (I82559_DEBUG) mii_dump(sc, "done PHY"); 1029 } 1030 1031 xprintf("%s: Link speed: ", i82559_devname(sc)); 1032 if ((status & BMSR_ANCOMPLETE) != 0) { 1033 /* A link partner was negogiated... */ 1034 1035 uint16_t remote = (*sc->mii_read_register)(sc, MII_ANLPAR); 1036 1037 autoneg = 1; 1038 if ((remote & ANLPAR_TXFD) != 0) { 1039 xprintf("100BaseT FDX"); 1040 linkspeed = ETHER_SPEED_100FDX; 1041 } 1042 else if ((remote & ANLPAR_TXHD) != 0) { 1043 xprintf("100BaseT HDX"); 1044 linkspeed = ETHER_SPEED_100HDX; 1045 } 1046 else if ((remote & ANLPAR_10FD) != 0) { 1047 xprintf("10BaseT FDX"); 1048 linkspeed = ETHER_SPEED_10FDX; 1049 } 1050 else if ((remote & ANLPAR_10HD) != 0) { 1051 xprintf("10BaseT HDX"); 1052 linkspeed = ETHER_SPEED_10HDX; 1053 } 1054 xprintf("\n"); 1055 } 1056 else { 1057 /* no link partner negotiation */ 1058 autoneg = 0; 1059 xprintf("Unknown, assuming 10BaseT\n"); 1060 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1061 (*sc->mii_write_register)(sc, MII_BMCR, control); 1062 linkspeed = ETHER_SPEED_10HDX; 1063 } 1064 1065 if ((status & BMSR_LINKSTAT) == 0) 1066 (*sc->mii_write_register)(sc, MII_BMCR, control); 1067#if 0 /* NYI */ 1068 mii_set_speed(sc, linkspeed, autoneg); 1069#endif 1070 1071 status = (*sc->mii_read_register)(sc, MII_BMSR); /* clear latching bits */ 1072 if (I82559_DEBUG) mii_dump(sc, "final PHY"); 1073} 1074 1075 1076/* Utilities */ 1077 1078#define CBALLOC(ext) \ 1079 ((uint32_t *)KMALLOC(CB_HDR_BYTES+(ext), sizeof(uint32_t))) 1080#define CBFREE(cb) KFREE((void *)cb) 1081 1082/* Initiate an action command and wait for it to complete. The common 1083 CB header is filled in here. Any extension must be already be 1084 filled in correct DMA byte order. */ 1085static int 1086i82559_polled_action(i82559_softc *sc, uint8_t op, uint32_t *cb) 1087{ 1088 uint16_t cmd, status; 1089 int count; 1090 cb_hdr_t *cbh = (cb_hdr_t *)cb; 1091 1092 cbh->cb_stat &= HTOL2(~(M_CB0_OK | M_CB0_C)); 1093 cmd = ltoh2(cbh->cb_cmd); 1094 cmd &= ~(M_CB0_I | M_CB0_S | M_CB0_CMD); 1095 cmd |= (V_CB0_CMD(op) | M_CB0_EL); 1096 cbh->cb_cmd = htol2(cmd); 1097 1098 cbh->cb_link = HTOL4(NULL_LINK); /* Apparent end of chain encoding. */ 1099 1100 i82559_scb_command1(sc, V_SCB_CUC(K_CUC_START), PTR_TO_PCI(cb)); 1101 1102 count = 1000; 1103 do { 1104 cfe_usleep(10); 1105 status = ltoh2(cbh->cb_stat); 1106 } while ((status & M_CB0_C) == 0 && --count > 0); 1107 1108 /* Setting EL asserts CI/CNA on completion. */ 1109 WRITECSR8(sc, R_SCB_STATACK, M_SCB_CNA); 1110 1111 return ((status & M_CB0_OK) != 0); 1112} 1113 1114static void 1115i82559_dump(i82559_softc *sc) 1116{ 1117 uint32_t buffer[149]; 1118 uint32_t *cb; 1119 1120 cb = CBALLOC(sizeof(uint32_t)); 1121 if (cb != NULL) { 1122 uint8_t *bb; 1123 int i; 1124 1125 cb[CB_HDR_WORDS+0] = htol4(PTR_TO_PCI(buffer)); 1126 i82559_polled_action(sc, K_CB_DUMP, cb); 1127 CBFREE(cb); 1128 1129 bb = (uint8_t *)buffer; 1130 xprintf("i82559: state dump:"); 1131 for (i = 0; i < 149*4; i++) { 1132 if (i % 16 == 0) 1133 xprintf("\n %04x:", i); 1134 if (i % 4 == 0) 1135 xprintf(" "); 1136 xprintf(" %02x", *bb++); 1137 } 1138 xprintf("\n"); 1139 } 1140} 1141 1142 1143static void 1144i82559_isr(void *arg) 1145{ 1146 i82559_softc *sc = (i82559_softc *)arg; 1147 uint8_t status; 1148 1149#if IPOLL 1150 sc->interrupts++; 1151#endif 1152 1153 for (;;) { 1154 1155 /* Read and clear the interrupt status. */ 1156 status = READCSR8(sc, R_SCB_STATACK); 1157 WRITECSR8(sc, R_SCB_STATACK, status); 1158 if ((status & sc->intmask) == 0) 1159 break; 1160 1161 if (status & (M_SCB_FR | M_SCB_RNR)) { 1162#if IPOLL 1163 sc->rx_interrupts++; 1164#endif 1165 /* Process received packets. */ 1166 i82559_procrxchain(sc); 1167 } 1168 if (status & M_SCB_RNR) { 1169 /* Restart the receiver. */ 1170 i82559_rx_restart(sc); 1171 } 1172 1173 if (status & M_SCB_CX) { 1174#if IPOLL 1175 sc->tx_interrupts++; 1176#endif 1177 /* Process received packets. */ 1178 i82559_proctxring(sc); 1179 } 1180 1181 } 1182} 1183 1184 1185/* Required 1-bits and selected setting for the i82559 Configuration 1186 Bytes. These match the mandatory and most of the recommended 1187 values in the manual. Chip-specific adjustments are done below. */ 1188static const uint8_t proto_config[24] = { 1189 0x16, /* 0 */ 1190 0x08, 1191 0x00, 1192 0x01, /* MWI Enable (not i82557) */ 1193 0x00, /* 4 */ 1194 0x00, 1195 0x22, /* Extended TxCB (not i82557) */ 1196 0x03, 1197 0x01, /* 8 */ 1198 0x00, 1199 0x2E, 1200 0x00, 1201 0x61, /* 12 */ 1202 0x00, 1203 0xF2, 1204 0x48, 1205 0x00, /* 16 */ 1206 0x00, 1207 0xF3, 1208 0x80, 1209 0x3F, /* 20 */ 1210 0x05, 1211 0x00, /* filler */ 1212 0x00 1213}; 1214 1215#if 0 /* Observed after reset (i82557, rev 2): */ 1216 0x00, 0x00, 0x2e, 0x00, /* 8 - 11 */ 1217 0x60, 0x00, 0xF2, 0xC8, /* 12 - 15 */ 1218 0x00, 0x40, 0xF2, 0x00, /* 16 - 19 */ 1219 0x3F, 0x05, /* 20 - 21 */ 1220#endif 1221 1222#if 0 /* Observed after reset (i82559, rev 8): */ 1223 0x01, 0x00, 0x2e, 0x00, 1224 0x60, 0xFF, 0xFF, 0xC8, 1225 0x00, 0x40, 0xF2, 0x00, 1226 0x3F, 0x05, 1227#endif 1228 1229#if 0 /* Observed after reset (i82559S, rev 9): */ 1230 0x01, 0x00, 0x2e, 0x00, 1231 0x60, 0xFF, 0xFF, 0xC8, 1232 0x00, 0x40, 0xF2, 0x80, 1233 0x3F, 0x05, 1234#endif 1235 1236static void 1237i82559_configure(i82559_softc *sc) 1238{ 1239 uint32_t *cb; 1240 uint8_t *config; 1241 1242 cb = CBALLOC(sizeof(proto_config)); 1243 if (cb != NULL) { 1244 config = (uint8_t *)&cb[CB_HDR_WORDS]; 1245 memcpy(config, proto_config, sizeof(proto_config)); 1246 1247 /* Chip-specific adjustments */ 1248 switch (sc->chip) { 1249 case chip_i82557: 1250 config[3] = 0x00; /* no MWI */ 1251 config[5] = 0x32; /* no Extended TxCB */ 1252 config[12] = 0x60; /* wait on tx only */ 1253 config[17] = 0x40; /* restore default */ 1254 break; 1255 default: 1256 break; 1257 } 1258 1259 i82559_polled_action(sc, K_CB_CONFIGURE, cb); 1260 CBFREE(cb); 1261 } 1262} 1263 1264static void 1265i82559_setaddress(i82559_softc *sc) 1266{ 1267 uint32_t *cb; 1268 uint8_t *hwaddr; 1269 1270 cb = CBALLOC(ENET_ADDR_LEN); 1271 if (cb != NULL) { 1272 hwaddr = (uint8_t *)&cb[CB_HDR_WORDS]; 1273 memcpy(hwaddr, sc->hwaddr, ENET_ADDR_LEN); 1274 1275 i82559_polled_action(sc, K_CB_ADDRSETUP, cb); 1276 CBFREE(cb); 1277 } 1278} 1279 1280static void 1281i82559_hwinit(i82559_softc *sc) 1282{ 1283 if (sc->state == eth_state_uninit) { 1284 sc->mii_read_register = mii_read; 1285 sc->mii_write_register = mii_write; 1286 1287 mii_probe(sc); 1288 mii_autonegotiate(sc); 1289 if (sc->chip != chip_i82557 && sc->chip != chip_i82558) { 1290 sc->linkstat = READCSR8(sc, R_GEN_STAT); 1291 sc->linkstat &= (M_GSTAT_LINKUP | M_GSTAT_100 | M_GSTAT_FDX); 1292 } 1293 1294 /* Set up linear addressing. */ 1295 i82559_scb_command1(sc, V_SCB_CUC(K_CUC_BASE), 0); 1296 i82559_scb_command1(sc, V_SCB_RUC(K_RUC_BASE), 0); 1297 1298 if (I82559_DEBUG) i82559_dump(sc); 1299 1300 i82559_configure(sc); 1301 i82559_setaddress(sc); 1302 sc->tx_thresh = 8; /* 8*8 = 64 bytes */ 1303 1304 if (I82559_DEBUG) i82559_dump(sc); 1305 } 1306} 1307 1308 1309static void 1310i82559_start(i82559_softc *sc) 1311{ 1312 uint8_t status; 1313 volatile tcb_t *tcb; 1314 volatile rfd_t *rfd; 1315 1316 i82559_hwinit(sc); 1317 1318 sc->intmask = 0; 1319 status = READCSR8(sc, R_SCB_STATACK); 1320 WRITECSR8(sc, R_SCB_STATACK, status); /* clear any pending. */ 1321 READCSR8(sc, R_SCB_STATACK); /* push */ 1322 1323 sc->intmask = (M_SCB_FR | M_SCB_RNR | M_SCB_CX); 1324 1325#if IPOLL 1326 cfe_request_irq(sc->irq, i82559_isr, sc, CFE_IRQ_FLAGS_SHARED, 0); 1327 WRITECSR8(sc, R_SCB_IC, 0); 1328#endif 1329 1330 rfd = &sc->rx_remove->rfd; 1331 i82559_scb_command1(sc, V_SCB_RUC(K_RUC_START), PTR_TO_PCI(rfd)); 1332 1333 tcb = sc->tx_suspend; 1334 tcb->tcb_hdr.cb_cmd = HTOL2(V_CB0_CMD(K_CB_NOP) | M_CB0_S); 1335 tcb->tcb_hdr.cb_stat &= HTOL2(~(M_CB0_OK | M_CB0_C)); 1336 i82559_scb_command1(sc, V_SCB_CUC(K_CUC_START), PTR_TO_PCI(tcb)); 1337 1338 sc->state = eth_state_on; 1339} 1340 1341static void 1342i82559_stop(i82559_softc *sc) 1343{ 1344 uint8_t status; 1345 1346 /* Make sure that no further interrupts will be processed. */ 1347 sc->intmask = 0; 1348 WRITECSR8(sc, R_SCB_IC, M_SCB_M); 1349 (void)READCSR8(sc, R_SCB_IC); /* push */ 1350 cfe_usleep(10); 1351 status = READCSR8(sc, R_SCB_STATACK); 1352 WRITECSR8(sc, R_SCB_STATACK, status); 1353 1354#if IPOLL 1355 cfe_free_irq(sc->irq, 0); 1356#endif 1357 1358 xprintf("%s: %d sent, %d received, %d interrupts\n", 1359 i82559_devname(sc), sc->outpkts, sc->inpkts, sc->interrupts); 1360 if (IPOLL) { 1361 xprintf(" %d rx interrupts, %d tx interrupts\n", 1362 sc->rx_interrupts, sc->tx_interrupts); 1363 } 1364} 1365 1366 1367/* Declarations for CFE Device Driver Interface routines */ 1368 1369static int i82559_ether_open(cfe_devctx_t *ctx); 1370static int i82559_ether_read(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1371static int i82559_ether_inpstat(cfe_devctx_t *ctx,iocb_inpstat_t *inpstat); 1372static int i82559_ether_write(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1373static int i82559_ether_ioctl(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1374static int i82559_ether_close(cfe_devctx_t *ctx); 1375static void i82559_ether_poll(cfe_devctx_t *ctx, int64_t ticks); 1376static void i82559_ether_reset(void *softc); 1377 1378 1379/* CFE Device Driver dispatch structure */ 1380 1381const static cfe_devdisp_t i82559_ether_dispatch = { 1382 i82559_ether_open, 1383 i82559_ether_read, 1384 i82559_ether_inpstat, 1385 i82559_ether_write, 1386 i82559_ether_ioctl, 1387 i82559_ether_close, 1388 i82559_ether_poll, 1389 i82559_ether_reset 1390}; 1391 1392/* CFE Device Driver descriptor */ 1393 1394const cfe_driver_t i82559drv = { 1395 "i8255x Ethernet", 1396 "eth", 1397 CFE_DEV_NETWORK, 1398 &i82559_ether_dispatch, 1399 i82559_ether_probe 1400}; 1401 1402 1403/* CFE Device Driver probe functions. */ 1404 1405static int 1406i82559_ether_attach(cfe_driver_t *drv, pcitag_t tag, int index) 1407{ 1408 i82559_softc *sc; 1409 uint32_t device; 1410 uint32_t class; 1411 phys_addr_t pa; 1412 uint8_t eeprom[EEPROM_SIZE]; 1413 const char *devname; 1414 char descr[100]; 1415 1416 device = pci_conf_read(tag, PCI_ID_REG); 1417 class = pci_conf_read(tag, PCI_CLASS_REG); 1418 1419#if 1 1420 /* Use memory space for the CSRs */ 1421 pci_map_mem(tag, PCI_MAPREG(0), PCI_MATCH_BITS, &pa); 1422#else 1423 /* Use i/o space for the CSRs */ 1424 pci_map_io(tag, PCI_MAPREG(1), PCI_MATCH_BITS, &pa); 1425#endif 1426 1427 sc = (i82559_softc *) KMALLOC(sizeof(i82559_softc), 0); 1428 1429 if (sc == NULL) { 1430 xprintf("I82559: No memory to complete probe\n"); 1431 return 0; 1432 } 1433 memset(sc, 0, sizeof(i82559_softc)); 1434 1435 sc->membase = (uint32_t)pa; 1436 sc->irq = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG) & 0xFF; 1437 sc->tag = tag; 1438 sc->device = PCI_PRODUCT(device); 1439 sc->revision = PCI_REVISION(class); 1440 sc->devctx = NULL; 1441 1442 sc->linkspeed = ETHER_SPEED_AUTO; /* select autonegotiation */ 1443 1444 sc->state = eth_state_uninit; 1445 1446 /* Intel recommends a software reset prior to any access. */ 1447 WRITECSR(sc, R_PORT, V_PORT_FUNC(K_PORT_FUNC_SWRESET)); 1448 cfe_usleep(10); 1449 WRITECSR8(sc, R_SCB_IC, M_SCB_M); /* mask all interrupts */ 1450 1451 i82559_init(sc); 1452 1453 srom_read_all(sc, eeprom); 1454 if (I82559_DEBUG) srom_dump(eeprom); 1455 memcpy(sc->hwaddr, &eeprom[EEPROM_ADDR_INDEX], ENET_ADDR_LEN); 1456 1457 if (sc->device == K_PCI_ID_I82559ER) { 1458 devname = "i82559ER"; 1459 sc->chip = chip_i82559; 1460 } 1461 else { 1462 switch (sc->revision) { 1463 case 0x01: case 0x02: case 0x03: 1464 devname = "i82557"; 1465 sc->chip = chip_i82557; 1466 break; 1467 case 0x04: case 0x05: 1468 devname = "i82558"; 1469 sc->chip = chip_i82558; 1470 break; 1471 case 0x06: case 0x07: case 0x08: 1472 devname = "i82559"; 1473 sc->chip = chip_i82559; 1474 break; 1475 case 0x09: 1476 devname = "i82559S"; 1477 sc->chip = chip_i82559; 1478 break; 1479 case 0x0C: case 0x0D: case 0x0E: 1480 devname = "i82550"; 1481 sc->chip = chip_i82550; 1482 break; 1483 case 0x0F: case 0x10: 1484 devname = "i82551"; 1485 sc->chip = chip_i82551; 1486 break; 1487 default: 1488 devname = "i8255x"; 1489 sc->chip = chip_i82557; 1490 break; 1491 } 1492 } 1493 xsprintf(descr, "%s Ethernet at 0x%X (%a)", 1494 devname, sc->membase, sc->hwaddr); 1495 1496 cfe_attach(drv, sc, NULL, descr); 1497 return 1; 1498} 1499 1500static void 1501i82559_ether_probe(cfe_driver_t *drv, 1502 unsigned long probe_a, unsigned long probe_b, 1503 void *probe_ptr) 1504{ 1505 int index; 1506 int n; 1507 1508 n = 0; 1509 index = 0; 1510 for (;;) { 1511 pcitag_t tag; 1512 pcireg_t device; 1513 1514 if (pci_find_class(PCI_CLASS_NETWORK, index, &tag) != 0) 1515 break; 1516 1517 index++; 1518 1519 device = pci_conf_read(tag, PCI_ID_REG); 1520 if (PCI_VENDOR(device) == K_PCI_VENDOR_INTEL) { 1521 switch (PCI_PRODUCT(device)) { 1522 case K_PCI_ID_I82557: 1523 case K_PCI_ID_I82559ER: 1524 case K_PCI_ID_INBUSINESS: 1525 i82559_ether_attach(drv, tag, n); 1526 n++; 1527 break; 1528 default: 1529 break; 1530 } 1531 } 1532 } 1533} 1534 1535 1536/* The functions below are called via the dispatch vector for the i82559. */ 1537 1538static int 1539i82559_ether_open(cfe_devctx_t *ctx) 1540{ 1541 i82559_softc *sc = ctx->dev_softc; 1542 1543 if (sc->state == eth_state_on) 1544 i82559_stop(sc); 1545 1546 sc->devctx = ctx; 1547 1548 sc->inpkts = sc->outpkts = 0; 1549 sc->interrupts = 0; 1550 sc->rx_interrupts = sc->tx_interrupts = 0; 1551 1552 i82559_start(sc); 1553 1554#if XPOLL 1555 i82559_isr(sc); 1556#endif 1557 1558 return 0; 1559} 1560 1561static int 1562i82559_ether_read(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1563{ 1564 i82559_softc *sc = ctx->dev_softc; 1565 eth_pkt_t *pkt; 1566 int blen; 1567 1568#if XPOLL 1569 i82559_isr(sc); 1570#endif 1571 1572 if (sc->state != eth_state_on) return -1; 1573 1574 CS_ENTER(sc); 1575 pkt = (eth_pkt_t *) q_deqnext(&(sc->rxqueue)); 1576 CS_EXIT(sc); 1577 1578 if (pkt == NULL) { 1579 buffer->buf_retlen = 0; 1580 } 1581 else { 1582 blen = buffer->buf_length; 1583 if (blen > pkt->length) blen = pkt->length; 1584 1585 hs_memcpy_to_hs(buffer->buf_ptr, pkt->buffer, blen); 1586 buffer->buf_retlen = blen; 1587 1588 eth_free_pkt(sc, pkt); 1589 i82559_fillrxchain(sc); 1590 } 1591 1592#if XPOLL 1593 i82559_isr(sc); 1594#endif 1595 1596 return 0; 1597} 1598 1599static int 1600i82559_ether_inpstat(cfe_devctx_t *ctx, iocb_inpstat_t *inpstat) 1601{ 1602 i82559_softc *sc = ctx->dev_softc; 1603 1604#if XPOLL 1605 i82559_isr(sc); 1606#endif 1607 1608 if (sc->state != eth_state_on) return -1; 1609 1610 /* We avoid an interlock here because the result is a hint and an 1611 interrupt cannot turn a non-empty queue into an empty one. */ 1612 inpstat->inp_status = (q_isempty(&(sc->rxqueue))) ? 0 : 1; 1613 1614 return 0; 1615} 1616 1617static int 1618i82559_ether_write(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1619{ 1620 i82559_softc *sc = ctx->dev_softc; 1621 eth_pkt_t *pkt; 1622 int blen; 1623 1624#if XPOLL 1625 i82559_isr(sc); 1626#endif 1627 1628 if (sc->state != eth_state_on) return -1; 1629 1630 pkt = eth_alloc_pkt(sc); 1631 if (!pkt) return CFE_ERR_NOMEM; 1632 1633 blen = buffer->buf_length; 1634 if (blen > pkt->length) blen = pkt->length; 1635 1636 hs_memcpy_from_hs(pkt->buffer, buffer->buf_ptr, blen); 1637 pkt->length = blen; 1638 1639 if (i82559_transmit(sc, pkt) != 0) { 1640 eth_free_pkt(sc, pkt); 1641 return CFE_ERR_IOERR; 1642 } 1643 1644#if XPOLL 1645 i82559_isr(sc); 1646#endif 1647 1648 return 0; 1649} 1650 1651static int 1652i82559_ether_ioctl(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1653{ 1654 i82559_softc *sc = ctx->dev_softc; 1655 int speed; 1656 1657 switch ((int)buffer->buf_ioctlcmd) { 1658 case IOCTL_ETHER_GETHWADDR: 1659 hs_memcpy_to_hs(buffer->buf_ptr, sc->hwaddr, sizeof(sc->hwaddr)); 1660 return 0; 1661 1662 case IOCTL_ETHER_SETHWADDR: 1663 return -1; /* not supported */ 1664 1665 case IOCTL_ETHER_GETSPEED: 1666 speed = sc->linkspeed; 1667 hs_memcpy_to_hs(buffer->buf_ptr,&speed,sizeof(int)); 1668 return 0; 1669 1670 case IOCTL_ETHER_SETSPEED: 1671 return -1; /* NYI */ 1672 1673 case IOCTL_ETHER_GETLINK: 1674 speed = sc->linkspeed; 1675 hs_memcpy_to_hs(buffer->buf_ptr,&speed,sizeof(int)); 1676 return 0; 1677 1678 case IOCTL_ETHER_GETLOOPBACK: 1679 speed = sc->loopback; 1680 hs_memcpy_to_hs(buffer->buf_ptr,&speed,sizeof(int)); 1681 return 0; 1682 1683 case IOCTL_ETHER_SETLOOPBACK: 1684 return -1; /* NYI */ 1685 1686 default: 1687 return -1; 1688 } 1689} 1690 1691static int 1692i82559_ether_close(cfe_devctx_t *ctx) 1693{ 1694 i82559_softc *sc = ctx->dev_softc; 1695 1696 sc->state = eth_state_off; 1697 i82559_stop(sc); 1698 1699 /* resynchronize the control blocks */ 1700 i82559_resetrings(sc); 1701 1702 sc->devctx = NULL; 1703 return 0; 1704} 1705 1706static void 1707i82559_ether_poll(cfe_devctx_t *ctx, int64_t ticks) 1708{ 1709 i82559_softc *sc = ctx->dev_softc; 1710 1711#if XPOLL 1712 i82559_isr(sc); 1713#endif 1714 1715 if (sc->chip != chip_i82557 && sc->chip != chip_i82558) { 1716 uint8_t linkstat = READCSR8(sc, R_GEN_STAT); 1717 1718 linkstat &= (M_GSTAT_LINKUP | M_GSTAT_100 | M_GSTAT_FDX); 1719 if (linkstat != sc->linkstat) { 1720 if ((linkstat & M_GSTAT_LINKUP) == 0) { 1721 if ((sc->linkstat & M_GSTAT_LINKUP) != 0) { 1722 xprintf("%s: Link speed: Unknown (down)\n", 1723 i82559_devname(sc)); 1724 } 1725 } 1726 else { 1727 xprintf("%s: Link speed: %sBaseT %s\n", i82559_devname(sc), 1728 ((linkstat & M_GSTAT_100) != 0 ? "100" : "10"), 1729 ((linkstat & M_GSTAT_FDX) != 0 ? "FDX" : "HDX")); 1730 } 1731 sc->linkstat = linkstat; 1732 } 1733 } 1734} 1735 1736static void 1737i82559_ether_reset(void *softc) 1738{ 1739 /* NYI */ 1740} 1741