Lines Matching defs:WRITECSR
372 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val)))
376 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val)))
381 WRITECSR((sc), R_CSR_BUSMODE, M_CSR0_SWRESET); \
693 WRITECSR(sc, R_CSR_TXPOLL, 1);
730 WRITECSR(sc, R_CSR_OPMODE, opmode);
923 WRITECSR(sc, R_CSR_ROM_MII, csr9);
929 WRITECSR(sc, R_CSR_ROM_MII, csr9);
935 WRITECSR(sc, R_CSR_ROM_MII, csr9);
952 WRITECSR(sc, R_CSR_ROM_MII, csr9);
956 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK);
958 WRITECSR(sc, R_CSR_ROM_MII, csr9);
963 WRITECSR(sc, R_CSR_ROM_MII, csr9);
975 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK); /* rising edge */
977 WRITECSR(sc, R_CSR_ROM_MII, csr9); /* falling edge */
996 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1014 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL);
1030 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1041 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL);
1054 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1073 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1075 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCHIPSEL);
1087 WRITECSR(sc, R_CSR_ROM_MII, csr9 &~ M_CSR9_SROMCHIPSEL);
1124 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMREAD);
1134 WRITECSR(sc, R_CSR_ROM_MII, 0); /* CS hold, Tcsh=0 */
1177 WRITECSR(sc, R_CSR_ROM_MII, 0); /* reset pointer */
1229 WRITECSR(sc, R_CSR_ROMCTL, cmd);
1241 WRITECSR(sc, R_CSR_ROMCTL, csr19);
1321 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1324 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC);
1326 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1338 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1340 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC);
1342 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1387 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1389 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_MDC);
1391 WRITECSR(sc, R_CSR_ROM_MII, csr9);
1525 WRITECSR(sc, R_CSR_OPMODE, opmode);
1642 WRITECSR(sc, R_CSR_SIAMODE0, 0);
1649 WRITECSR(sc, R_CSR_SIAMODE1, M_CSR14_10BT_HD);
1650 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata);
1654 WRITECSR(sc, R_CSR_SIAMODE1, M_CSR14_10BT_FD);
1655 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata);
1659 WRITECSR(sc, R_CSR_SIAMODE1, 0);
1660 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata);
1664 WRITECSR(sc, R_CSR_SIAMODE1, 0);
1665 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata);
1670 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET);
1674 WRITECSR(sc, R_CSR_OPMODE, opmode);
1689 WRITECSR(sc, R_CSR_SIAMODE0, 0);
1696 WRITECSR(sc, R_CSR_OPMODE, opmode);
1703 WRITECSR(sc, R_CSR_SIAMODE1, tempword);
1707 WRITECSR(sc, R_CSR_SIAMODE1, tempword);
1708 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata);
1709 WRITECSR(sc, R_CSR_OPMODE, opmode);
1710 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET);
1713 WRITECSR(sc, R_CSR_STATUS, M_CSR5_LINKPASS); /* try to clear this... */
1736 WRITECSR(sc, R_CSR_STATUS, M_CSR5_LINKPASS);
1795 WRITECSR(sc, R_CSR_SIAMODE0, 0);
1803 WRITECSR(sc, R_CSR_SIAMODE0, v &~ 0xFFFF);
1805 WRITECSR(sc, R_CSR_SIAMODE1, v &~ 0xFFFF);
1807 WRITECSR(sc, R_CSR_SIAMODE2, v | 0xC000); /* WC of HCKR, RMP */
1809 WRITECSR(sc, R_CSR_SIAMODE2, sc->gpdata);
1811 WRITECSR(sc, R_CSR_SIAMODE2, (v &~ 0xFFFF) | M_CSR15_GP_AUIBNC);
1813 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET);
1864 WRITECSR(sc, R_CSR_SIAMODE2, 0x0821 << 16);
1865 WRITECSR(sc, R_CSR_SIAMODE2, 0x0001 << 16);
1867 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000 << 16);
1876 WRITECSR(sc, R_CSR_SIAMODE2, 0x080E << 16);
1877 WRITECSR(sc, R_CSR_SIAMODE2, 0x000E << 16);
1881 WRITECSR(sc, R_CSR_SIAMODE2, 0x0821 << 16);
1882 WRITECSR(sc, R_CSR_SIAMODE2, 0x0001 << 16);
1884 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000 << 16);
1891 WRITECSR(sc, R_CSR_SIAMODE2, 0x080F << 16);
1904 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFFFFFF);
1909 WRITECSR(sc, R_CSR_SIAMODE2, gpr_control | M_CSR15_GP_AUIBNC);
1911 WRITECSR(sc, R_CSR_SIAMODE2, 0x40000); /* release reset */
1916 WRITECSR(sc, R_CSR_SIAMODE2, gpr_control);
1924 WRITECSR(sc, R_CSR_SIAMODE2, M_CSR15_CONFIG_GEPS_LEDS);
1938 WRITECSR(sc, R_CSR_BUSMODE, v);
1946 WRITECSR(sc, R_CSR_OPMODE, v);
1949 /* WRITECSR(sc, R_CSR_SIASTATUS, 0); */
1954 WRITECSR(sc, R_CSR_OPMODE, csr6word &~ (M_CSR6_TXSTART | M_CSR6_RXSTART));
1957 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start));
1958 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start));
1972 WRITECSR(sc, R_CSR_SIAMODE0, 0);
1975 WRITECSR(sc, R_CSR_SIAMODE1, csr14word);
1976 WRITECSR(sc, R_CSR_SIAMODE0, M_CSR13_CONN_NOT_RESET);
2069 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL);
2072 WRITECSR(sc, R_CSR_GENPORT, M_CSR12_CONTROL | gpr_control);
2074 WRITECSR(sc, R_CSR_GENPORT, gpr_data); /* setup PHY */
2090 WRITECSR(sc, R_CSR_BUSMODE, v);
2096 WRITECSR(sc, R_CSR_OPMODE, v);
2101 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART));
2104 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start));
2105 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start));
2129 WRITECSR(sc, R_CSR_OPMODE, opmode);
2139 WRITECSR(sc, R_CSR_SIAMODE0, 0);
2145 WRITECSR(sc, R_CSR_SIAMODE1, 0x7F3F);
2146 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008);
2151 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | M_CSR13_CONN_NOT_RESET);
2155 WRITECSR(sc, R_CSR_OPMODE, opmode);
2164 WRITECSR(sc, R_CSR_SIAMODE0, 0);
2170 WRITECSR(sc, R_CSR_SIAMODE1, 0x7A3F);
2171 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008);
2176 WRITECSR(sc, R_CSR_SIAMODE1, 0x0000);
2177 WRITECSR(sc, R_CSR_SIAMODE2, 0x000E);
2182 WRITECSR(sc, R_CSR_SIAMODE1, 0x7F3F);
2183 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008);
2187 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | mode0 | M_CSR13_CONN_NOT_RESET );
2207 WRITECSR(sc, R_CSR_BUSMODE, v);
2209 WRITECSR(sc, R_CSR_INTMASK, 0);
2211 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start));
2212 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start));
2224 WRITECSR(sc, R_CSR_SIAMODE0, 0);
2230 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFF);
2231 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000);
2235 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFD);
2236 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000);
2241 WRITECSR(sc, R_CSR_SIAMODE0, 0xEF00 | M_CSR13_CONN_NOT_RESET);
2245 WRITECSR(sc, R_CSR_OPMODE, opmode);
2251 WRITECSR(sc, R_CSR_SIAMODE0, 0);
2257 WRITECSR(sc, R_CSR_SIAMODE1, 0xFEFB);
2258 WRITECSR(sc, R_CSR_SIAMODE2, 0x0008);
2262 WRITECSR(sc, R_CSR_SIAMODE1, 0x0000);
2263 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000);
2267 WRITECSR(sc, R_CSR_SIAMODE1, 0xFFFF);
2268 WRITECSR(sc, R_CSR_SIAMODE2, 0x0000);
2271 WRITECSR(sc, R_CSR_SIAMODE0, 0x8F00 | M_CSR13_CONN_NOT_RESET );
2291 WRITECSR(sc, R_CSR_BUSMODE, v);
2293 WRITECSR(sc, R_CSR_INTMASK, 0);
2310 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL);
2313 WRITECSR(sc, R_CSR_GENPORT, M_CSR12_CONTROL | gpr_control);
2315 WRITECSR(sc, R_CSR_GENPORT, gpr_data); /* setup PHY */
2321 WRITECSR(sc, R_CSR_BUSMODE, v);
2327 WRITECSR(sc, R_CSR_OPMODE, v);
2332 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART));
2335 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start));
2336 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start));
2368 WRITECSR(sc, R_CSR_MIIM, cmd);
2392 WRITECSR(sc, R_CSR_MIIM, cmd);
2414 WRITECSR(sc, R_CSR_OPMODE, M_CSR6_PORTSEL);
2418 WRITECSR(sc, R_CSR_GENPORT, gpr_control);
2419 WRITECSR(sc, R_CSR_ENDEC, M_CSR15_EG_JDIS);
2425 WRITECSR(sc, R_CSR_BUSMODE, v);
2431 WRITECSR(sc, R_CSR_OPMODE, v);
2436 WRITECSR(sc, R_CSR_OPMODE, opmode &~ (M_CSR6_TXSTART | M_CSR6_RXSTART));
2439 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start));
2440 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start));
2450 WRITECSR(sc, R_CSR_OPMODE, opmode);
2477 WRITECSR(sc, R_CSR_OPMODE,
2642 WRITECSR(sc, R_CSR_STATUS, status);
2648 WRITECSR(sc, R_CSR_INTMASK, 0);
2663 WRITECSR(sc, R_CSR_INTMASK, sc->intmask);
2685 WRITECSR(sc, R_CSR_TXPOLL, 1);
2689 WRITECSR(sc, R_CSR_RXPOLL, 1);
2703 WRITECSR(sc, R_CSR_RXRING, PTR_TO_PCI(sc, sc->rxdscr_start));
2704 WRITECSR(sc, R_CSR_TXRING, PTR_TO_PCI(sc, sc->txdscr_start));
2718 WRITECSR(sc, R_CSR_INTMASK, 0); /* no interrupts */
2719 WRITECSR(sc, R_CSR_STATUS, 0x1FFFF); /* clear any pending */
2732 WRITECSR(sc, R_CSR_INTMASK, sc->intmask);
2737 WRITECSR(sc, R_CSR_OPMODE, opmode);
2742 WRITECSR(sc, R_CSR_OPMODE, opmode);
2753 WRITECSR(sc, R_CSR_INTMASK, 0);
2758 WRITECSR(sc, R_CSR_STATUS, 0x1FFFF);
2761 WRITECSR(sc, R_CSR_OPMODE, opmode);
2782 WRITECSR(sc, R_CSR_OPMODE, opmode);
3410 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMREAD);
3415 WRITECSR(sc, R_CSR_ROM_MII, 0/*csr9*/);
3431 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMWRITE);
3436 WRITECSR(sc, R_CSR_ROM_MII, 0/*csr9*/);
3453 WRITECSR(sc, R_CSR_ROM_MII, M_CSR9_SERROMSEL|M_CSR9_ROMWRITE);
3458 WRITECSR(sc, R_CSR_ROM_MII, 0/*csr9*/);