cfe/dev/dev_bcm4401.c

287 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val)))
291 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val)))
398     WRITECSR(sc, R_RCV_PTR, V_RPTR_LD(PTR_TO_PCI(nextrxd) & 0xFFF));
553 	WRITECSR(sc, R_XMT_PTR, V_XPTR_LD(PTR_TO_PCI(sc->txdscr_add) & 0xFFF));
702     WRITECSR(sc, R_MII_STATUS_CONTROL, M_MIICTL_PR | V_MIICTL_MD(0xD));
706 	WRITECSR(sc, R_DEV_CONTROL, devctl);
718     WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI);
721     WRITECSR(sc, R_MII_DATA, cmd | V_MIIDATA_SB(K_MII_START));
743     WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI);
747     WRITECSR(sc, R_MII_DATA, cmd | V_MIIDATA_SB(K_MII_START));
941     WRITECSR(sc, R_CAM_DATA_H, M_CAM_VB | V_CAM_CD_H(enet_upper));
942     WRITECSR(sc, R_CAM_DATA_L, V_CAM_CD_L(enet_lower));
944     WRITECSR(sc, R_CAM_CONTROL, V_CAMCTL_IX(0) | M_CAMCTL_CW);
971 	WRITECSR(sc, R_SBINTVEC, V_SBINT_MK(K_SBINT_ENET_MAC));
984     WRITECSR(sc, R_SB_TO_PCI_TRANSLATION2, xlat);
1008     WRITECSR(sc, R_XMT_CONTROL1, ctrl);
1026 	WRITECSR(sc, R_CAM_CONTROL, M_CAMCTL_CE);
1031 	WRITECSR(sc, R_RCV_PTR, 0);
1032 	WRITECSR(sc, R_RCV_CONTROL, M_RCTL_RE | V_RCTL_RO(PKTBUF_RX_OFFSET));
1033 	WRITECSR(sc, R_RCV_ADDR, PTR_TO_PCI(sc->rxdscrmem));
1034 	WRITECSR(sc, R_RCV_PTR, PTR_TO_PCI(sc->rxdscr_add) & 0xFFF);
1037 	WRITECSR(sc, R_XMT_PTR, 0);
1038 	WRITECSR(sc, R_XMT_CONTROL, M_XCTL_XE);
1039 	WRITECSR(sc, R_XMT_ADDR, PTR_TO_PCI(sc->txdscrmem));
1042 	WRITECSR(sc, R_EMAC_XMT_MAX_BURST, 32);
1043 	WRITECSR(sc, R_EMAC_RCV_MAX_BURST, 32);
1045 	WRITECSR(sc, R_RCV_CONFIG, M_RCFG_AM);   /* All multicast */
1047 	WRITECSR(sc, R_RCV_CONFIG, 0);
1049 	WRITECSR(sc, R_RCV_MAX_LENGTH, MAX_ETHER_PACK);
1053 	WRITECSR(sc, R_EMAC_CONTROL, ctrl);
1057 	WRITECSR(sc, R_XMT_MAX_LENGTH, MAX_ETHER_PACK);
1059 	WRITECSR(sc, R_INT_RECV_LAZY, V_INTLZY_FC(1) | V_INTLZY_TO(100));
1064 	WRITECSR(sc, R_ENET_CONTROL, ctrl);
1103 	WRITECSR(sc, R_INT_STATUS, status);  /* write-to-clear */
1146     WRITECSR(sc, R_GP_TIMER, 0);             /* stop the timer */
1149     WRITECSR(sc, R_INT_MASK, 0);
1156     WRITECSR(sc, R_INT_MASK, sc->intmask);
1160     WRITECSR(sc, R_GP_TIMER, GP_TIMER_HZ/4);
1172     WRITECSR(sc, R_GP_TIMER, 0);
1178     WRITECSR(sc, R_INT_MASK, 0);
1183     WRITECSR(sc, R_ENET_CONTROL, M_ECTL_ED);
1194     WRITECSR(sc, R_XMT_CONTROL, 0);
1204     WRITECSR(sc, R_RCV_CONTROL, 0);
1215     WRITECSR(sc, R_INT_STATUS, status);
1306     WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_RS | M_SBTS_CE | M_SBTS_FC);
1312 	WRITECSR(sc, R_SBTMSTATEHI, 0);
1318 	WRITECSR(sc, R_SBIMSTATE, sbis);
1322     WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_CE | M_SBTS_FC);
1325     WRITECSR(sc, R_SBTMSTATELOW, M_SBTS_CE);