Searched refs:hwip (Results 1 - 24 of 24) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.h38 u32 hwip; member in struct:soc15_reg_golden
47 u32 hwip; member in struct:soc15_reg_rlcg
54 uint32_t hwip; member in struct:soc15_reg
61 uint32_t hwip; member in struct:soc15_reg_entry
71 uint32_t hwip; member in struct:soc15_allowed_register_entry
80 uint32_t hwip; member in struct:soc15_ras_field_entry
94 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
H A Damdgpu_imu.h42 u32 hwip; member in struct:imu_rlc_ram_golden
H A Dsoc15_common.h40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \
146 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
148 #define RREG32_RLC_NO_KIQ(reg, hwip) \
149 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
H A Damdgpu_virt.h368 u32 acc_flags, u32 hwip, u32 xcc_id);
370 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
376 u32 acc_flags, u32 hwip,
H A Damdgpu_aca.c183 struct aca_hwip *hwip; local
190 hwip = &aca_hwid_mcatypes[type];
191 if (!hwip->hwid)
198 return hwip->hwid == hwid && hwip->mcatype == mcatype;
205 if (!aca_bank_hwip_is_matched(bank, handle->hwip))
588 handle->hwip = ras_info->hwip;
H A Damdgpu_aca.h152 enum aca_hwip_type hwip; member in struct:aca_handle
187 enum aca_hwip_type hwip; member in struct:aca_info
H A Damdgpu_virt.c923 u32 acc_flags, u32 hwip,
928 switch (hwip) {
1044 u32 acc_flags, u32 hwip, u32 xcc_id)
1049 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
1061 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id)
1066 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
922 amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, bool write, u32 *rlcg_flag) argument
1042 amdgpu_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip, u32 xcc_id) argument
1060 amdgpu_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) argument
H A Damdgpu_ras.h380 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
381 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
391 uint32_t hwip; member in struct:amdgpu_ras_err_status_reg_entry
H A Dimu_v11_0_3.c117 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
H A Dsoc15.c421 if (!adev->reg_offset[en->hwip][en->inst])
423 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
457 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
462 tmp = (entry->hwip == GC_HWIP) ?
475 (entry->hwip == GC_HWIP) ?
H A Dsoc21.c317 if (!adev->reg_offset[en->hwip][en->inst])
319 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
H A Dnv.c397 if (!adev->reg_offset[en->hwip][en->inst])
399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
H A Dimu_v11_0.c328 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
H A Dumc_v12_0.c530 .hwip = ACA_HWIP_TYPE_UMC,
H A Dmmhub_v1_8.c787 .hwip = ACA_HWIP_TYPE_SMU,
H A Damdgpu_ras.c4076 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
4100 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
4177 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
4180 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
H A Damdgpu_xgmi.c1084 .hwip = ACA_HWIP_TYPE_PCS_XGMI,
H A Damdgpu.h143 u32 hwip; member in struct:amdgpu_hwip_reg_entry
H A Dgfx_v9_4_3.c744 .hwip = ACA_HWIP_TYPE_SMU,
1433 adev, entry->hwip, entry->instance) :
1435 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
H A Dsdma_v4_4_2.c2239 .hwip = ACA_HWIP_TYPE_SMU,
H A Dgfx_v9_0.c4927 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
H A Dgfx_v10_0.c8089 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dcommon_baco.h47 uint32_t hwip; member in struct:soc15_baco_cmd_entry
H A Dcommon_baco.c112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]

Completed in 600 milliseconds