1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_ACA_H__
25#define __AMDGPU_ACA_H__
26
27#include <linux/list.h>
28
29#define ACA_MAX_REGS_COUNT	(16)
30
31#define ACA_REG_FIELD(x, h, l)			(((x) & GENMASK_ULL(h, l)) >> l)
32#define ACA_REG__STATUS__VAL(x)			ACA_REG_FIELD(x, 63, 63)
33#define ACA_REG__STATUS__OVERFLOW(x)		ACA_REG_FIELD(x, 62, 62)
34#define ACA_REG__STATUS__UC(x)			ACA_REG_FIELD(x, 61, 61)
35#define ACA_REG__STATUS__EN(x)			ACA_REG_FIELD(x, 60, 60)
36#define ACA_REG__STATUS__MISCV(x)		ACA_REG_FIELD(x, 59, 59)
37#define ACA_REG__STATUS__ADDRV(x)		ACA_REG_FIELD(x, 58, 58)
38#define ACA_REG__STATUS__PCC(x)			ACA_REG_FIELD(x, 57, 57)
39#define ACA_REG__STATUS__ERRCOREIDVAL(x)	ACA_REG_FIELD(x, 56, 56)
40#define ACA_REG__STATUS__TCC(x)			ACA_REG_FIELD(x, 55, 55)
41#define ACA_REG__STATUS__SYNDV(x)		ACA_REG_FIELD(x, 53, 53)
42#define ACA_REG__STATUS__CECC(x)		ACA_REG_FIELD(x, 46, 46)
43#define ACA_REG__STATUS__UECC(x)		ACA_REG_FIELD(x, 45, 45)
44#define ACA_REG__STATUS__DEFERRED(x)		ACA_REG_FIELD(x, 44, 44)
45#define ACA_REG__STATUS__POISON(x)		ACA_REG_FIELD(x, 43, 43)
46#define ACA_REG__STATUS__SCRUB(x)		ACA_REG_FIELD(x, 40, 40)
47#define ACA_REG__STATUS__ERRCOREID(x)		ACA_REG_FIELD(x, 37, 32)
48#define ACA_REG__STATUS__ADDRLSB(x)		ACA_REG_FIELD(x, 29, 24)
49#define ACA_REG__STATUS__ERRORCODEEXT(x)	ACA_REG_FIELD(x, 21, 16)
50#define ACA_REG__STATUS__ERRORCODE(x)		ACA_REG_FIELD(x, 15, 0)
51
52#define ACA_REG__IPID__MCATYPE(x)		ACA_REG_FIELD(x, 63, 48)
53#define ACA_REG__IPID__INSTANCEIDHI(x)		ACA_REG_FIELD(x, 47, 44)
54#define ACA_REG__IPID__HARDWAREID(x)		ACA_REG_FIELD(x, 43, 32)
55#define ACA_REG__IPID__INSTANCEIDLO(x)		ACA_REG_FIELD(x, 31, 0)
56
57#define ACA_REG__MISC0__VALID(x)		ACA_REG_FIELD(x, 63, 63)
58#define ACA_REG__MISC0__OVRFLW(x)		ACA_REG_FIELD(x, 48, 48)
59#define ACA_REG__MISC0__ERRCNT(x)		ACA_REG_FIELD(x, 43, 32)
60
61#define ACA_REG__SYND__ERRORINFORMATION(x)	ACA_REG_FIELD(x, 17, 0)
62
63/* NOTE: The following codes refers to the smu header file */
64#define ACA_EXTERROR_CODE_CE			0x3a
65#define ACA_EXTERROR_CODE_FAULT			0x3b
66
67#define ACA_ERROR_UE_MASK		BIT_MASK(ACA_ERROR_TYPE_UE)
68#define ACA_ERROR_CE_MASK		BIT_MASK(ACA_ERROR_TYPE_CE)
69#define ACA_ERROR_DEFERRED_MASK		BIT_MASK(ACA_ERROR_TYPE_DEFERRED)
70
71enum aca_reg_idx {
72	ACA_REG_IDX_CTL			= 0,
73	ACA_REG_IDX_STATUS		= 1,
74	ACA_REG_IDX_ADDR		= 2,
75	ACA_REG_IDX_MISC0		= 3,
76	ACA_REG_IDX_CONFG		= 4,
77	ACA_REG_IDX_IPID		= 5,
78	ACA_REG_IDX_SYND		= 6,
79	ACA_REG_IDX_DESTAT		= 8,
80	ACA_REG_IDX_DEADDR		= 9,
81	ACA_REG_IDX_CTL_MASK		= 10,
82	ACA_REG_IDX_COUNT		= 16,
83};
84
85enum aca_hwip_type {
86	ACA_HWIP_TYPE_UNKNOW = -1,
87	ACA_HWIP_TYPE_PSP = 0,
88	ACA_HWIP_TYPE_UMC,
89	ACA_HWIP_TYPE_SMU,
90	ACA_HWIP_TYPE_PCS_XGMI,
91	ACA_HWIP_TYPE_COUNT,
92};
93
94enum aca_error_type {
95	ACA_ERROR_TYPE_INVALID = -1,
96	ACA_ERROR_TYPE_UE = 0,
97	ACA_ERROR_TYPE_CE,
98	ACA_ERROR_TYPE_DEFERRED,
99	ACA_ERROR_TYPE_COUNT
100};
101
102struct aca_bank {
103	u64 regs[ACA_MAX_REGS_COUNT];
104};
105
106struct aca_bank_node {
107	struct aca_bank bank;
108	struct list_head node;
109};
110
111struct aca_bank_info {
112	int die_id;
113	int socket_id;
114	int hwid;
115	int mcatype;
116};
117
118struct aca_bank_report {
119	struct aca_bank_info info;
120	u64 count[ACA_ERROR_TYPE_COUNT];
121};
122
123struct aca_bank_error {
124	struct list_head node;
125	struct aca_bank_info info;
126	u64 count[ACA_ERROR_TYPE_COUNT];
127};
128
129struct aca_error {
130	struct list_head list;
131	struct mutex lock;
132	enum aca_error_type type;
133	int nr_errors;
134};
135
136struct aca_handle_manager {
137	struct list_head list;
138	int nr_handles;
139};
140
141struct aca_error_cache {
142	struct aca_error errors[ACA_ERROR_TYPE_COUNT];
143};
144
145struct aca_handle {
146	struct list_head node;
147	enum aca_hwip_type hwip;
148	struct amdgpu_device *adev;
149	struct aca_handle_manager *mgr;
150	struct aca_error_cache error_cache;
151	const struct aca_bank_ops *bank_ops;
152	struct device_attribute aca_attr;
153	char attr_name[64];
154	const char *name;
155	u32 mask;
156	void *data;
157};
158
159struct aca_bank_ops {
160	int (*aca_bank_generate_report)(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,
161					struct aca_bank_report *report, void *data);
162	bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type,
163				  void *data);
164};
165
166struct aca_smu_funcs {
167	int max_ue_bank_count;
168	int max_ce_bank_count;
169	int (*set_debug_mode)(struct amdgpu_device *adev, bool enable);
170	int (*get_valid_aca_count)(struct amdgpu_device *adev, enum aca_error_type type, u32 *count);
171	int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_error_type type, int idx, struct aca_bank *bank);
172};
173
174struct amdgpu_aca {
175	struct aca_handle_manager mgr;
176	const struct aca_smu_funcs *smu_funcs;
177	bool is_enabled;
178};
179
180struct aca_info {
181	enum aca_hwip_type hwip;
182	const struct aca_bank_ops *bank_ops;
183	u32 mask;
184};
185
186int amdgpu_aca_init(struct amdgpu_device *adev);
187void amdgpu_aca_fini(struct amdgpu_device *adev);
188int amdgpu_aca_reset(struct amdgpu_device *adev);
189void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs);
190bool amdgpu_aca_is_enabled(struct amdgpu_device *adev);
191
192int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info);
193int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size);
194
195int amdgpu_aca_add_handle(struct amdgpu_device *adev, struct aca_handle *handle,
196			  const char *name, const struct aca_info *aca_info, void *data);
197void amdgpu_aca_remove_handle(struct aca_handle *handle);
198int amdgpu_aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *handle,
199				     enum aca_error_type type, void *data);
200int amdgpu_aca_smu_set_debug_mode(struct amdgpu_device *adev, bool en);
201void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);
202#endif
203