#
2757a848 |
|
23-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Explicitly disable ASPM when dynamic switching disabled Currently there are separate but related checks: * amdgpu_device_should_use_aspm() * amdgpu_device_aspm_support_quirk() * amdgpu_device_pcie_dynamic_switching_supported() Simplify into checking whether DPM was enabled or not in the auto case. This works because amdgpu_device_pcie_dynamic_switching_supported() populates that value. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1a6513de |
|
23-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move AMD_IS_APU check for ASPM into top level function There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e0a3e7bf |
|
29-Sep-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Drop unnecessary return statements There is no reason to call return at the end of function that returns void. Fixes the below: WARNING: void function return statements are not generally useful Thus remove such a statement in the affected functions. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4e8303cf |
|
11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
939a392f |
|
02-Aug-2023 |
Ran Sun <sunran001@208suo.com> |
drm/amdgpu: Clean up errors in nv.c Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
36f3f375 |
|
27-Jul-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use nbio callback for nv and soc21 Make the new ascis to follow nbio callback method to get pcie replay count. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f05f4fe6 |
|
25-Jul-2023 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable SDMA MGCG for SDMA 5.2.x Now the SDMA firmware can support SDMA MGCG properly, so let's enable it from the driver side. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
20a29ac0 |
|
19-May-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: retire set_vga_state for some ASIC set_vga_state operation only allowed on SI generation ASIC, retire the realted function on those ASIC which did not do anything. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6fa6fe9 |
|
01-May-2023 |
Thong Thai <thong.thai@amd.com> |
drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution Update the maximum resolution reported for HEVC encoding on VCN 3 devices to reflect its 8K encoding capability. v2: Also update the max height for H.264 encoding to match spec. (Ruijing) Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1c312e81 |
|
25-Apr-2023 |
Shane Xiao <shane.xiao@amd.com> |
drm/amdgpu: Enable doorbell selfring after resize FB BAR [Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <shane.xiao@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Tested-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Christian K�nig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
476ac50f |
|
01-May-2023 |
Thong Thai <thong.thai@amd.com> |
drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution Update the maximum resolution reported for HEVC encoding on VCN 3 devices to reflect its 8K encoding capability. v2: Also update the max height for H.264 encoding to match spec. (Ruijing) Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b03f38b9 |
|
25-Apr-2023 |
Shane Xiao <shane.xiao@amd.com> |
drm/amdgpu: Enable doorbell selfring after resize FB BAR [Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <shane.xiao@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Tested-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Christian K�nig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
86b20703 |
|
27-Jul-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to rlc safe_mode func (v4) v1: To support multple XCD case (Le) v2: unify naming style (Le) v3: apply the changes to gc v11_0 (Hawking) v4: apply the changes to gc SOC21 (Morris) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Morris Zhang <Shiwu.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d51ac6d0 |
|
23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to select_sh_se function v2 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ad5dcfe |
|
15-Mar-2023 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default"). The root cause is still not clear for now. So extend and apply the ASPM quirk from commit e02fe3bc7aba ("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to workaround the issue on Navi cards too. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4489f0fd |
|
06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Retire pcie_gen3_enable function Not needed since from vi. drop the function so we don't duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dabc114e |
|
06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move to common helper to query soc rev_id Replace soc15, nv, soc21 get_rev_id callback with common helper so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
65ba96e9 |
|
06-Mar-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Move to common indirect reg access helper Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
84b31d48 |
|
08-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: fix codec array for SR_IOV Copy paste error. Fixes: 384334120b66 ("drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested") Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4454 Cc: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
920da947 |
|
07-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix error checking in amdgpu_read_mm_registers for nv Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2b072442 |
|
15-Mar-2023 |
Kai-Heng Feng <kai.heng.feng@canonical.com> |
drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default"). The root cause is still not clear for now. So extend and apply the ASPM quirk from commit e02fe3bc7aba ("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to workaround the issue on Navi cards too. Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default") Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
45aa07fa |
|
08-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: fix codec array for SR_IOV Copy paste error. Fixes: 384334120b66 ("drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested") Reported-by: Abaci Robot <abaci@linux.alibaba.com> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4454 Cc: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b42fee5e |
|
07-Mar-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix error checking in amdgpu_read_mm_registers for nv Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
38433412 |
|
13-Jan-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested Only VCN0 supports AV1. Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
65009bf2 |
|
23-Nov-2022 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c: Corrected typo in the video capabilities resolution Corrected the typo in the 4K resolution parameters. Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
97e50305 |
|
26-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: update VCN codec support for Yellow Carp Supports AV1. Mesa already has support for this and doesn't rely on the kernel caps for yellow carp, so this was already working from an application perspective. Fixes: 554398174d98 ("amdgpu/nv.c - Added video codec support for Yellow Carp") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2002 Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
bf1781e1 |
|
04-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: simplify nv and soc21 read_register functions Check of the base offset for the IP exists rather than explicitly checking for how many instances of a particular IP there are. This is what soc15.c already does. Expand this to nv.c and soc21.c. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fd0ed91a |
|
12-Apr-2022 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: correct cp doorbell range 1. move MES doorbell inside the mec doorbell range, for mes belongs to mec block 2. setting the correct gfx/mec doorbell range, so that fw can correctly detect gfx/compute work load to enter/exit power saving state. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Tested-and-acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b608e785 |
|
14-Apr-2021 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: allocate doorbell index for mes kiq Allocate a doorbell index for mes kiq queue. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
25faeddc |
|
25-Mar-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expand cg_flags from u32 to u64 With this, we can support more CG flags. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fabe1753 |
|
28-Feb-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable gfx power gating for GC 10.3.7 Enable gfx power gating for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a1358bb |
|
28-Feb-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblock This will enable the following block clock gating. - MC - SDMA - HDP - ATHUB - IH - VCN/JPEG Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
db749b76 |
|
22-Feb-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/nv: set mode2 reset for MP1 13.0.8 Set mode2 reset support for MP1 13.0.8. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e148e8c |
|
20-Feb-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/nv: enable gfx10.3.7 clock gating support This will enable the following gfx clock gating. - Fine clock gating - Medium Grain clock gating - 3D Coarse clock gating - Coarse Grain clock gating - RLC/CP light sleep clock gating Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50439060 |
|
22-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add mode2 reset support for smu 13.0.5 This patch adds mode2 reset support for smu 13.0.5. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
87b5e77f |
|
08-Feb-2022 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable vcn pg and cg for vcn 3.1.2 Enable PG and CG for VCN/JPEG Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
afc2f276 |
|
28-Oct-2021 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu/vcn: add vcn support for vcn 3.1.2 Load VCN FW, set caps. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
50e14a62 |
|
02-Dec-2021 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add Clock and Power Gating support for gc 10.3.6 Add below supports: GFX Coarse Grain Clock Gating(CGCG) GFX Coarse grain light sleep/deep sleep(CGLS) GFX Medium Grain Clock Gating(MGCG) GFX Medium Grain light sleep/deep sleep(MGLS) GFX Fine Grain Clock Gating(FGCG) RLC MGLS CP MGLS MMHUB Clock Gating SDMA Clock Gating HDP Clock Gating ATHUB Clock Gating IH Clock Gating GFX Power Gating Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1957f27d |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add nv common init for gc 10.3.6 This patch adds add nv common init for gc 10.3.6. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d01899d3 |
|
16-Feb-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Use amdgpu_device_should_use_aspm on navi umd pstate switching The `program_aspm` callback is already guarded for aspm, but the `enable_aspm` callback doesn't follow the module parameter. Update it to use the helper `amdgpu_device_should_use_aspm`. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0ab5d711 |
|
16-Feb-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Refactor `amdgpu_aspm` to be evaluated per device Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
35c27d95 |
|
28-Jan-2022 |
Sathishkumar S <sathishkumar.sundararaju@amd.com> |
drm/amdgpu: update vcn/jpeg PG flags for VCN 3.1.1 update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b67f00e0 |
|
09-Jan-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: set new revision id for 10.3.7 GC Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f9ed188d |
|
08-Feb-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add support for GC 10.1.4 Add basic support for GC 10.1.4, it uses same IP blocks with GC 10.1.3 Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
04022982 |
|
10-Jan-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to common helper to read bios from rom create a common helper function for soc15 and onwards to read bios image from rom Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
86700a40 |
|
18-Jan-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/amdgpu: modify a pair of functions for the pcie port wreg/rreg This patch will modify a pair of functions for pcie port wreg/rreg. AMD GPU have had an independent NBIO block from SOC15 arch. If the dirver wants to read/write the address space of the pcie devices, it has to go through the NBIO block. This patch will move the pcie port wreg/rreg functions to "amdgpu_device.c", so that to reuse the functions on the future GPU ASICs. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
baf3f8f3 |
|
30-Nov-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: handle SRIOV VCN revision parsing For SR-IOV, the IP discovery revision number encodes additional information. Handle that case here. v2: drop additional IP versions Reviewed-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
981b3045 |
|
23-Nov-2021 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID [WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3993811 |
|
04-Nov-2021 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Fix MMIO HDP flush on SRIOV Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
da3b36a2 |
|
23-Nov-2021 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID [WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d3a21f7e |
|
04-Nov-2021 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdgpu: Fix MMIO HDP flush on SRIOV Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4d395f93 |
|
09-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64) Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking") Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bf99b9b0 |
|
11-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop nv_set_ip_blocks() No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5efacdf0 |
|
18-Oct-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: support B0&B1 external revision id for yellow carp B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1d789535 |
|
04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3e67f4f2 |
|
27-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: convert to IP version checking Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a1f62df7 |
|
26-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: export common IP functions So they can be driven by IP dicovery table. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f76f795a |
|
09-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move headless sku check into harvest function Consolidate harvesting information. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3f68c01b |
|
25-Sep-2021 |
Zhan Liu <zhan.liu@amd.com> |
drm/amd/display: add cyan_skillfish display support [Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Jun Lei <jun.lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
53c2ff8b |
|
18-Oct-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: support B0&B1 external revision id for yellow carp B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
733ee71a |
|
18-Jun-2021 |
Ryan Taylor <Ryan.Taylor@amd.com> |
drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3) Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
641df099 |
|
13-Jul-2021 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: enable SMU for cyan_skilfish Enable SMU support for cyan_skilfish. v2: Squash in fix (Alex) Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1c7916af |
|
16-Jun-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: enable psp v11.0.8 for cyan_skillfish Add psp v11.0.8 to ip block initialization. v2: use APU flags (Alex) Signed-off-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
338b3cf0 |
|
01-Jun-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add nbio support for cyan_skillfish nbio version is 2.3. v2: Make it more explicit (Alex) Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b515937b |
|
13-Jul-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add chip early init for cyan_skillfish Set cg/pg flags and rev id for cyan_skillfish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f36fb5a0 |
|
13-Jul-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: set ip blocks for cyan_skillfish Add ip blocks for cyan_skillfish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
70839197 |
|
13-Jul-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: dynamic initialize ip offset for cyan_skillfish Add ip offset definition for cyan_skillfish and initialize it. v2: squash in ip_offset updates (Alex) Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e97c8d86 |
|
01-Jun-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: update yellow carp external rev_id handling 0x1681 has a different external revision id. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f72ac409 |
|
19-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
drm/amdgpu - Corrected the video codecs array name for yellow carp Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9075096b |
|
13-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Optimize code for video codec support structure Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
55439817 |
|
09-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Added video codec support for Yellow Carp Added the supported codecs in the video capabilities query. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d80cded9 |
|
19-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
drm/amdgpu - Corrected the video codecs array name for yellow carp Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ab7a11bd |
|
01-Jun-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: update yellow carp external rev_id handling 0x1681 has a different external revision id. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6505d6fc |
|
13-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Optimize code for video codec support structure Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ea272ce4 |
|
09-Jul-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Added video codec support for Yellow Carp Added the supported codecs in the video capabilities query. Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9f6a7857 |
|
22-Jun-2021 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: move apu flags initialization to the start of device init In some asics, we need to adjust the behavior according to the apu flags at very early stage. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b3a24461 |
|
18-Jun-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
amdgpu/nv.c - Added codec query for Beige Goby Added the Beige Goby capabilities in codec query. v2: fix build error and indent (James) Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
adcf949e |
|
25-May-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix the hang caused by PCIe link width switch SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
5a5da8ae |
|
24-May-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix NAK-G generation during PCI-e link width switch A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
c8b73f7f |
|
18-May-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amdgpu: Add DC support and display block for Yellow Carp To enable output on real display instead of virtual. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bdc974cf |
|
28-Apr-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add video_codecs query support for yellow carp Add video_codecs query support for yellow carp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7d38d9dc |
|
14-Apr-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add mode2 reset support for yellow carp This patch adds mode2 reset support for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
948b1216 |
|
20-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: enable VCN PG and CG for yellow carp Enable VCN 3.0 PG and CG for Yellow Carp by setting up flags. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
54f4f6f3 |
|
13-Jan-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable vcn dpg mode on yellow carp Enable vcn dpg mode on yellow carp. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ee8d893f |
|
13-Jan-2021 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable vcn/jpeg on yellow carp Enable vcn/jpeg IP on yellow carp. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
db72c3fa |
|
12-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add IH Clock Gating support for yellow carp IH CG need to be enabled by driver. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b7dd14c7 |
|
12-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add ATHUB Clock Gating support for yellow carp ATHUB MGCG/MGLS is enabled by default. Adding ATHUB MGCG/MGLS flag to ensure athub mgcg/ls enabled. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6bd95572 |
|
12-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add HDP Clock Gating support for yellow carp HDP MGCG is enabled by default. Adding AMD_CG_SUPPORT_HDP_MGCG to ensure hdp mgcg enabled. HDP MGLS need to be enabled by driver. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f1e9aa65 |
|
10-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add SDMA Clock Gating support for yellow carp Add AMD_CG_SUPPORT_SDMA_LS support. SDMA MGCG programming is migrated to RLC. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fd0a316e |
|
06-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add GFX Power Gating support for yellow carp Add GFX Power Gating support. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
83ae09b5 |
|
05-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add MMHUB Clock Gating support for yellow carp Add AMD_CG_SUPPORT_MC_MGCG/AMD_CG_SUPPORT_MC_LS support. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9c6c48e6 |
|
05-Jan-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add GFX Clock Gating support for yellow carp Add below supports: GFX Coarse Grain Clock Gating(CGCG) GFX Coarse grain light sleep/deep sleep(CGLS) GFX Medium Grain Clock Gating(MGCG) GFX Medium Grain light sleep/deep sleep(MGLS) GFX Fine Grain Clock Gating(FGCG) RLC MGLS CP MGLS Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
903bb18b |
|
25-Mar-2021 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: enable psp_v13 for yellow carp This patch enables psp_v13 for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
120a6db4 |
|
03-Dec-2020 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add smu ip block for yellow carp(V3) Yellow carp smu ip version: 13_0_1. V2: rename smu_v13_0 to smu_v13_0_1. V3: reuse smu_v13_0 with aldebaran. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c462ca9 |
|
03-Nov-2020 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: set ip blocks for yellow carp Enable ip blocks for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e7990721 |
|
03-Nov-2020 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu: add nv common ip block support for yellow carp This patch adds common ip support for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2a4021cc |
|
25-May-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Change IP init sequence to support PSP program IH_RB_CNTL on NV12 SRIOV To enable PSP program IH_RB_CNTL, the PSP IP should be initialized before IH IP, otherwise, it will hit psp NULL pointer. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f2958a8b |
|
22-Apr-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4aa7e6e0 |
|
11-May-2021 |
YuBiao Wang <YuBiao.Wang@amd.com> |
drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid [Why] IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it. [How] Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov. Reviewed-by: Chen, Horace <Horace.Chen@amd.com> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ddaed58b |
|
10-Mar-2021 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/amdgpu: Enable DCN IP init for Beige Goby [Why&How] Adds DCN IP block initialization for Beige Goby Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d69d278f |
|
22-Apr-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add cgls for beige_goby Enable cgls to improve the runtime power efficiency. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e47e4c0e |
|
01-Apr-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
drm/amdgpu: enabled VCN3.0 CG for BEIGE GOBY Enable VCN CG for BEIGE GOBY Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a764bef3 |
|
19-Mar-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable ih CG for beige_goby Enable ih clock gating for beige_goby. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
170c193f |
|
19-Mar-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable hdp CG and LS for beige_goby Enable hdp MGCG and LS for beige_goby. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5d36b865 |
|
19-Mar-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable mc CG and LS for beige_goby Enable mc CG and LS for beige_goby. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
147de218 |
|
19-Mar-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable athub/mmhub PG for beige_goby Enable athub/mmhub power gating for beige_goby. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bc6bd46b |
|
19-Mar-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable GFX clock gating for beige_goby Enable GFX MGCG, CGCG and 3DCG for beige_goby. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5ed7715d |
|
11-Mar-2021 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/pm: add mode1 support for beige_goby Add mode1 reset as the default reset method for beige_goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f703d4b6 |
|
10-Mar-2021 |
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> |
drm/amdgpu: Enable VCN for Beige Goby Enabled VCN support for Beige Goby chip Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c0729819 |
|
10-Nov-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add psp support for beige_goby add general PSP support for beige_goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4d352669 |
|
02-Nov-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add smu support for beige_goby Use soft-pptable for beige_goby v2: fix format Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5663da86 |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add virtual display support for beige_goby Add virtual ip block for beige_goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8760403e |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add sdma ip block for beige_goby Enable sdma block for beige_goby, same as sienna_cichlid v2: share the same setting of sdma instance num with vangogh Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Suggested-by: Alexander Deucher <Alexander.Deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
898319ca |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add gfx ip block for beige_goby Enable gfx block for beige_goby, same as dimgrey_cavefish Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a1dede36 |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add ih ip block for beige_goby Enable ih block for beige_goby, same as dimgrey_cavefish Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2d527ea6 |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add gmc ip block for beige_goby Enable gmc block for beige_goby, same as sienna_cichlid Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aa2caa2a |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add common ip block for beige_goby Same as dimgrey_cavefish v2: fix comments typo Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fd5b4b44 |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: initialize IP offset for beige_goby Add ip offset definition for beige_goby and initialize it v2: squash in fixes (Alex) V3: fix permissions on file (Alex) Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8573035a |
|
13-Oct-2020 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amd/amdgpu: add common support for beige_goby Add external id and set clock gating for beige_goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ed9d2053 |
|
12-May-2021 |
Bokun Zhang <bokun.zhang@amd.com> |
drm/amdgpu: Complete multimedia bandwidth interface - Update SRIOV PF2VF header with latest revision - Extend existing function in amdgpu_virt.c to read MM bandwidth config from PF2VF message - Add SRIOV Sienna Cichlid codec array and update the bandwidth with PF2VF message v2: squash in removal of unused variable (Alex) Signed-off-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Monk liu <monk.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0064b0ce |
|
10-May-2021 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/pm: enable ASPM by default Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
32358093 |
|
06-May-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: update the method for harvest IP for specific SKU Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7bd939d0 |
|
29-Apr-2021 |
Likun GAO <Likun.Gao@amd.com> |
drm/amdgpu: add judgement when add ip blocks (v2) Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ec0f72cb |
|
23-Apr-2021 |
Jinzhou Su <Jinzhou.Su@amd.com> |
drm/amdgpu: Enable SDMA LS for Vangogh Add flags AMD_CG_SUPPORT_SDMA_LS for Vangogh. Start to open sdma ls from firmware version 70. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1d712be9 |
|
22-Apr-2021 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: add cgls enable cgls to improve the runtime power efficiency. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ef9bcfde |
|
20-Apr-2021 |
Jinzhou Su <Jinzhou.Su@amd.com> |
drm/amdgpu: Enable SDMA MGCG for Vangogh Add flags AMD_CG_SUPPORT_SDMA_MGCG for Vangogh. Start to open sdma mgcg from firmware version 70. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c1a3768 |
|
06-May-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: update the method for harvest IP for specific SKU Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
83a0b863 |
|
29-Apr-2021 |
Likun GAO <Likun.Gao@amd.com> |
drm/amdgpu: add judgement when add ip blocks (v2) Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3273f8b9 |
|
14-Apr-2021 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: enable ASPM on navi1x enable ASPM on navi1x for the benifit of system power consumption without performance hurt. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
181e772f |
|
19-Mar-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop redundant and unneeded BACO APIs V2 Use other APIs which are with the same functionality but much more clean. V2: drop mediate unneeded interface Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6ce68e6 |
|
19-Mar-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: label these APIs used internally as static Also drop unnecessary header file and declarations. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fe68ceef |
|
18-Mar-2021 |
Xiaojian Du <Xiaojian.Du@amd.com> |
Revert "drm/amdgpu: disable gpu reset on Vangogh for now" This reverts commit 33cf440d594bfbf81fc20604957bc64f02d0b560. And it will enable mode-2 gpu reset for vangogh, it asks PSP firmware version is 00.1A.00.0F or newer. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5c03e584 |
|
19-Nov-2020 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu:add smu mode1/2 support for aldebaran Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f786950 |
|
02-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/codec: drop the internal codec index And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3b246e8b |
|
07-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3) For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
650bc7ae |
|
24-Feb-2021 |
Asher.Song <Asher.Song@amd.com> |
drm/amdgpu:disable VCN for Navi12 SKU Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Asher.Song <Asher.Song@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c61ac81 |
|
24-Feb-2021 |
Asher.Song <Asher.Song@amd.com> |
drm/amdgpu:disable VCN for Navi12 SKU Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Asher.Song <Asher.Song@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
|
#
f172865a |
|
04-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: add PCI reset support Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1001f2a1 |
|
03-Feb-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: support rom clockgating related function for NV family Add functions to support enable/disable rom clock gating and get rom clock gating status. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0bf7f2dc |
|
03-Feb-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: switch to use smuio callbacks for NV family Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e1edaeaf |
|
31-Jan-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: support ASPM for some specific ASIC Support to program ASPM and LTR for Sienna Cichlid and forward ASIC. Disable ASPM for Sienna Cichlid and forward ASIC by default. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
33cf440d |
|
26-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: disable gpu reset on Vangogh for now Until the issues in the SMU firmware are fixed. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com>
|
#
b913ec62 |
|
25-Nov-2020 |
Alex Deucher <alexdeucher@gmail.com> |
drm/amdgpu: fix mode2 reset sequence for vangogh We need to save and restore PCI config space. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com>
|
#
16086355 |
|
25-Nov-2020 |
Alex Deucher <alexdeucher@gmail.com> |
drm/amdgpu/nv: add mode2 reset handling Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com>
|
#
bf087285 |
|
28-Dec-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: switch hdp callback functions for hdp v5 Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
15ed44c0 |
|
15-Dec-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: set mode1 reset as default for dimgrey_cavefish Use mode1 reset for dimgrey_cavefish by default. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
acf2740f |
|
16-Oct-2020 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/sriov: reopen sienna_child smu ip block under sriov open smu ip block meets with one-vf mode need Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
38a25091 |
|
05-Nov-2020 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: enable DCN for navi10 headless SKU There is a NULL pointer crash when DCN disabled on headless SKU. On normal SKU, the variable adev->ddev.mode_config.funcs is initialized in dm_hw_init(), and it is fine to access it in amdgpu_device_resume(). But on headless SKU, DCN is disabled, the funcs variable is not initialized, then crash arises. Enable DCN to fix this issue. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8301f6b9 |
|
05-Nov-2020 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: enable DCN for navi10 headless SKU There is a NULL pointer crash when DCN disabled on headless SKU. On normal SKU, the variable adev->ddev.mode_config.funcs is initialized in dm_hw_init(), and it is fine to access it in amdgpu_device_resume(). But on headless SKU, DCN is disabled, the funcs variable is not initialized, then crash arises. Enable DCN to fix this issue. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a3964ec4 |
|
02-Nov-2020 |
Jinzhou.Su <Jinzhou.Su@amd.com> |
drm/amdgpu: Enable FGCG for Vangogh Add flags AMD_CG_SUPPORT_GFX_FGCG for Vangogh Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0ebce667 |
|
30-Oct-2020 |
Jinzhou.Su <Jinzhou.Su@amd.com> |
amdgpu: Add mmhub MGCG and MGLS for vangogh Add AMD_CG_SUPPORT_MC_MGCG and AMD_CG_SUPPORT_MC_LS Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4f0a1c99 |
|
28-Oct-2020 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu: rename nv_is_headless_sku() for headless NAVI ASICs Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
06a5af1f |
|
27-Oct-2020 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKU Navi14 0x7340/C9 SKU has no display and video support, remove them. Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
51a7e938 |
|
27-Oct-2020 |
Jinzhou.Su <Jinzhou.Su@amd.com> |
amdgpu: Add GFX MGCG and MGLS for vangogh add GFX Medium Grain Light Sleep support for vangogh add AMD_CG_SUPPORT_GFX_CP_LS and AMD_CG_SUPPORT_GFX_RLC_LS v2: add GFX Medium Grain Clock Gating Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9c94b5ef |
|
28-Oct-2020 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu: rename nv_is_headless_sku() for headless NAVI ASICs Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dd657888 |
|
27-Oct-2020 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKU Navi14 0x7340/C9 SKU has no display and video support, remove them. Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c345c89b |
|
26-Oct-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add vangogh apu flag This patch is to add vangogh apu flag to support more kickers that belongs vangogh series. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a305e7dc |
|
21-Oct-2020 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3) The blockchain SKU has no display and video support, remove them. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0165b85c |
|
23-Oct-2020 |
Xiaomeng Hou <Xiaomeng.Hou@amd.com> |
drm/amdgpu: enable IP discovery for vangogh enable IP discovery for vangogh. Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aa5375c5 |
|
21-Oct-2020 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3) The blockchain SKU has no display and video support, remove them. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
07f9c22f |
|
16-Oct-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable VCN PG and CG for vangogh Enable VCN 3.0 PG and CG for Vangogh by setting up flags. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
84b934bc |
|
14-Oct-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/display: enable display ip block for vangogh This patch is to enable display IP block for vangogh platforms. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
27747293 |
|
18-Aug-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2) Fulfill Navi gfx and pcie settings on umd pstate switching. V2: temporarily skip the pcie ASPM setting considering the ASPM function is not fully enabled yet Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7cc656e2 |
|
10-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add DM block for dimgrey_cavefish Add DM block support for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8e3bfb99 |
|
10-Aug-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable ih CG for dimgrey_cavefish Set ih CG flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2c70c332 |
|
10-Aug-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable hdp CG and LS for dimgrey_cavefish Set hdp CG and LS flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aff39cde |
|
04-Jun-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add psp and smu block for dimgrey_cavefish Add psp and smu block for dimgrey_cavefish with psp firmware load type. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by:Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
be6b1cd3 |
|
22-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable jpeg3.0 for dimgrey_cavefish Enable jpeg3.0 ip block for dimgrey_cavefish. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0afc770b |
|
22-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable vcn3.0 for dimgrey_cavefish Enable vcn3.0 ip block for dimgrey_cavefish. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
73da8e86 |
|
10-Aug-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable athub/mmhub PG for dimgrey_cavefish Set athub/mmhub PG flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
135333a0 |
|
10-Aug-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable mc CG and LS for dimgrey_cavefish Set mc CG and LS flag for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
583e5a5e |
|
10-Aug-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: enable GFX clock gating for dimgrey_cavefish Enable GFX MGCG, CGCG and 3DCG for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cc6161aa |
|
05-Aug-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable jpeg3.0 PG and CG for dimgrey_cavefish Enable JPEG3.0 PG and CG for dimgrey_cavefish. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d5bc1579 |
|
05-Aug-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable VCN3.0 PG and CG for dimgrey_cavefish Enable VCN3.0 PG and CG for dimgrey_cavefish Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
467db422 |
|
22-Jul-2020 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/vcn: enable VCN DPG mode for dimgrey_cavefish Enable VCN DPG mode for dimgrey_cavefish. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
76a2d9ea |
|
10-Mar-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add virtual display support for dimgrey_cavefish Add virtual ip block for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
01069226 |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add sdma ip block for dimgrey_cavefish Enable sdma block for dimgrey_cavefish, same as sienna_cichlid. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
feb6329c |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add gfx ip block for dimgrey_cavefish Enable gfx block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
771cc67e |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add ih ip block for dimgrey_cavefish Enable ih block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3e02ad44 |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add gmc ip block for dimgrey_cavefish Enable gmc block for dimgrey_cavefish, same as sienna_cichlid. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2aa92b12 |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add common ip block for dimgrey_cavefish Same as navy_flounder. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
038d757b |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: initialize IP offset for dimgrey_cavefish Add ip offset definition for dimgrey_cavefish and initialize it. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
550c58e0 |
|
02-Oct-2020 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add common support for dimgrey_cavefish Add external id and set clock gating for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ac0dc4c5 |
|
22-Sep-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable gfx clock gating and power gating for vangogh This patch is to enable the gfx cg and pg for vangogh. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8bb3aa1a |
|
28-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: IP discovery table is not ready yet for VG Fallback to legacy path for now. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ed3b7353 |
|
16-Sep-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: enable psp support for vangogh This patch is to enable psp support for vangogh Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c821e0fb |
|
28-May-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add smu ip block for vangogh This patch is to add ip block for vangogh. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7e91bd7 |
|
26-Aug-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add nbio v7.2 for vangogh (v2) VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio v2.3 for navi series, so add new nbio v7.2 block. v2: squash in fix for sdma and vcn instances Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5de54343 |
|
26-Aug-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add pcie port indirect read and write on nv This patch is to add pcie port indirect read/write callback for nv series. They will be used for new asic. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4e532d6 |
|
27-Aug-2020 |
Thong Thai <thong.thai@amd.com> |
drm/amdgpu: enable vcn3.0 for van gogh Same as other VCN 3.0 asics. Signed-off-by: Thong Thai <thong.thai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88edbad6 |
|
12-Oct-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: set ip blocks for van gogh Enable ip blocks for van gogh. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fced3c3a |
|
28-Aug-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) Van gogh only has one sdma. v2: use num_instances rather than APU flag Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
026570e6 |
|
27-Aug-2020 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add nv common ip block support for van gogh This patch adds common ip support for van gogh. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
705a2b5b |
|
15-Sep-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to indirect reg access helper Switch WREG32/RREG32_PCIE to use indirect reg access helper for soc15 and onwards Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
78f0aef1 |
|
22-Sep-2020 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdgpu: fix hdp register access error mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1dd4aa6 |
|
23-Aug-2020 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Fix consecutive DPC recovery failures. Cache the PCI state on boot and before each case where we might loose it. v2: Add pci_restore_state while caching the PCI state to avoid breaking PCI core logic for stuff like suspend/resume. v3: Extract pci_restore_state from amdgpu_device_cache_pci_state to avoid superflous restores during GPU resets and suspend/resumes. v4: Style fixes. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
22dd44f4 |
|
25-Aug-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: use MODE1 reset for navy_flounder by default Switch default gpu reset method to MODE1 for navy_flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a7173731 |
|
19-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add pre_asic_init callback for navi Nothing to do for this family. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75947544 |
|
25-Aug-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: use MODE1 reset for navy_flounder by default Switch default gpu reset method to MODE1 for navy_flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11043b7a |
|
10-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: note what type of reset we are using When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f2e2573c |
|
06-Aug-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: use mode1 reset by default for sienna_cichlid Swith default gpu reset method for sienna_cichlid to MODE1 reset. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ca6fd7a6 |
|
06-Aug-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: use mode1 reset by default for sienna_cichlid Swith default gpu reset method for sienna_cichlid to MODE1 reset. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ebfbd1c2 |
|
21-Jul-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: expand sienna chichlid reg access support Added dedicated 64bit reg read/write support Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4922f1bc |
|
21-Jul-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: expand sienna chichlid reg access support Added dedicated 64bit reg read/write support Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c652923a |
|
17-Jul-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: enable xgmi support for sienna cichlid set xgmi support flag suring nv ip init sequence Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
85e7151b |
|
08-Jul-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: enable ih CG for navy_flounder Enable ih CG by setting the corresponding flag. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4759f887 |
|
08-Jul-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: enable hdp CG and LS for navy_flounder Enable hdp CG and LS by setting the corresponding flags. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
92c73756 |
|
08-Jul-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: enable mc CG and LS for navy_flounder Enable mc CG and LS by setting the corresponding flags. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
47fc894a |
|
08-Jul-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: enable athub/mmhub PG for navy_flounder Enable athub/mmhub PG by setting the corresponding flags. Actually the enablement is exercised by PMFW. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a6c5308f |
|
08-Jul-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: add DC support for navy flounder Plumb DC support for navy flounder through. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
40582e67 |
|
02-Jul-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: enable GFX clock gating for navy_flounder Enable GFX MGCG, CGCG and 3DCG for navy_flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
00740df9 |
|
01-Jul-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounder Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6e9dd0e |
|
01-Jul-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable VCN3.0 DPG for navy_flounder Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ebb06097 |
|
01-Jul-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
290b4ad5 |
|
08-Jul-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: add vcn ip block for navy_flounder Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7420eab2 |
|
08-Jul-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add psp block for navy_flounder Add psp and smu block for navy_flounder with psp firmware load type. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f4497d10 |
|
14-Apr-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add smu block for navy_flounder Add SMU block for navy_flounder with direct firmware load type. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5404f073 |
|
23-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add virtual display support for navy_flounder. Virtual display support for bring up and virtualization. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
df2d15df |
|
14-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add sdma ip block for navy_flounder Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
885eb3fa |
|
13-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add gfx ip block for navy_flounder since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
026c396b |
|
12-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add ih ip block for navy_flounder navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fc8f07da |
|
12-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add gmc ip block for navy_flounder navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8515e0a4 |
|
12-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: add common ip block for navy_flounder Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c8c959f6 |
|
10-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu: initialize IP offset for navy_flounder since navy_flounder has the same ip offset with sienna_cichlid, follow sienna_cichlid setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
543aa259 |
|
10-Feb-2020 |
Jiansong Chen <Jiansong.Chen@amd.com> |
drm/amdgpu/soc15: add support for navy_flounder Add soc support. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c45fbe1b |
|
23-Jun-2020 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amd/sriov skip jped ip block and close pgcg flags For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
273da6ff |
|
14-Jul-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: add module parameter choose reset mode Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
311531f0 |
|
13-Jul-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: enable mode1 reset For sienna cichlid, add mode1 reset path for sGPU. v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1 v3: split emergency restart logic to a new patch Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b0443b1 |
|
05-Jul-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: fix coding error of mmhub pg enablement MMHUB powergating should be disabled on navi12 and enabled on sienna cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1299461 |
|
22-Jun-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: request init data in virt detection Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks. Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
464ab91a |
|
20-May-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amdgpu: Enable DM block for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d00b0fa9 |
|
02-Apr-2020 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable DPG mode for VCN3.0 Enable DPG mode for VCN3.0 by updating related flag. V2: update description. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
846938c2 |
|
26-Mar-2020 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/powerplay: enable mmhub pg mmhub pg can be obvserved from PCTL_CTRL Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b794616d |
|
25-Mar-2020 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/powerplay: enable athub pg enable athub pg and the status can be checked in ATHUB_MISC_CNTL. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
38d5bbef |
|
17-Mar-2020 |
shaoyunl <shaoyun.liu@amd.com> |
drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOV SMU firmware already been loaded from host, don't enable it for now. May need to re-work it if we want to enable the SMU for guest in the future. Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
98f8ea29 |
|
18-Mar-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid. Enable mmhub clockgating. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bcc8367f |
|
27-Feb-2020 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: add athub ls support athub ls is bounded with hdp ls,verified. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3a32c25a |
|
27-Feb-2020 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: add IH cg support IH cg verified Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ca36461f |
|
27-Feb-2020 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: add HDP mgcg and ls support add HDP mgcg and ls support and verified Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
91c6adf8 |
|
27-Feb-2020 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: fix the HDP LS/DS/SD programming confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
00194def |
|
23-Jan-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: open GFX clock gating for sienna_cichlid Open GFX MGCG, CGCG and 3DCG for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4d72dd12 |
|
24-Mar-2020 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid By adding JPEG HW block to Sienna_Cichlid Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b467c4f5 |
|
03-Dec-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid By setting up the flags to the ASIC Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b8f10585 |
|
24-Mar-2020 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable VCN3.0 for Sienna_Cichlid By adding VCN HW block to Sienna_Cichlid Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e823be13 |
|
03-Dec-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid By setting up the flags to the ASIC Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a346ef86 |
|
24-Mar-2020 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add mes block to sienna_cichlid Add mes block support to sienna_cichlid. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
20519232 |
|
26-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: assign the doorbell index to mes ring MES ring will use the assigned doorbell index for command submission. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
56304e72 |
|
24-Mar-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add psp block load condition for sienna_cichlid Enable PSP block for firmware loading and other security setup only when amdgpu use PSP load type to load ucode. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5aa02350 |
|
24-Mar-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: enable psp ip block for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b07e5c60 |
|
24-Mar-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/powerplay: add smu block for sienna_cichlid Add SMU block for sienna_cichlid with psp load type. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9a986760 |
|
14-Aug-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add virtual display support for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
157e72e8 |
|
16-Jun-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add sdma ip block for sienna_cichlid (v5) Sienna_Cichlid have 4 sdma controllers. v2: add missing license to sdma_common.h (Alex) v3: rebase (Alex) v4: squash in policy fix (Alex) v4: squash in fw_name fix Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
933c8a93 |
|
01-May-2020 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add gfx ip block for sienna_cichlid (v3) Add support for GC 10.3. v2: Squash in gb_addr_config fix (Alex) v3: Add num_pkrs support (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
757b3af8 |
|
16-Jun-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add ih ip block for sienna_cichlid Update IH handling for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0b3df16b |
|
16-Jun-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add gmc ip block for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2e1ba10e |
|
17-Apr-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/soc15: add common ip block for sienna_cichlid Add common ip block for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dccdbf3f |
|
07-Nov-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: initialize IP offset for sienna_cichlid (v2) Add IP offset headers and state. V2: squash in updates (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
117910ed |
|
18-Mar-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/soc15: add support for sienna_cichlid Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3967ae6d |
|
28-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: enable init reset check gpu reset is implemented for navi so we can enable this. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
337b7244 |
|
28-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: remove some dead code navi never supported the pci config reset. Neither did vega. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
007026cd |
|
28-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: allow access to SDMA status registers For access via ioctl for tools like umr and mesa. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d3a37634 |
|
19-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop navi pcie bw callback It's not implemented yet so just drop it so the sysfs pcie bw file returns an appropriate error instead of garbage. Reviewed-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-By: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
79bebabb |
|
21-Apr-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: for nv12 always need smu ip because nv12 SRIOV support one vf mode Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
028cfb24 |
|
10-Apr-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix wrong vram lost counter increment V2 Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dadce777 |
|
10-Apr-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: fix wrong vram lost counter increment V2 Vram lost counter is wrongly increased by two during baco reset. V2: assumed vram lost for mode1 reset on all ASICs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
122078de |
|
04-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: equip new req_init_data handshake by this new handshake host side can prepare vbios/ip-discovery and pf&vf exchange data upon recieving this request without stopping world switch. this way the world switch is less impacted by VF's exclusive mode request Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3aa0115d |
|
03-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup all virtualization detection routine we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fe442491 |
|
05-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: disable jpeg block for SRIOV MMSCH doesn't support jpeg ring on SRIOV Signed-off-by: Jinage Zhao <jiange.zhao@amd.com> Singed-off-by: darlington Opara <darlington.opara@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a9d4fe2f |
|
20-Jan-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: remove unnecessary conversion to bool Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
df5e984c |
|
07-Jan-2020 |
Tiecheng Zhou <Tiecheng.Zhou@amd.com> |
drm/amdgpu/sriov: workaround on rev_id for Navi12 under sriov guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, as a consequence, the rev_id and external_rev_id are wrong. workaround it by hardcoding the rev_id to 0, which is the default value. v2. add comment in the code Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9530273e |
|
07-Jan-2020 |
Evan Quan <evan.quan@amd.com> |
drm/amd/powerplay: cover the powerplay implementation details V3 This can save users much troubles. As they do not actually need to care whether swSMU or traditional powerplay routine should be used. V2: apply the fixes to vi.c and cik.c also V3: squash in oops fix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f8a69a80 |
|
13-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: add asic func for fetching vbios from rom directly Needed as a fallback if the vbios can't be fetched by other means. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
11520f27 |
|
28-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: split swSMU baco_reset into enter and exit BACO - Bus Active, Chip Off So we can use it for power savings rather than just reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ac742616 |
|
07-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add supports_baco callback for NV asics. BACO - Bus Active, Chip Off Check the BACO capabilities from the powerplay table. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
29bc37b4 |
|
13-Nov-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nv: add asic func for fetching vbios from rom directly Needed as a fallback if the vbios can't be fetched by other means. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5be45a26 |
|
08-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir By adding JPEG IP block to the family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
099d66e4 |
|
11-Nov-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add PG and CG for JPEG2.0 And enable them for Navi1x and Renoir Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2af81531 |
|
05-Nov-2019 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdgpu: fix sysfs interface pcie_replay_count error on navi asic the asic callback function of get_pcie_replay_count is not implement on navi asic, it will cause null pinter error when read this interface. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4def374 |
|
28-Oct-2019 |
Jiange Zhao <Jiange.Zhao@amd.com> |
drm/amdgpu/SRIOV: SRIOV VF doesn't support BACO SRIOV VF doesn't support BACO. Only PF with BACO capability can do it. Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
664fe85a |
|
22-Oct-2019 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: Allow reading more status registers on si/cik Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2c9a0c66 |
|
01-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't increment vram lost if we are in hibernation We reset the GPU as part of our hibernation sequence so we need to make sure we don't mark vram as lost in that case. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
923c087a |
|
27-Sep-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
drm/amdgpu: Add the HDP flush support for Navi The HDP flush support code was missing in the nbio and nv files. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
49379032 |
|
01-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: don't increment vram lost if we are in hibernation We reset the GPU as part of our hibernation sequence so we need to make sure we don't mark vram as lost in that case. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a4ac7693 |
|
11-Sep-2019 |
Jiange Zhao <Jiange.Zhao@amd.com> |
drm/amdgpu/SRIOV: Navi10/12 VF doesn't support SMU In SRIOV case, SMU and powerplay are handled in HV. VF shouldn't have control over SMU and powerplay. Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b05b6903 |
|
11-Sep-2019 |
Jiange Zhao <Jiange.Zhao@amd.com> |
drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions Mailbox functions and interrupts are only for Navi12 VF. Register functions and irqs during initialization. Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bebc0762 |
|
23-Aug-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: switch to new amdgpu_nbio structure no functional change, just switch to new structures Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
20c14ee1 |
|
30-Aug-2019 |
Petr Cvek <petrcvekcz@gmail.com> |
drm/amdgpu: Fix undefined dm_ip_block for navi12 There is missing "if defined" CONFIG_DRM_AMD_DC block for non DC configurations. This will cause link error. The patch is fixing that. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110979 Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3526257 |
|
27-Aug-2019 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: introduce vram lost for reset (v2) for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5ef3b8ac |
|
26-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable athub powergating for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c1653ea0 |
|
26-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable vcn powergating for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6892c1f8 |
|
27-Jun-2019 |
YueHaibing <yuehaibing@huawei.com> |
drm/amdgpu: remove set but not used variable 'psp_enabled' Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init': drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning: variable 'psp_enabled' set but not used [-Wunused-but-set-variable] It's not used since inroduction in commit c6b6a42175f5 ("drm/amdgpu: add navi10 common ip block (v3)") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6da6c279 |
|
20-Aug-2019 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: disable MMHUB PG for navi10 Disable MMHUB PG for navi10 according to the production requirement. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
221a2bdb |
|
20-Aug-2019 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/amdgpu: disable MMHUB PG for navi10 Disable MMHUB PG for navi10 according to the production requirement. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
65872e59 |
|
01-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable vcn clock gating for navi12 enables vcn medium grained clock gating Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ca51678d |
|
01-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable athub clock gating for navi12 enables athub medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fbe0bc57 |
|
01-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable ih clock gating for navi12 enables ih clock gating Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8b797b3d |
|
01-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable mmhub clock gating for navi12 enables mmhub medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
358ab97f |
|
29-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable sdma clock gating for navi12 enables sdma medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5211c37a |
|
01-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable hdp clock gating for navi12 enables hdp medium grained clock gating and memory light sleep Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
dca009e7 |
|
29-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable gfx clock gatings for navi12 enables following gfx clock gating features: - medium grained clock gating - medium grained light sleep - coarse grained clock gating - cp memory light sleep - rlc memory light sleep CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b5c73856 |
|
05-Aug-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init() move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a common function nv_reg_base_init(). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
35ef88fa |
|
05-Aug-2019 |
tiancyin <tianci.yin@amd.com> |
drm/amdgpu/soc15: fix external_rev_id for navi14 fix the hard code external_rev_id. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
078655d9 |
|
16-Jul-2019 |
Leo Li <sunpeng.li@amd.com> |
drm/amdgpu: Add nv12 DC ip block Load DC and amdgpu display manager Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
400e9c5e |
|
18-Jul-2019 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: enable DPG mode for Navi12 Enable Dynamic Power Gating VCN for Navi12. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1fbed280 |
|
18-Jul-2019 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu: add VCN ip block for Navi12 Add VCN2 ip block for Navi12 Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6b66ae2e |
|
17-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: add psp ip block for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7f47efeb |
|
15-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: add smu ip block for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
79902029 |
|
26-Jun-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable virtual display for navi12 Virtual display is a sw display interface for bring up and virtualization or for cards without display hardware. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
44e9e7c9 |
|
16-May-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: add ip blocks for navi12 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e17e58b |
|
16-May-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: set nbio/hdp cg for navi12 Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
74b5e509 |
|
16-May-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: initialize cg/pg flags and external rev id for navi12 don't enable any cg/pg features yet. v2: calculate external revision id from revision id so that we can differentiate navi12 A0 from A1 directly. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
03d0a073 |
|
14-May-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: initialize reg base for navi12 Set up the register offset map for navi12. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e9eea902 |
|
31-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop drmP.h from nv.c And fix up the fallout. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2ddc6c3e |
|
23-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add reset_method asic callback for navi Navi uses either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d1daf850 |
|
02-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: consolidate navi14 IP init It's the same as navi10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0377b088 |
|
01-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/vcn: enable indirect DPG SRAM mode for navi14 Enable VCN dynamic powergating for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
03917df7 |
|
01-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/nv: set vcn pg flag for navi14 Enable VCN power gating by default. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d0c39f8c |
|
20-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable clock gatings for navi14 Set appropriate CG flags for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e149a2f6 |
|
01-Mar-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: Enable VCN on navi14 Add navi14 vcn firmware, and enable VCN on navi14. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8fceceb6 |
|
26-Feb-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: add dm block enable DC for navi14. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ab5e5121 |
|
12-Feb-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable sw smu ip for navi14 same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4adc0732 |
|
10-Feb-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable psp ip block for navi14 Same as navi10. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Snow Zhang <Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
691f69b6 |
|
15-Jan-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: enable virtual display for navi14 Virtual display is a sw based kms interface for virtualization and emulation. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a29bfd12 |
|
19-Dec-2018 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: add ip blocks for navi14 Add the initial IP blocks for navi14 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5e71e011 |
|
17-Dec-2018 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/soc15: add support for navi14 same as navi10 Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a0f6d926 |
|
17-Dec-2018 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/soc15: initialize reg base for navi14 (v2) Initialize the IP register base offsets for navi14. v2: squash in MP, CLK, THM updates Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b5203d16 |
|
12-Jul-2019 |
Arnd Bergmann <arnd@arndb.de> |
drm/amd/amdgpu: hide #warning for missing DC config It is annoying to have #warnings that trigger in randconfig builds like drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15." drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi." Remove these and rely on the users to turn these on. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f8a7976b |
|
05-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: properly guard DC support in navi code Need to add appropriate ifdef. Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3e2bb60a |
|
04-Jul-2019 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdgpu: add mode1 (psp) reset for navi asic add mode1 (by psp) reset for navi asic. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
767acabd |
|
05-Jul-2019 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/powerplay: add baco smu reset function for smu11 add baco reset support for smu11. it can help gpu do asic reset when gpu recovery. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a201b6ac |
|
14-Jun-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amd/powerplay: make athub pg bit configured by pg_flags The athub pg features enabling should be indicated by pg_flags. Reported-by: Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c12d410f |
|
14-Jun-2019 |
Huang Rui <ray.huang@amd.com> |
drm/amd/powerplay: make mmhub pg bit configured by pg_flags The mmhub pg features enabling should be indicated by pg_flags. Reported-by: Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4f199c7 |
|
26-Feb-2019 |
Harry Wentland <harry.wentland@amd.com> |
drm/amdgpu: Enable DC support for Navi10 Enable the IP for navi10. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
157710ea |
|
15-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: enable VCN2.0 DPG mode It will be the default for VCN2.x family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
462a70d8 |
|
13-May-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: correct reference clock value on navi10 remove the divisor 4 Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6ff68731 |
|
18-Apr-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu/nv: set vcn pg flag Enable VCN power gating by default. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
36f87f0a |
|
11-Apr-2019 |
Tianci Yin <tianci.yin@amd.com> |
drm/amdgpu: disable some gfx light sleep temporarily disable to avoid s3 test failure. s3 test failure log: "[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=8278, emitted seq=8281" Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Tianci Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c6b6a421 |
|
03-Mar-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add navi10 common ip block (v3) This adds the core SOC code for navi asics. v1: add place holder and initial basic function (Ray) v2: add new introduced functions to avoid reference NULL pointer (Hawking) v3L squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|