/linux-master/drivers/clocksource/ |
H A D | timer-qcom.c | 34 static void __iomem *event_base; variable 42 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 44 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 56 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 58 writel_relaxed(ctrl, event_base + TIMER_CLEAR); 59 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); 65 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); 73 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 75 writel_relaxed(ctrl, event_base [all...] |
/linux-master/arch/x86/events/ |
H A D | msr.c | 223 event->hw.event_base = msr[cfg].msr; 233 if (event->hw.event_base) 234 rdmsrl(event->hw.event_base, now); 253 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { 256 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
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H A D | rapl.c | 157 rdmsrl(event->hw.event_base, raw); 185 rdmsrl(event->hw.event_base, new_raw_count); 365 event->hw.event_base = rapl_msrs[bit].msr;
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H A D | core.c | 122 if (unlikely(!hwc->event_base)) 1228 hwc->event_base = 0; 1237 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + 1245 hwc->event_base = x86_pmu_event_addr(hwc->idx); 1372 if (unlikely(!hwc->event_base)) 1410 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
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/linux-master/arch/s390/include/asm/ |
H A D | pai.h | 84 #define PAI_SAVE_AREA(x) ((x)->hw.event_base)
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H A D | perf_event.h | 70 #define SAMPL_RATE(hwc) ((hwc)->event_base)
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/linux-master/drivers/perf/ |
H A D | thunderx2_pmu.c | 334 hwc->event_base = (unsigned long)tx2_pmu->base 350 hwc->event_base = (unsigned long)tx2_pmu->base 364 hwc->event_base = (unsigned long)tx2_pmu->base; 380 reg_writel(0, hwc->event_base); 410 reg_writel(0, hwc->event_base); 451 hwc->event_base + CCPI2_PERF_CTL); 460 reg_writel(0, hwc->event_base + CCPI2_PERF_CTL); 480 hwc->event_base + CCPI2_COUNTER_SEL); 481 new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_H); 483 reg_readl(hwc->event_base [all...] |
H A D | riscv_pmu_sbi.c | 399 cmask, cflags, hwc->event_base, hwc->config, 403 cmask, cflags, hwc->event_base, hwc->config, 0); 407 hwc->event_base, hwc->config);
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H A D | riscv_pmu.c | 334 hwc->event_base = mapped_event;
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H A D | arm-ccn.c | 893 dt_cfg = hw->event_base; 947 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); 990 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); 1013 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
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H A D | cxl_pmu.c | 650 hwc->event_base); 743 hwc->event_base = event_idx;
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/linux-master/arch/alpha/kernel/ |
H A D | perf_event.c | 351 evtype[n] = group->hw.event_base; 359 evtype[n] = pe->hw.event_base; 459 cpuc->evtype[n0] = event->hw.event_base; 634 * We place the event type in event_base here and leave calculation 642 hwc->event_base = ev; 656 evtypes[n] = hwc->event_base;
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/linux-master/arch/x86/events/intel/ |
H A D | cstate.c | 333 event->hw.event_base = core_msr[cfg].msr; 345 event->hw.event_base = pkg_msr[cfg].msr; 354 event->hw.event_base = module_msr[cfg].msr; 374 rdmsrl(event->hw.event_base, val);
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H A D | uncore.c | 153 rdmsrl(event->hw.event_base, count); 170 if (!uncore_mmio_is_valid_offset(box, event->hw.event_base)) 173 return readq(box->io_addr + event->hw.event_base); 262 hwc->event_base = uncore_fixed_ctr(box); 268 hwc->event_base = uncore_perf_ctr(box, hwc->idx); 795 event->hw.event_base = uncore_freerunning_counter(box, event);
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H A D | uncore_discovery.c | 459 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); 460 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
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H A D | p4.c | 874 rdmsrl(hwc->event_base, v); 1017 if (hwc->event_base) { 1026 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
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/linux-master/arch/loongarch/kernel/ |
H A D | perf_event.c | 274 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base) | 548 event->hw.event_base = 0xffffffff; 772 hwc->event_base = loongarch_pmu_perf_event_encode(pev);
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/linux-master/drivers/fpga/ |
H A D | dfl-fme-perf.c | 788 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); 826 hwc->event_base = evtype; 844 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); 858 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base);
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/linux-master/arch/x86/events/amd/ |
H A D | uncore.c | 109 rdmsrl(hwc->event_base, new); 124 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); 176 hwc->event_base = pmu->msr_base + 1 + (2 * hwc->idx); 876 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));
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/linux-master/drivers/perf/hisilicon/ |
H A D | hisi_pcie_pmu.c | 375 hwc->event_base = HISI_PCIE_EXT_CNT; 377 hwc->event_base = HISI_PCIE_CNT; 399 return hisi_pcie_pmu_readq(pcie_pmu, event->hw.event_base, idx); 521 hisi_pcie_pmu_writeq(pcie_pmu, hwc->event_base, idx, prev_cnt);
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/linux-master/arch/mips/kernel/ |
H A D | perf_event_mipsxx.c | 325 cntr_mask = (hwc->event_base >> 10) & 0xffff; 327 cntr_mask = (hwc->event_base >> 8) & 0xffff; 352 unsigned int range = evt->event_base >> 24; 357 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0x3ff) | 362 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | 440 M_PERFCTL_EVENT(hwc->event_base & 0x3ff)); 1506 hwc->event_base = mipspmu_perf_event_encode(pev);
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/linux-master/arch/sparc/kernel/ |
H A D | perf_event.c | 1356 events[n] = group->hw.event_base; 1365 events[n] = event->hw.event_base; 1385 cpuc->events[n0] = event->hw.event_base; 1455 hwc->event_base = perf_event_encode(pmap); 1461 hwc->event_base = attr->config; 1481 events[n] = hwc->event_base;
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/linux-master/drivers/dma/idxd/ |
H A D | perfmon.c | 131 hwc->event_base = ioread64(CNTRCFG_REG(idxd, idx)); 219 event->hw.event_base = ioread64(PERFMON_TABLE_OFFSET(idxd));
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/linux-master/arch/powerpc/perf/ |
H A D | imc-pmu.c | 562 event->hw.event_base = (u64)pcni->vbase + l_config; 894 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); 1043 return (__be64 *)event->hw.event_base;
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H A D | core-book3s.c | 1604 flags[n] = group->hw.event_base; 1613 flags[n] = event->hw.event_base; 1646 cpuhw->flags[n0] = event->hw.event_base; 2166 event->hw.event_base = cflags[n];
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