Searched refs:qnum (Results 1 - 21 of 21) sorted by last modified time

/haiku/src/add-ons/kernel/drivers/network/wlan/marvell88w8363/dev/mwl/
H A Dif_mwl.c247 static void mwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix);
1285 "%s: out of xmit buffers on q %d\n", __func__, txq->qnum);
1372 "%s: tail drop on q %d\n", __func__, txq->qnum);
2830 mwl_txq_init(struct mwl_softc *sc, struct mwl_txq *txq, int qnum) argument
2836 txq->qnum = qnum;
2903 if (mwl_hal_setedcaparams(mh, txq->qnum, cwmin, cwmax, aifs, txoplim)) {
3265 ds->TxPriority = txq->qnum;
3283 ds->TxPriority = txq->qnum;
3285 ds->TxPriority = txq->qnum;
4503 mwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix) argument
[all...]
H A Dmwlhal.h159 mwl_hal_txstart(struct mwl_hal *mh, int qnum) argument
609 int mwl_hal_setedcaparams(struct mwl_hal *mh, uint8_t qnum,
H A Dmwlhal.c525 mwl_hal_txstart(struct mwl_hal *mh0, int qnum)
1856 mwl_hal_setedcaparams(struct mwl_hal *mh0, uint8_t qnum, argument
1876 pCmd->TxQNum = qnum; /* XXX check */
H A Dif_mwlvar.h126 int qnum; /* f/w q number */ member in struct:mwl_txq
135 device_get_nameunit((_sc)->sc_dev), (_tq)->qnum); \
/haiku/src/add-ons/kernel/drivers/network/wlan/marvell88w8335/dev/malo/
H A Dif_malo.c744 malo_txq_init(struct malo_softc *sc, struct malo_txq *txq, int qnum) argument
750 txq->qnum = qnum;
792 "%s: out of xmit buffers on q %d\n", __func__, txq->qnum);
874 malo_printtxbuf(const struct malo_txbuf *bf, u_int qnum, u_int ix) argument
879 printf("Q%u[%3u]", qnum, ix);
934 __func__, txq->qnum);
954 malo_printtxbuf(bf, txq->qnum, nreaped);
1176 ds->txpriority = txq->qnum;
1599 malo_printtxbuf(bf, txq->qnum, i
[all...]
H A Dif_malohal.c750 malo_hal_txstart(struct malo_hal *mh, int qnum) argument
H A Dif_malo.h489 int qnum; /* f/w q number */ member in struct:malo_txq
498 device_get_nameunit((_sc)->malo_dev), (_tq)->qnum); \
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/
H A Dif_ath_tx_edma.c627 "%s: called; bf=%p, txq=%p, qnum=%d\n",
640 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum) argument
642 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
662 ath_edma_free_txfifo(struct ath_softc *sc, int qnum) argument
664 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
H A Dif_ath.c3951 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) argument
3953 txq->axq_qnum = qnum;
3974 int qnum; local
4000 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4001 if (qnum == -1) {
4008 if (qnum >= nitems(sc->sc_txq)) {
4010 "hal qnum %u out of range, max %zu!\n",
4011 qnum, nitems(sc->sc_txq));
4012 ath_hal_releasetxqueue(ah, qnum);
4015 if (!ATH_TXQ_SETUP(sc, qnum)) {
[all...]
H A Dif_ath_debug.h111 u_int qnum, u_int ix, int done);
113 const uint32_t *ds, u_int qnum, u_int ix, int done);
H A Dif_ath_debug.c138 u_int qnum, u_int ix, int done)
147 printf("Q%u[%3u] (nseg=%d)", qnum, ix, bf->bf_nseg);
201 u_int qnum, u_int ix, int done)
209 printf("Q%u[%3u]", qnum, ix);
244 u_int qnum, u_int ix, int done)
247 ath_printtxbuf_edma(sc, first_bf, qnum, ix, done);
249 ath_printtxbuf_legacy(sc, first_bf, qnum, ix, done);
254 const uint32_t *ds, u_int qnum, u_int ix, int done)
257 printf("Q%u[%3u] ", qnum, ix);
137 ath_printtxbuf_edma(struct ath_softc *sc, const struct ath_buf *first_bf, u_int qnum, u_int ix, int done) argument
200 ath_printtxbuf_legacy(struct ath_softc *sc, const struct ath_buf *first_bf, u_int qnum, u_int ix, int done) argument
243 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *first_bf, u_int qnum, u_int ix, int done) argument
253 ath_printtxstatbuf(struct ath_softc *sc, const struct ath_buf *first_bf, const uint32_t *ds, u_int qnum, u_int ix, int done) argument
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/
H A Dar5416_reset.c495 uint32_t data, synthDelay, qnum;
506 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
507 if (ar5212NumTxPending(ah, qnum)) {
509 "%s: frames pending on queue %d\n", __func__, qnum);
H A Dar5416.h208 extern void ar5416BTCoexSetQcuThresh(struct ath_hal *ah, int qnum);
H A Dar5416_btcoex.c87 ar5416BTCoexSetQcuThresh(struct ath_hal *ah, int qnum) argument
91 ahp->ah_btCoexMode |= SM(qnum, AR_BT_QCU_THRESH);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/
H A Dar5212_reset.c734 uint32_t data, synthDelay, qnum; local
745 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
746 if (ar5212NumTxPending(ah, qnum)) {
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/
H A Dar5211.h187 extern uint32_t ar5211NumTxPending(struct ath_hal *, u_int qnum);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_reset.c1261 u_int32_t synth_delay, qnum; local
1265 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1266 if (ar9300_num_tx_pending(ah, qnum)) {
1268 "%s: Transmit frames pending on queue %d\n", __func__, qnum);
H A Dar9300.h1537 extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum);
H A Dar9300_xmit_ds.c444 static int qnum = 0;
472 if (mode == 8) { /* set TXE for qnum */
473 OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum);
483 qnum = (int) ds;
501 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
502 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
509 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
510 /* enable prefetch on qnum */
511 OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum);
515 OS_REG_WRITE(ah, AR_QMISC(qnum), /* se
[all...]
H A Dar9300_misc.c2416 ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) argument
2422 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
3829 u_int32_t qnum = (u_int32_t)data; local
3837 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
3842 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
3845 val = OS_REG_READ(ah, AR_QMISC(qnum));
3846 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
H A Dar9300_tx99_tgt.c498 a_uint32_t qnum = (a_uint32_t)data; local
508 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
512 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
515 val = OS_REG_READ(ah, AR_QMISC(qnum));
516 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);

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