1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007 Marvell Semiconductor, Inc. 5 * Copyright (c) 2007 Sam Leffler, Errno Consulting 6 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 17 * redistribution must be conditioned upon including a substantially 18 * similar Disclaimer requirement for further binary redistribution. 19 * 20 * NO WARRANTY 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGES. 32 */ 33 34#include <sys/cdefs.h> 35#ifdef __FreeBSD__ 36__FBSDID("$FreeBSD: releng/12.0/sys/dev/malo/if_malohal.c 326255 2017-11-27 14:52:40Z pfg $"); 37#endif 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/endian.h> 42#include <sys/kernel.h> 43#include <sys/malloc.h> 44#include <sys/firmware.h> 45#include <sys/socket.h> 46 47#include <machine/bus.h> 48#include <sys/bus.h> 49 50#include <net/if.h> 51#include <net/if_var.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/ethernet.h> 55 56#include <net80211/ieee80211_var.h> 57 58#include <dev/malo/if_malo.h> 59 60#define MALO_WAITOK 1 61#define MALO_NOWAIT 0 62 63#define _CMD_SETUP(pCmd, _type, _cmd) do { \ 64 pCmd = (_type *)&mh->mh_cmdbuf[0]; \ 65 memset(pCmd, 0, sizeof(_type)); \ 66 pCmd->cmdhdr.cmd = htole16(_cmd); \ 67 pCmd->cmdhdr.length = htole16(sizeof(_type)); \ 68} while (0) 69 70static __inline uint32_t 71malo_hal_read4(struct malo_hal *mh, bus_size_t off) 72{ 73 return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off); 74} 75 76static __inline void 77malo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val) 78{ 79 bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val); 80} 81 82static void 83malo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 84{ 85 bus_addr_t *paddr = (bus_addr_t*) arg; 86 87 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 88 *paddr = segs->ds_addr; 89} 90 91/* 92 * Setup for communication with the device. We allocate 93 * a command buffer and map it for bus dma use. The pci 94 * device id is used to identify whether the device has 95 * SRAM on it (in which case f/w download must include a 96 * memory controller reset). All bus i/o operations happen 97 * in BAR 1; the driver passes in the tag and handle we need. 98 */ 99struct malo_hal * 100malo_hal_attach(device_t dev, uint16_t devid, 101 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag) 102{ 103 int error; 104 struct malo_hal *mh; 105 106 mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO); 107 if (mh == NULL) 108 return NULL; 109 110 mh->mh_dev = dev; 111 mh->mh_ioh = ioh; 112 mh->mh_iot = iot; 113 114 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname), 115 "%s_hal", device_get_nameunit(dev)); 116 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF); 117 118 /* 119 * Allocate the command buffer and map into the address 120 * space of the h/w. We request "coherent" memory which 121 * will be uncached on some architectures. 122 */ 123 error = bus_dma_tag_create(tag, /* parent */ 124 PAGE_SIZE, 0, /* alignment, bounds */ 125 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 126 BUS_SPACE_MAXADDR, /* highaddr */ 127 NULL, NULL, /* filter, filterarg */ 128 MALO_CMDBUF_SIZE, /* maxsize */ 129 1, /* nsegments */ 130 MALO_CMDBUF_SIZE, /* maxsegsize */ 131 BUS_DMA_ALLOCNOW, /* flags */ 132 NULL, /* lockfunc */ 133 NULL, /* lockarg */ 134 &mh->mh_dmat); 135 if (error != 0) { 136 device_printf(dev, "unable to allocate memory for cmd tag, " 137 "error %u\n", error); 138 goto fail; 139 } 140 141 /* allocate descriptors */ 142 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf, 143 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 144 &mh->mh_dmamap); 145 if (error != 0) { 146 device_printf(dev, "unable to allocate memory for cmd buffer, " 147 "error %u\n", error); 148 goto fail; 149 } 150 151 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap, 152 mh->mh_cmdbuf, MALO_CMDBUF_SIZE, 153 malo_hal_load_cb, &mh->mh_cmdaddr, 154 BUS_DMA_NOWAIT); 155 if (error != 0) { 156 device_printf(dev, "unable to load cmd buffer, error %u\n", 157 error); 158 goto fail; 159 } 160 161 return (mh); 162 163fail: 164 if (mh->mh_cmdbuf != NULL) 165 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, 166 mh->mh_dmamap); 167 if (mh->mh_dmat) 168 bus_dma_tag_destroy(mh->mh_dmat); 169 free(mh, M_DEVBUF); 170 171 return (NULL); 172} 173 174/* 175 * Low level firmware cmd block handshake support. 176 */ 177 178static void 179malo_hal_send_cmd(struct malo_hal *mh) 180{ 181 uint32_t dummy; 182 183 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 185 186 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 187 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 188 189 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 190 MALO_H2ARIC_BIT_DOOR_BELL); 191} 192 193static int 194malo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd) 195{ 196#define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000 197 int i; 198 199 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) { 200 if (mh->mh_cmdbuf[0] == le16toh(cmd)) 201 return 1; 202 203 DELAY(1 * 1000); 204 } 205 206 return 0; 207#undef MAX_WAIT_FW_COMPLETE_ITERATIONS 208} 209 210static int 211malo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd) 212{ 213 MALO_HAL_LOCK_ASSERT(mh); 214 215 if ((mh->mh_flags & MHF_FWHANG) && 216 (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) { 217 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n", 218 cmd); 219 return ENXIO; 220 } 221 222 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 223 device_printf(mh->mh_dev, "%s: device not present!\n", 224 __func__); 225 return EIO; 226 } 227 228 malo_hal_send_cmd(mh); 229 if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) { 230 device_printf(mh->mh_dev, 231 "timeout waiting for f/w cmd 0x%x\n", cmd); 232 mh->mh_flags |= MHF_FWHANG; 233 return ETIMEDOUT; 234 } 235 236 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, 237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 238 239 return 0; 240} 241 242static int 243malo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index) 244{ 245 struct malo_cmd_caltable *cmd; 246 int ret; 247 248 MALO_HAL_LOCK_ASSERT(mh); 249 250 _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE); 251 cmd->annex = annex; 252 cmd->index = index; 253 254 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE); 255 if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255) 256 ret = EIO; 257 return ret; 258} 259 260static int 261malo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal) 262{ 263 const uint8_t *data; 264 int len; 265 266 MALO_HAL_LOCK(mh); 267 /* NB: we hold the lock so it's ok to use cmdbuf */ 268 data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl; 269 if (malo_hal_get_cal_table(mh, 33, 0) == 0) { 270 len = (data[2] | (data[3] << 8)) - 12; 271 /* XXX validate len */ 272 memcpy(cal->pt_ratetable_20m, &data[12], len); 273 } 274 mh->mh_flags |= MHF_CALDATA; 275 MALO_HAL_UNLOCK(mh); 276 277 return 0; 278} 279 280/* 281 * Reset internal state after a firmware download. 282 */ 283static int 284malo_hal_resetstate(struct malo_hal *mh) 285{ 286 /* 287 * Fetch cal data for later use. 288 * XXX may want to fetch other stuff too. 289 */ 290 if ((mh->mh_flags & MHF_CALDATA) == 0) 291 malo_hal_get_pwrcal_table(mh, &mh->mh_caldata); 292 return 0; 293} 294 295static void 296malo_hal_fw_reset(struct malo_hal *mh) 297{ 298 299 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) { 300 device_printf(mh->mh_dev, "%s: device not present!\n", 301 __func__); 302 return; 303 } 304 305 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET); 306 mh->mh_flags &= ~MHF_FWHANG; 307} 308 309static void 310malo_hal_trigger_pcicmd(struct malo_hal *mh) 311{ 312 uint32_t dummy; 313 314 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE); 315 316 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr); 317 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 318 319 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 320 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 321 322 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, 323 MALO_H2ARIC_BIT_DOOR_BELL); 324 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE); 325} 326 327static int 328malo_hal_waitfor(struct malo_hal *mh, uint32_t val) 329{ 330 int i; 331 332 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 333 DELAY(MALO_FW_CHECK_USECS); 334 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val) 335 return 0; 336 } 337 338 return -1; 339} 340 341/* 342 * Firmware block xmit when talking to the boot-rom. 343 */ 344static int 345malo_hal_send_helper(struct malo_hal *mh, int bsize, 346 const void *data, size_t dsize, int waitfor) 347{ 348 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 349 mh->mh_cmdbuf[1] = htole16(bsize); 350 if (data != NULL) 351 memcpy(&mh->mh_cmdbuf[4], data , dsize); 352 353 malo_hal_trigger_pcicmd(mh); 354 355 if (waitfor == MALO_NOWAIT) 356 goto pass; 357 358 /* XXX 2000 vs 200 */ 359 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 360 device_printf(mh->mh_dev, 361 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 362 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 363 364 return ETIMEDOUT; 365 } 366 367pass: 368 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 369 370 return (0); 371} 372 373static int 374malo_hal_fwload_helper(struct malo_hal *mh, char *helper) 375{ 376 const struct firmware *fw; 377 int error; 378 379 fw = firmware_get(helper); 380 if (fw == NULL) { 381 device_printf(mh->mh_dev, "could not read microcode %s!\n", 382 helper); 383 return (EIO); 384 } 385 386 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 387 helper, fw->datasize); 388 389 error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize, 390 MALO_WAITOK); 391 if (error != 0) 392 goto fail; 393 394 /* tell the card we're done and... */ 395 error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT); 396 397fail: 398 firmware_put(fw, FIRMWARE_UNLOAD); 399 400 return (error); 401} 402 403/* 404 * Firmware block xmit when talking to the 1st-stage loader. 405 */ 406static int 407malo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize, 408 uint16_t seqnum, int waitfor) 409{ 410 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD); 411 mh->mh_cmdbuf[1] = htole16(dsize); 412 mh->mh_cmdbuf[2] = htole16(seqnum); 413 mh->mh_cmdbuf[3] = 0; 414 if (data != NULL) 415 memcpy(&mh->mh_cmdbuf[4], data, dsize); 416 417 malo_hal_trigger_pcicmd(mh); 418 419 if (waitfor == MALO_NOWAIT) 420 goto pass; 421 422 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) { 423 device_printf(mh->mh_dev, 424 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n", 425 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE)); 426 427 return ETIMEDOUT; 428 } 429 430pass: 431 malo_hal_write4(mh, MALO_REG_INT_CODE, 0); 432 433 return 0; 434} 435 436static int 437malo_hal_fwload_main(struct malo_hal *mh, char *firmware) 438{ 439 const struct firmware *fw; 440 const uint8_t *fp; 441 int error; 442 size_t count; 443 uint16_t seqnum; 444 uint32_t blocksize; 445 446 error = 0; 447 448 fw = firmware_get(firmware); 449 if (fw == NULL) { 450 device_printf(mh->mh_dev, "could not read firmware %s!\n", 451 firmware); 452 return (EIO); 453 } 454 455 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n", 456 firmware, fw->datasize); 457 458 seqnum = 1; 459 for (count = 0; count < fw->datasize; count += blocksize) { 460 blocksize = MIN(256, fw->datasize - count); 461 fp = (const uint8_t *)fw->data + count; 462 463 error = malo_hal_send_main(mh, fp, blocksize, seqnum++, 464 MALO_NOWAIT); 465 if (error != 0) 466 goto fail; 467 DELAY(500); 468 } 469 470 /* 471 * send a command with size 0 to tell that the firmware has been 472 * uploaded 473 */ 474 error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT); 475 DELAY(100); 476 477fail: 478 firmware_put(fw, FIRMWARE_UNLOAD); 479 480 return (error); 481} 482 483int 484malo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware) 485{ 486 int error, i; 487 uint32_t fwreadysig, opmode; 488 489 /* 490 * NB: now malo(4) supports only STA mode. It will be better if it 491 * supports AP mode. 492 */ 493 fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE; 494 opmode = MALO_HOSTCMD_STA_MODE; 495 496 malo_hal_fw_reset(mh); 497 498 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL, 499 MALO_A2HRIC_BIT_MASK); 500 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00); 501 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00); 502 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK, 503 MALO_A2HRIC_BIT_MASK); 504 505 error = malo_hal_fwload_helper(mh, helper); 506 if (error != 0) { 507 device_printf(mh->mh_dev, "failed to load bootrom loader.\n"); 508 goto fail; 509 } 510 511 DELAY(200 * MALO_FW_CHECK_USECS); 512 513 error = malo_hal_fwload_main(mh, firmware); 514 if (error != 0) { 515 device_printf(mh->mh_dev, "failed to load firmware.\n"); 516 goto fail; 517 } 518 519 /* 520 * Wait for firmware to startup; we monitor the INT_CODE register 521 * waiting for a signature to written back indicating it's ready to go. 522 */ 523 mh->mh_cmdbuf[1] = 0; 524 525 if (opmode != MALO_HOSTCMD_STA_MODE) 526 malo_hal_trigger_pcicmd(mh); 527 528 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) { 529 malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode); 530 DELAY(MALO_FW_CHECK_USECS); 531 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) { 532 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00); 533 return malo_hal_resetstate(mh); 534 } 535 } 536 537 return ETIMEDOUT; 538fail: 539 malo_hal_fw_reset(mh); 540 541 return (error); 542} 543 544/* 545 * Return "hw specs". Note this must be the first cmd MUST be done after 546 * a firmware download or the f/w will lockup. 547 */ 548int 549malo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw) 550{ 551 struct malo_cmd_get_hwspec *cmd; 552 int ret; 553 554 MALO_HAL_LOCK(mh); 555 556 _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC); 557 memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN); 558 cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048); 559 560 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC); 561 if (ret == 0) { 562 IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr); 563 hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff; 564 hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff; 565 hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff; 566 hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff; 567 hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff; 568 hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff; 569 hw->regioncode = le16toh(cmd->regioncode) & 0x00ff; 570 hw->fw_releasenum = le32toh(cmd->fw_releasenum); 571 hw->maxnum_wcb = le16toh(cmd->num_wcb); 572 hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr); 573 hw->num_antenna = le16toh(cmd->num_antenna); 574 hw->hwversion = cmd->version; 575 hw->hostinterface = cmd->hostif; 576 } 577 578 MALO_HAL_UNLOCK(mh); 579 580 return ret; 581} 582 583void 584malo_hal_detach(struct malo_hal *mh) 585{ 586 587 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap); 588 bus_dma_tag_destroy(mh->mh_dmat); 589 mtx_destroy(&mh->mh_mtx); 590 free(mh, M_DEVBUF); 591} 592 593/* 594 * Configure antenna use. Takes effect immediately. 595 * 596 * XXX tx antenna setting ignored 597 * XXX rx antenna setting should always be 3 (for now) 598 */ 599int 600malo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant) 601{ 602 struct malo_cmd_rf_antenna *cmd; 603 int ret; 604 605 if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX)) 606 return EINVAL; 607 608 MALO_HAL_LOCK(mh); 609 610 _CMD_SETUP(cmd, struct malo_cmd_rf_antenna, 611 MALO_HOSTCMD_802_11_RF_ANTENNA); 612 cmd->action = htole16(dirset); 613 if (ant == 0) { /* default to all/both antennae */ 614 /* XXX never reach now. */ 615 ant = 3; 616 } 617 cmd->mode = htole16(ant); 618 619 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA); 620 621 MALO_HAL_UNLOCK(mh); 622 623 return ret; 624} 625 626/* 627 * Configure radio. Takes effect immediately. 628 * 629 * XXX preamble installed after set fixed rate cmd 630 */ 631int 632malo_hal_setradio(struct malo_hal *mh, int onoff, 633 enum malo_hal_preamble preamble) 634{ 635 struct malo_cmd_radio_control *cmd; 636 int ret; 637 638 MALO_HAL_LOCK(mh); 639 640 _CMD_SETUP(cmd, struct malo_cmd_radio_control, 641 MALO_HOSTCMD_802_11_RADIO_CONTROL); 642 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 643 if (onoff == 0) 644 cmd->control = 0; 645 else 646 cmd->control = htole16(preamble); 647 cmd->radio_on = htole16(onoff); 648 649 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL); 650 651 MALO_HAL_UNLOCK(mh); 652 653 return ret; 654} 655 656/* 657 * Set the interrupt mask. 658 */ 659void 660malo_hal_intrset(struct malo_hal *mh, uint32_t mask) 661{ 662 663 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0); 664 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 665 666 mh->mh_imask = mask; 667 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask); 668 (void)malo_hal_read4(mh, MALO_REG_INT_CODE); 669} 670 671int 672malo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan) 673{ 674 struct malo_cmd_fw_set_rf_channel *cmd; 675 int ret; 676 677 MALO_HAL_LOCK(mh); 678 679 _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel, 680 MALO_HOSTCMD_SET_RF_CHANNEL); 681 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 682 cmd->cur_channel = chan->channel; 683 684 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL); 685 686 MALO_HAL_UNLOCK(mh); 687 688 return ret; 689} 690 691int 692malo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c) 693{ 694 struct malo_cmd_rf_tx_power *cmd; 695 const struct malo_hal_caldata *cal = &mh->mh_caldata; 696 uint8_t chan = c->channel; 697 uint16_t pow; 698 int i, idx, ret; 699 700 MALO_HAL_LOCK(mh); 701 702 _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power, 703 MALO_HOSTCMD_802_11_RF_TX_POWER); 704 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST); 705 for (i = 0; i < 4; i++) { 706 idx = (chan - 1) * 4 + i; 707 pow = cal->pt_ratetable_20m[idx]; 708 cmd->power_levellist[i] = htole16(pow); 709 } 710 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER); 711 712 MALO_HAL_UNLOCK(mh); 713 714 return ret; 715} 716 717int 718malo_hal_setpromisc(struct malo_hal *mh, int enable) 719{ 720 /* XXX need host cmd */ 721 return 0; 722} 723 724int 725malo_hal_setassocid(struct malo_hal *mh, 726 const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd) 727{ 728 struct malo_cmd_fw_set_aid *cmd; 729 int ret; 730 731 MALO_HAL_LOCK(mh); 732 733 _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid, 734 MALO_HOSTCMD_SET_AID); 735 cmd->cmdhdr.seqnum = 1; 736 cmd->associd = htole16(associd); 737 IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid); 738 739 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID); 740 MALO_HAL_UNLOCK(mh); 741 return ret; 742} 743 744/* 745 * Kick the firmware to tell it there are new tx descriptors 746 * for processing. The driver says what h/w q has work in 747 * case the f/w ever gets smarter. 748 */ 749void 750malo_hal_txstart(struct malo_hal *mh, int qnum) 751{ 752 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 753 MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY); 754 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE); 755} 756 757/* 758 * Return the current ISR setting and clear the cause. 759 */ 760void 761malo_hal_getisr(struct malo_hal *mh, uint32_t *status) 762{ 763 uint32_t cause; 764 765 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 766 MALO_REG_A2H_INTERRUPT_CAUSE); 767 if (cause == 0xffffffff) { /* card removed */ 768 cause = 0; 769 } else if (cause != 0) { 770 /* clear cause bits */ 771 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 772 MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 773 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 774 MALO_REG_INT_CODE); 775 cause &= mh->mh_imask; 776 } 777 778 *status = cause; 779} 780 781/* 782 * Callback from the driver on a cmd done interrupt. Nothing to do right 783 * now as we spin waiting for cmd completion. 784 */ 785void 786malo_hal_cmddone(struct malo_hal *mh) 787{ 788 /* NB : do nothing. */ 789} 790 791int 792malo_hal_prescan(struct malo_hal *mh) 793{ 794 struct malo_cmd_prescan *cmd; 795 int ret; 796 797 MALO_HAL_LOCK(mh); 798 799 _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN); 800 cmd->cmdhdr.seqnum = 1; 801 802 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN); 803 804 MALO_HAL_UNLOCK(mh); 805 806 return ret; 807} 808 809int 810malo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson) 811{ 812 struct malo_cmd_postscan *cmd; 813 int ret; 814 815 MALO_HAL_LOCK(mh); 816 817 _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN); 818 cmd->cmdhdr.seqnum = 1; 819 cmd->isibss = htole32(ibsson); 820 IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr); 821 822 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN); 823 824 MALO_HAL_UNLOCK(mh); 825 826 return ret; 827} 828 829int 830malo_hal_set_slot(struct malo_hal *mh, int is_short) 831{ 832 int ret; 833 struct malo_cmd_fw_setslot *cmd; 834 835 MALO_HAL_LOCK(mh); 836 837 _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT); 838 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET); 839 cmd->slot = (is_short == 1 ? 1 : 0); 840 841 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT); 842 843 MALO_HAL_UNLOCK(mh); 844 845 return ret; 846} 847 848int 849malo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate) 850{ 851 int i, ret; 852 struct malo_cmd_set_rate *cmd; 853 854 MALO_HAL_LOCK(mh); 855 856 _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE); 857 cmd->aprates[0] = 2; 858 cmd->aprates[1] = 4; 859 cmd->aprates[2] = 11; 860 cmd->aprates[3] = 22; 861 if (curmode == IEEE80211_MODE_11G) { 862 cmd->aprates[4] = 0; /* XXX reserved? */ 863 cmd->aprates[5] = 12; 864 cmd->aprates[6] = 18; 865 cmd->aprates[7] = 24; 866 cmd->aprates[8] = 36; 867 cmd->aprates[9] = 48; 868 cmd->aprates[10] = 72; 869 cmd->aprates[11] = 96; 870 cmd->aprates[12] = 108; 871 } 872 873 if (rate != 0) { 874 /* fixed rate */ 875 for (i = 0; i < 13; i++) { 876 if (cmd->aprates[i] == rate) { 877 cmd->rateindex = i; 878 cmd->dataratetype = 1; 879 break; 880 } 881 } 882 } 883 884 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE); 885 886 MALO_HAL_UNLOCK(mh); 887 888 return ret; 889} 890 891int 892malo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[]) 893{ 894 struct malo_cmd_mcast *cmd; 895 int ret; 896 897 if (nmc > MALO_HAL_MCAST_MAX) 898 return EINVAL; 899 900 MALO_HAL_LOCK(mh); 901 902 _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR); 903 memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN); 904 cmd->numaddr = htole16(nmc); 905 cmd->action = htole16(0xffff); 906 907 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR); 908 909 MALO_HAL_UNLOCK(mh); 910 911 return ret; 912} 913