1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef _ATH_AR9300_H_ 18#define _ATH_AR9300_H_ 19 20#include "ar9300_freebsd_inc.h" 21 22/* XXX doesn't belong here */ 23#define AR_EEPROM_MODAL_SPURS 5 24 25/* Ensure that AH_BYTE_ORDER is defined */ 26#ifndef AH_BYTE_ORDER 27#error AH_BYTE_ORDER needs to be defined! 28#endif 29 30/* 31 * (a) this should be N(a), 32 * (b) FreeBSD does define nitems, 33 * (c) it doesn't have an AH_ prefix, sigh. 34 */ 35#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) 36 37#include "ah_internal.h" 38#include "ah_eeprom.h" 39#include "ah_devid.h" 40#include "ar9300eep.h" /* For Eeprom definitions */ 41 42#define AR9300_MAGIC 0x19741014 43 44/* MAC register values */ 45 46#define INIT_CONFIG_STATUS 0x00000000 47#define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 48#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ 49 50/* 51 * Various fifo fill before Tx start, in 64-byte units 52 * i.e. put the frame in the air while still DMAing 53 */ 54#define MIN_TX_FIFO_THRESHOLD 0x1 55#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) 56#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 57 58 #define CHANSEL_DIV 15 59 #define FCLK 40 60 61#define COEFF ((FCLK * 5) / 2) 62#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 63#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 64#define CHANSEL_5G_DOT5MHZ 2188 65 66/* 67 * Receive Queue Fifo depth. 68 */ 69enum RX_FIFO_DEPTH { 70 HAL_HP_RXFIFO_DEPTH = 16, 71 HAL_LP_RXFIFO_DEPTH = 128, 72}; 73 74/* 75 * Gain support. 76 */ 77#define NUM_CORNER_FIX_BITS_2133 7 78#define CCK_OFDM_GAIN_DELTA 15 79 80enum GAIN_PARAMS { 81 GP_TXCLIP, 82 GP_PD90, 83 GP_PD84, 84 GP_GSEL 85}; 86 87enum GAIN_PARAMS_2133 { 88 GP_MIXGAIN_OVR, 89 GP_PWD_138, 90 GP_PWD_137, 91 GP_PWD_136, 92 GP_PWD_132, 93 GP_PWD_131, 94 GP_PWD_130, 95}; 96 97typedef struct _gain_opt_step { 98 int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; 99 int32_t stepGain; 100 int8_t stepName[16]; 101} GAIN_OPTIMIZATION_STEP; 102 103typedef struct { 104 u_int32_t numStepsInLadder; 105 u_int32_t defaultStepNum; 106 GAIN_OPTIMIZATION_STEP optStep[10]; 107} GAIN_OPTIMIZATION_LADDER; 108 109typedef struct { 110 u_int32_t currStepNum; 111 u_int32_t currGain; 112 u_int32_t targetGain; 113 u_int32_t loTrig; 114 u_int32_t hiTrig; 115 u_int32_t gainFCorrection; 116 u_int32_t active; 117 GAIN_OPTIMIZATION_STEP *curr_step; 118} GAIN_VALUES; 119 120typedef struct { 121 u_int16_t synth_center; 122 u_int16_t ctl_center; 123 u_int16_t ext_center; 124} CHAN_CENTERS; 125 126/* RF HAL structures */ 127typedef struct rf_hal_funcs { 128 HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *); 129 HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, 130 struct ieee80211_channel *chan); 131} RF_HAL_FUNCS; 132 133struct ar9300_ani_default { 134 u_int16_t m1_thresh_low; 135 u_int16_t m2_thresh_low; 136 u_int16_t m1_thresh; 137 u_int16_t m2_thresh; 138 u_int16_t m2_count_thr; 139 u_int16_t m2_count_thr_low; 140 u_int16_t m1_thresh_low_ext; 141 u_int16_t m2_thresh_low_ext; 142 u_int16_t m1_thresh_ext; 143 u_int16_t m2_thresh_ext; 144 u_int16_t firstep; 145 u_int16_t firstep_low; 146 u_int16_t cycpwr_thr1; 147 u_int16_t cycpwr_thr1_ext; 148}; 149 150/* 151 * Per-channel ANI state private to the driver. 152 */ 153struct ar9300_ani_state { 154 struct ieee80211_channel c; /* XXX ew? */ 155 HAL_BOOL must_restore; 156 HAL_BOOL ofdms_turn; 157 u_int8_t ofdm_noise_immunity_level; 158 u_int8_t cck_noise_immunity_level; 159 u_int8_t spur_immunity_level; 160 u_int8_t firstep_level; 161 u_int8_t ofdm_weak_sig_detect_off; 162 u_int8_t mrc_cck_off; 163 164 /* Thresholds */ 165 u_int32_t listen_time; 166 u_int32_t ofdm_trig_high; 167 u_int32_t ofdm_trig_low; 168 int32_t cck_trig_high; 169 int32_t cck_trig_low; 170 int32_t rssi_thr_low; 171 int32_t rssi_thr_high; 172 173 int32_t rssi; /* The current RSSI */ 174 u_int32_t tx_frame_count; /* Last tx_frame_count */ 175 u_int32_t rx_frame_count; /* Last rx Frame count */ 176 u_int32_t rx_busy_count; /* Last rx busy count */ 177 u_int32_t rx_ext_busy_count; /* Last rx busy count; extension channel */ 178 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ 179 u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ 180 u_int32_t cck_phy_err_count; /* CCK err count since last reset */ 181 182 struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ 183 HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ 184}; 185 186#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ 187 188#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ 189 190#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ 191#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ 192#define HAL_AR_EN 0x40000000 /* AR detect is capable */ 193 194#define DO_ANI(ah) \ 195 ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) 196 197#if 0 198struct ar9300_stats { 199 u_int32_t ast_ani_niup; /* ANI increased noise immunity */ 200 u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ 201 u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ 202 u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 203 u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 204 u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 205 u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 206 u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 207 u_int32_t ast_ani_stepup; /* ANI increased first step level */ 208 u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ 209 u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 210 u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 211 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 212 u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ 213 u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 214 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 215 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 216}; 217#endif 218 219struct ar9300_rad_reader { 220 u_int16_t rd_index; 221 u_int16_t rd_expSeq; 222 u_int32_t rd_resetVal; 223 u_int8_t rd_start; 224}; 225 226struct ar9300_rad_writer { 227 u_int16_t wr_index; 228 u_int16_t wr_seq; 229}; 230 231struct ar9300_radar_event { 232 u_int32_t re_ts; /* 32 bit time stamp */ 233 u_int8_t re_rssi; /* rssi of radar event */ 234 u_int8_t re_dur; /* duration of radar pulse */ 235 u_int8_t re_chanIndex; /* Channel of event */ 236}; 237 238struct ar9300_radar_q_elem { 239 u_int32_t rq_seqNum; 240 u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ 241 struct ar9300_radar_event rq_event; /* Radar event */ 242}; 243 244struct ar9300_radar_q_info { 245 u_int16_t ri_qsize; /* q size */ 246 u_int16_t ri_seqSize; /* Size of sequence ring */ 247 struct ar9300_rad_reader ri_reader; /* State for the q reader */ 248 struct ar9300_rad_writer ri_writer; /* state for the q writer */ 249}; 250 251#define HAL_MAX_ACK_RADAR_DUR 511 252#define HAL_MAX_NUM_PEAKS 3 253#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ 254#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ 255#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ 256#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ 257#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ 258 259struct ar9300_ar_state { 260 u_int16_t ar_prev_time_stamp; 261 u_int32_t ar_prev_width; 262 u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; 263 u_int32_t ar_ack_sum; 264 u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; 265 u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ 266 u_int32_t ar_par_threshold; /* Thresh to determine peak */ 267 u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ 268}; 269 270struct ar9300_radar_state { 271 struct ieee80211_channel *rs_chan; /* Channel info */ 272 u_int8_t rs_chan_index; /* Channel index in radar structure */ 273 u_int32_t rs_num_radar_events; /* Number of radar events */ 274 int32_t rs_firpwr; /* Thresh to check radar sig is gone */ 275 u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ 276 u_int32_t rs_height; /* Thresh for pulse height (dB)*/ 277 u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ 278 u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ 279}; 280typedef struct { 281 u_int8_t uc_receiver_errors; 282 u_int8_t uc_bad_tlp_errors; 283 u_int8_t uc_bad_dllp_errors; 284 u_int8_t uc_replay_timeout_errors; 285 u_int8_t uc_replay_number_rollover_errors; 286} ar_pcie_error_moniter_counters; 287 288#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ 289#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ 290#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ 291#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ 292#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ 293#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ 294 295/* 296 * For Kite and later chipsets, the following bits are not being programmed in EEPROM 297 * and so need to be enabled always. 298 * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 299 * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 300 */ 301#define AR9300_RDEXT_DEFAULT 0x1F 302 303#define AR9300_MAX_CHAINS 3 304#define AR9300_NUM_CHAINS(chainmask) \ 305 (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) 306#define AR9300_CHAIN0_MASK 0x1 307#define AR9300_CHAIN1_MASK 0x2 308#define AR9300_CHAIN2_MASK 0x4 309 310/* Support for multiple INIs */ 311struct ar9300_ini_array { 312 const u_int32_t *ia_array; 313 u_int32_t ia_rows; 314 u_int32_t ia_columns; 315}; 316#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 317 (iniarray)->ia_array = (const u_int32_t *)(array); \ 318 (iniarray)->ia_rows = (rows); \ 319 (iniarray)->ia_columns = (columns); \ 320} while (0) 321#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 322 323#define INIT_CAL(_perCal) \ 324 (_perCal)->cal_state = CAL_WAITING; \ 325 (_perCal)->cal_next = AH_NULL; 326 327#define INSERT_CAL(_ahp, _perCal) \ 328do { \ 329 if ((_ahp)->ah_cal_list_last == AH_NULL) { \ 330 (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ 331 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 332 } else { \ 333 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 334 (_ahp)->ah_cal_list_last = (_perCal); \ 335 (_perCal)->cal_next = (_ahp)->ah_cal_list; \ 336 } \ 337} while (0) 338 339typedef enum cal_types { 340 IQ_MISMATCH_CAL = 0x1, 341 TEMP_COMP_CAL = 0x2, 342} HAL_CAL_TYPES; 343 344typedef enum cal_state { 345 CAL_INACTIVE, 346 CAL_WAITING, 347 CAL_RUNNING, 348 CAL_DONE 349} HAL_CAL_STATE; /* Calibrate state */ 350 351#define MIN_CAL_SAMPLES 1 352#define MAX_CAL_SAMPLES 64 353#define INIT_LOG_COUNT 5 354#define PER_MIN_LOG_COUNT 2 355#define PER_MAX_LOG_COUNT 10 356 357#define AR9300_NUM_BT_WEIGHTS 4 358#define AR9300_NUM_WLAN_WEIGHTS 4 359 360/* Per Calibration data structure */ 361typedef struct per_cal_data { 362 HAL_CAL_TYPES cal_type; // Type of calibration 363 u_int32_t cal_num_samples; // Number of SW samples to collect 364 u_int32_t cal_count_max; // Number of HW samples to collect 365 void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func 366 void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func 367} HAL_PERCAL_DATA; 368 369/* List structure for calibration data */ 370typedef struct cal_list { 371 const HAL_PERCAL_DATA *cal_data; 372 HAL_CAL_STATE cal_state; 373 struct cal_list *cal_next; 374} HAL_CAL_LIST; 375 376#define AR9300_NUM_CAL_TYPES 2 377#define AR9300_PAPRD_TABLE_SZ 24 378#define AR9300_PAPRD_GAIN_TABLE_SZ 32 379#define AR9382_MAX_GPIO_PIN_NUM (16) 380#define AR9382_GPIO_PIN_8_RESERVED (8) 381#define AR9382_GPIO_9_INPUT_ONLY (9) 382#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) 383#define AR9382_GPIO_PIN_11_RESERVED (11) 384#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) 385 386/* Paprd tx power adjust data structure */ 387struct ar9300_paprd_pwr_adjust { 388 u_int32_t target_rate; // rate index 389 u_int32_t reg_addr; // register offset 390 u_int32_t reg_mask; // mask of register 391 u_int32_t reg_mask_offset; // mask offset of register 392 u_int32_t sub_db; // offset value unit of dB 393}; 394 395struct ar9300NfLimits { 396 int16_t max; 397 int16_t min; 398 int16_t nominal; 399}; 400 401#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ 402struct ath_hal_9300 { 403 struct ath_hal_private ah_priv; /* base class */ 404 405 /* 406 * Information retrieved from EEPROM. 407 */ 408 ar9300_eeprom_t ah_eeprom; 409 410 GAIN_VALUES ah_gain_values; 411 412 u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; 413 u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; 414 u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; 415 u_int16_t ah_assoc_id; 416 417 /* 418 * Runtime state. 419 */ 420 u_int32_t ah_mask_reg; /* copy of AR_IMR */ 421 u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ 422 u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ 423 os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ 424 HAL_ANI_STATS ah_stats; /* various statistics */ 425 RF_HAL_FUNCS ah_rf_hal; 426 u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ 427 u_int32_t ah_tx_ok_interrupt_mask; 428 u_int32_t ah_tx_err_interrupt_mask; 429 u_int32_t ah_tx_desc_interrupt_mask; 430 u_int32_t ah_tx_eol_interrupt_mask; 431 u_int32_t ah_tx_urn_interrupt_mask; 432 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 433 HAL_SMPS_MODE ah_sm_power_mode; 434 HAL_BOOL ah_chip_full_sleep; 435 u_int32_t ah_atim_window; 436 HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ 437 u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ 438 u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ 439 u_int8_t ah_rx_chainmask_cfg; 440 u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ 441 /* Calibration related fields */ 442 HAL_CAL_TYPES ah_supp_cals; 443 HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ 444 HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ 445 HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ 446 HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ 447 HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ 448// IQ Cal aliases 449#define ah_total_power_meas_i ah_meas0.unsign 450#define ah_total_power_meas_q ah_meas1.unsign 451#define ah_total_iq_corr_meas ah_meas2.sign 452 union { 453 u_int32_t unsign[AR9300_MAX_CHAINS]; 454 int32_t sign[AR9300_MAX_CHAINS]; 455 } ah_meas0; 456 union { 457 u_int32_t unsign[AR9300_MAX_CHAINS]; 458 int32_t sign[AR9300_MAX_CHAINS]; 459 } ah_meas1; 460 union { 461 u_int32_t unsign[AR9300_MAX_CHAINS]; 462 int32_t sign[AR9300_MAX_CHAINS]; 463 } ah_meas2; 464 union { 465 u_int32_t unsign[AR9300_MAX_CHAINS]; 466 int32_t sign[AR9300_MAX_CHAINS]; 467 } ah_meas3; 468 u_int16_t ah_cal_samples; 469 /* end - Calibration related fields */ 470 u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ 471 u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ 472 u_int32_t ah_misc_mode; /* MISC_MODE settings */ 473 HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ 474 enum { 475 AUTO_32KHZ, /* use it if 32kHz crystal present */ 476 USE_32KHZ, /* do it regardless */ 477 DONT_USE_32KHZ, /* don't use it regardless */ 478 } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ 479 480 u_int32_t ah_ofdm_tx_power; 481 int16_t ah_tx_power_index_offset; 482 483 u_int ah_slot_time; /* user-specified slot time */ 484 u_int ah_ack_timeout; /* user-specified ack timeout */ 485 /* 486 * XXX 487 * 11g-specific stuff; belongs in the driver. 488 */ 489 u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ 490 u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ 491 u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ 492 /* 493 * RF Silent handling; setup according to the EEPROM. 494 */ 495 u_int32_t ah_gpio_select; /* GPIO pin to use */ 496 u_int32_t ah_polarity; /* polarity to disable RF */ 497 u_int32_t ah_gpio_bit; /* after init, prev value */ 498 HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ 499 500#ifdef ATH_BT_COEX 501 /* 502 * Bluetooth coexistence static setup according to the registry 503 */ 504 HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ 505 u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ 506 u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ 507 u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ 508 u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ 509 u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ 510 HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ 511 u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ 512 /* 513 * Bluetooth coexistence runtime settings 514 */ 515 HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ 516 u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 517 u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 518 u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 519 u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 520 u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ 521#endif 522 523 /* 524 * Generic timer support 525 */ 526 u_int32_t ah_avail_gen_timers; /* mask of available timers */ 527 u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ 528 u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ 529 HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ 530 531 /* 532 * ANI & Radar support. 533 */ 534 u_int32_t ah_proc_phy_err; /* Process Phy errs */ 535 u_int32_t ah_ani_period; /* ani update list period */ 536 struct ar9300_ani_state *ah_curani; /* cached last reference */ 537 struct ar9300_ani_state ah_ani[255]; /* per-channel state */ 538 struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ 539 struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ 540 struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ 541 struct ar9300_ar_state ah_ar; /* AR detector state */ 542 struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ 543 struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ 544 545 /* 546 * Transmit power state. Note these are maintained 547 * here so they can be retrieved by diagnostic tools. 548 */ 549 u_int16_t ah_rates_array[16]; 550 551 /* 552 * Tx queue interrupt state. 553 */ 554 u_int32_t ah_intr_txqs; 555 556 HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ 557 HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ 558 559 /* 560 * Extension Channel Rx Clear State 561 */ 562 u_int32_t ah_cycle_count; 563 u_int32_t ah_ctl_busy; 564 u_int32_t ah_ext_busy; 565 566 /* HT CWM state */ 567 HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; 568 u_int8_t ah_tx_chainmask; /* tx chain mask */ 569 u_int8_t ah_rx_chainmask; /* rx chain mask */ 570 571 /* optional tx chainmask */ 572 u_int8_t ah_tx_chainmaskopt; 573 574 u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ 575 u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ 576 577 int ah_hwp; 578 void *ah_cal_mem; 579 HAL_BOOL ah_emu_eeprom; 580 581 HAL_ANI_CMD ah_ani_function; 582 HAL_BOOL ah_rifs_enabled; 583 u_int32_t ah_rifs_reg[11]; 584 u_int32_t ah_rifs_sec_cnt; 585 586 /* open-loop power control */ 587 u_int32_t original_gain[22]; 588 int32_t init_pdadc; 589 int32_t pdadc_delta; 590 591 /* cycle counts for beacon stuck diagnostics */ 592 u_int32_t ah_cycles; 593 u_int32_t ah_rx_clear; 594 u_int32_t ah_rx_frame; 595 u_int32_t ah_tx_frame; 596 597#define BB_HANG_SIG1 0 598#define BB_HANG_SIG2 1 599#define BB_HANG_SIG3 2 600#define BB_HANG_SIG4 3 601#define MAC_HANG_SIG1 4 602#define MAC_HANG_SIG2 5 603 /* bb hang detection */ 604 int ah_hang[6]; 605 hal_hw_hangs_t ah_hang_wars; 606 607 /* 608 * Keytable type table 609 */ 610#define AR_KEYTABLE_SIZE 128 /* XXX! */ 611 uint8_t ah_keytype[AR_KEYTABLE_SIZE]; 612#undef AR_KEYTABLE_SIZE 613 /* 614 * Support for ar9300 multiple INIs 615 */ 616 struct ar9300_ini_array ah_ini_pcie_serdes; 617 struct ar9300_ini_array ah_ini_pcie_serdes_low_power; 618 struct ar9300_ini_array ah_ini_modes_additional; 619 struct ar9300_ini_array ah_ini_modes_additional_40mhz; 620 struct ar9300_ini_array ah_ini_modes_rxgain; 621 struct ar9300_ini_array ah_ini_modes_rxgain_bounds; 622 struct ar9300_ini_array ah_ini_modes_txgain; 623 struct ar9300_ini_array ah_ini_japan2484; 624 struct ar9300_ini_array ah_ini_radio_post_sys2ant; 625 struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; 626 struct ar9300_ini_array ah_ini_modes_rxgain_xlna; 627 struct ar9300_ini_array ah_ini_modes_rxgain_bb_core; 628 struct ar9300_ini_array ah_ini_modes_rxgain_bb_postamble; 629 630 /* 631 * New INI format starting with Osprey 2.0 INI. 632 * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) 633 */ 634 #define ATH_INI_PRE 0 635 #define ATH_INI_CORE 1 636 #define ATH_INI_POST 2 637 #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) 638 struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ 639 struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ 640 struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ 641 struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ 642 643 /* 644 * Added to support DFS postamble array in INI that we need to apply 645 * in DFS channels 646 */ 647 648 struct ar9300_ini_array ah_ini_dfs; 649 650#if ATH_WOW 651 struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ 652#endif 653 654 /* To indicate EEPROM mapping used */ 655 u_int32_t ah_immunity_vals[6]; 656 HAL_BOOL ah_immunity_on; 657 /* 658 * snap shot of counter register for debug purposes 659 */ 660#ifdef AH_DEBUG 661 u_int32_t last_tf; 662 u_int32_t last_rf; 663 u_int32_t last_rc; 664 u_int32_t last_cc; 665#endif 666 HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ 667 u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ 668 669 u_int32_t reg_dmn; /* Regulatory Domain */ 670 int16_t twice_antenna_gain; /* Antenna Gain */ 671 u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ 672 673 /* 674 * Upper limit after factoring in the regulatory max, antenna gain and 675 * multichain factor. No TxBF, CDD or STBC gain factored 676 */ 677 int16_t upper_limit[AR9300_MAX_CHAINS]; 678 679 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ 680 int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 681 682 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ 683 int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 684 685 /* Transmit Status ring support */ 686 struct ar9300_txs *ts_ring; 687 u_int16_t ts_tail; 688 u_int16_t ts_size; 689 u_int32_t ts_paddr_start; 690 u_int32_t ts_paddr_end; 691 692 /* Receive Buffer size */ 693#define HAL_RXBUFSIZE_DEFAULT 0xfff 694 u_int16_t rx_buf_size; 695 696 u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). 697 698 /* Indicate the PLL source clock rate is 25Mhz or not. 699 * clk_25mhz = 0 by default. 700 */ 701 u_int8_t clk_25mhz; 702 /* For PAPRD uses */ 703 u_int16_t small_signal_gain[AH_MAX_CHAINS]; 704 u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; 705 u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; 706 u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; 707 u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ 708 u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ 709 u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ 710 u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ 711 u_int32_t paprd_training_power; 712 /* For GreenTx use to store the default tx power */ 713 u_int8_t ah_default_tx_power[ar9300_rate_size]; 714 HAL_BOOL ah_paprd_broken; 715 716 /* To store offsets of host interface registers */ 717 struct { 718 u_int32_t AR_RC; 719 u_int32_t AR_WA; 720 u_int32_t AR_PM_STATE; 721 u_int32_t AR_H_INFOL; 722 u_int32_t AR_H_INFOH; 723 u_int32_t AR_PCIE_PM_CTRL; 724 u_int32_t AR_HOST_TIMEOUT; 725 u_int32_t AR_EEPROM; 726 u_int32_t AR_SREV; 727 u_int32_t AR_INTR_SYNC_CAUSE; 728 u_int32_t AR_INTR_SYNC_CAUSE_CLR; 729 u_int32_t AR_INTR_SYNC_ENABLE; 730 u_int32_t AR_INTR_ASYNC_MASK; 731 u_int32_t AR_INTR_SYNC_MASK; 732 u_int32_t AR_INTR_ASYNC_CAUSE_CLR; 733 u_int32_t AR_INTR_ASYNC_CAUSE; 734 u_int32_t AR_INTR_ASYNC_ENABLE; 735 u_int32_t AR_PCIE_SERDES; 736 u_int32_t AR_PCIE_SERDES2; 737 u_int32_t AR_GPIO_OUT; 738 u_int32_t AR_GPIO_IN; 739 u_int32_t AR_GPIO_OE_OUT; 740 u_int32_t AR_GPIO_OE1_OUT; 741 u_int32_t AR_GPIO_INTR_POL; 742 u_int32_t AR_GPIO_INPUT_EN_VAL; 743 u_int32_t AR_GPIO_INPUT_MUX1; 744 u_int32_t AR_GPIO_INPUT_MUX2; 745 u_int32_t AR_GPIO_OUTPUT_MUX1; 746 u_int32_t AR_GPIO_OUTPUT_MUX2; 747 u_int32_t AR_GPIO_OUTPUT_MUX3; 748 u_int32_t AR_INPUT_STATE; 749 u_int32_t AR_SPARE; 750 u_int32_t AR_PCIE_CORE_RESET_EN; 751 u_int32_t AR_CLKRUN; 752 u_int32_t AR_EEPROM_STATUS_DATA; 753 u_int32_t AR_OBS; 754 u_int32_t AR_RFSILENT; 755 u_int32_t AR_GPIO_PDPU; 756 u_int32_t AR_GPIO_DS; 757 u_int32_t AR_MISC; 758 u_int32_t AR_PCIE_MSI; 759 u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; 760 u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; 761 u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; 762 u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; 763 u_int32_t AR_TDMA_CCA_CNTL; 764 u_int32_t AR_TXAPSYNC; 765 u_int32_t AR_TXSYNC_INIT_SYNC_TMR; 766 u_int32_t AR_INTR_PRIO_SYNC_CAUSE; 767 u_int32_t AR_INTR_PRIO_SYNC_ENABLE; 768 u_int32_t AR_INTR_PRIO_ASYNC_MASK; 769 u_int32_t AR_INTR_PRIO_SYNC_MASK; 770 u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; 771 u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; 772 } ah_hostifregs; 773 774 u_int32_t ah_enterprise_mode; 775 u_int32_t ah_radar1; 776 u_int32_t ah_dc_offset; 777 HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ 778 HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ 779 u_int32_t ah_disable_cck; 780 HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ 781 782 783 /* 784 * Different types of memory where the calibration data might be stored. 785 * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. 786 * To disable searching a type, set its parameter to 0. 787 */ 788 int try_dram; 789 int try_flash; 790 int try_eeprom; 791 int try_otp; 792#ifdef ATH_CAL_NAND_FLASH 793 int try_nand; 794#endif 795 /* 796 * This is where we found the calibration data. 797 */ 798 int calibration_data_source; 799 int calibration_data_source_address; 800 /* 801 * This is where we look for the calibration data. must be set before ath_attach() is called 802 */ 803 int calibration_data_try; 804 int calibration_data_try_address; 805 u_int8_t 806 tx_iq_cal_enable : 1, 807 tx_iq_cal_during_agc_cal : 1, 808 tx_cl_cal_enable : 1; 809 810#if ATH_SUPPORT_MCI 811 /* For MCI */ 812 HAL_BOOL ah_mci_ready; 813 u_int32_t ah_mci_int_raw; 814 u_int32_t ah_mci_int_rx_msg; 815 u_int32_t ah_mci_rx_status; 816 u_int32_t ah_mci_cont_status; 817 u_int8_t ah_mci_bt_state; 818 u_int32_t ah_mci_gpm_addr; 819 u_int8_t *ah_mci_gpm_buf; 820 u_int32_t ah_mci_gpm_len; 821 u_int32_t ah_mci_gpm_idx; 822 u_int32_t ah_mci_sched_addr; 823 u_int8_t *ah_mci_sched_buf; 824 u_int8_t ah_mci_coex_major_version_wlan; 825 u_int8_t ah_mci_coex_minor_version_wlan; 826 u_int8_t ah_mci_coex_major_version_bt; 827 u_int8_t ah_mci_coex_minor_version_bt; 828 HAL_BOOL ah_mci_coex_bt_version_known; 829 HAL_BOOL ah_mci_coex_wlan_channels_update; 830 u_int32_t ah_mci_coex_wlan_channels[4]; 831 HAL_BOOL ah_mci_coex_2g5g_update; 832 HAL_BOOL ah_mci_coex_is_2g; 833 HAL_BOOL ah_mci_query_bt; 834 HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ 835 HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ 836 HAL_BOOL ah_mci_need_flush_btinfo; 837 HAL_BOOL ah_mci_concur_tx_en; 838 u_int8_t ah_mci_stomp_low_tx_pri; 839 u_int8_t ah_mci_stomp_all_tx_pri; 840 u_int8_t ah_mci_stomp_none_tx_pri; 841 u_int32_t ah_mci_wlan_cal_seq; 842 u_int32_t ah_mci_wlan_cal_done; 843#if ATH_SUPPORT_AIC 844 HAL_BOOL ah_aic_enabled; 845 u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; 846#endif 847 848#endif /* ATH_SUPPORT_MCI */ 849 u_int8_t ah_cac_quiet_enabled; 850#if ATH_WOW_OFFLOAD 851 u_int32_t ah_mcast_filter_l32_set; 852 u_int32_t ah_mcast_filter_u32_set; 853#endif 854 HAL_BOOL ah_reduced_self_gen_mask; 855 HAL_BOOL ah_chip_reset_done; 856 HAL_BOOL ah_abort_txdma_norx; 857 /* store previous passive RX Cal info */ 858 HAL_BOOL ah_skip_rx_iq_cal; 859 HAL_BOOL ah_rx_cal_complete; /* previous rx cal completed or not */ 860 u_int32_t ah_rx_cal_chan; /* chan on which rx cal is done */ 861 u_int32_t ah_rx_cal_chan_flag; 862 u_int32_t ah_rx_cal_corr[AR9300_MAX_CHAINS]; 863 864 /* Local additions for FreeBSD */ 865 /* 866 * These fields are in the top level HAL in the atheros 867 * codebase; here we place them in the AR9300 HAL and 868 * access them via accessor methods if the driver requires them. 869 */ 870 u_int32_t ah_ob_db1[3]; 871 u_int32_t ah_db2[3]; 872 u_int32_t ah_bb_panic_timeout_ms; 873 u_int32_t ah_bb_panic_last_status; 874 u_int32_t ah_tx_trig_level; 875 u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2]; 876 int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */ 877 int ah_phyrestart_disabled; 878 HAL_RSSI_TX_POWER green_tx_status; 879 int green_ap_ps_on; 880 int ah_enable_keysearch_always; 881 int ah_fccaifs; 882 int ah_reset_reason; 883 int ah_dcs_enable; 884 HAL_ANI_STATE ext_ani_state; /* FreeBSD; external facing ANI state */ 885 886 struct ar9300NfLimits nf_2GHz; 887 struct ar9300NfLimits nf_5GHz; 888 struct ar9300NfLimits *nfp; 889 890 uint32_t ah_beaconInterval; 891}; 892 893#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) 894 895#define IS_9300_EMU(ah) \ 896 (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) 897 898#define ar9300_eep_data_in_flash(_ah) \ 899 (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) 900 901#ifdef notyet 902// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. 903&& \ 904 ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ 905 (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) 906#endif 907 908/* 909 * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows 910 * other cards' DMA reads to complete in the middle of our reset. 911 */ 912#define WAR_6773(x) do { \ 913 if ((++(x) % 64) == 0) \ 914 OS_DELAY(1); \ 915} while (0) 916 917#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 918 int r; \ 919 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 920 OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ 921 WAR_6773(regWr); \ 922 } \ 923} while (0) 924 925#define UPPER_5G_SUB_BANDSTART 5700 926#define MID_5G_SUB_BANDSTART 5400 927#define TRAINPOWER_DB_OFFSET 6 928 929#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ 930 } else { \ 931 if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ 932 else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ 933 { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ 934 else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) 935 936#ifdef AH_ASSERT 937 #define ar9300FeatureNotSupported(feature, ah, func) \ 938 ath_hal_printf(ah, # feature \ 939 " not supported but called from %s\n", (func)), \ 940 hal_assert(0) 941#else 942 #define ar9300FeatureNotSupported(feature, ah, func) \ 943 ath_hal_printf(ah, # feature \ 944 " not supported but called from %s\n", (func)) 945#endif /* AH_ASSERT */ 946 947/* 948 * Green Tx, Based on different RSSI of Received Beacon thresholds, 949 * using different tx power by modified register tx power related values. 950 * The thresholds are decided by system team. 951 */ 952#define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ 953#define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ 954#define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta 955 Calibration Offset */ 956#define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value 957 in short distance*/ 958#define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value 959 in middle distance */ 960#define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value 961 in long distance */ 962#define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx 963 BB_powertx_rate9 reg 964 value in short 965 distance */ 966#define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx 967 BB_powertx_rate9 reg 968 value in middle 969 distance */ 970 971 972/* Tx power for short distacnce in SwGreenTx.*/ 973static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { 974 6, /*ALL_TARGET_LEGACY_6_24*/ 975 6, /*ALL_TARGET_LEGACY_36*/ 976 6, /*ALL_TARGET_LEGACY_48*/ 977 4, /*ALL_TARGET_LEGACY_54*/ 978 6, /*ALL_TARGET_LEGACY_1L_5L*/ 979 6, /*ALL_TARGET_LEGACY_5S*/ 980 6, /*ALL_TARGET_LEGACY_11L*/ 981 6, /*ALL_TARGET_LEGACY_11S*/ 982 6, /*ALL_TARGET_HT20_0_8_16*/ 983 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 984 4, /*ALL_TARGET_HT20_4*/ 985 4, /*ALL_TARGET_HT20_5*/ 986 4, /*ALL_TARGET_HT20_6*/ 987 2, /*ALL_TARGET_HT20_7*/ 988 0, /*ALL_TARGET_HT20_12*/ 989 0, /*ALL_TARGET_HT20_13*/ 990 0, /*ALL_TARGET_HT20_14*/ 991 0, /*ALL_TARGET_HT20_15*/ 992 0, /*ALL_TARGET_HT20_20*/ 993 0, /*ALL_TARGET_HT20_21*/ 994 0, /*ALL_TARGET_HT20_22*/ 995 0, /*ALL_TARGET_HT20_23*/ 996 6, /*ALL_TARGET_HT40_0_8_16*/ 997 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 998 4, /*ALL_TARGET_HT40_4*/ 999 4, /*ALL_TARGET_HT40_5*/ 1000 4, /*ALL_TARGET_HT40_6*/ 1001 2, /*ALL_TARGET_HT40_7*/ 1002 0, /*ALL_TARGET_HT40_12*/ 1003 0, /*ALL_TARGET_HT40_13*/ 1004 0, /*ALL_TARGET_HT40_14*/ 1005 0, /*ALL_TARGET_HT40_15*/ 1006 0, /*ALL_TARGET_HT40_20*/ 1007 0, /*ALL_TARGET_HT40_21*/ 1008 0, /*ALL_TARGET_HT40_22*/ 1009 0 /*ALL_TARGET_HT40_23*/ 1010}; 1011 1012/* Tx power for middle distacnce in SwGreenTx.*/ 1013static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { 1014 14, /*ALL_TARGET_LEGACY_6_24*/ 1015 14, /*ALL_TARGET_LEGACY_36*/ 1016 14, /*ALL_TARGET_LEGACY_48*/ 1017 12, /*ALL_TARGET_LEGACY_54*/ 1018 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1019 14, /*ALL_TARGET_LEGACY_5S*/ 1020 14, /*ALL_TARGET_LEGACY_11L*/ 1021 14, /*ALL_TARGET_LEGACY_11S*/ 1022 14, /*ALL_TARGET_HT20_0_8_16*/ 1023 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1024 14, /*ALL_TARGET_HT20_4*/ 1025 14, /*ALL_TARGET_HT20_5*/ 1026 12, /*ALL_TARGET_HT20_6*/ 1027 10, /*ALL_TARGET_HT20_7*/ 1028 0, /*ALL_TARGET_HT20_12*/ 1029 0, /*ALL_TARGET_HT20_13*/ 1030 0, /*ALL_TARGET_HT20_14*/ 1031 0, /*ALL_TARGET_HT20_15*/ 1032 0, /*ALL_TARGET_HT20_20*/ 1033 0, /*ALL_TARGET_HT20_21*/ 1034 0, /*ALL_TARGET_HT20_22*/ 1035 0, /*ALL_TARGET_HT20_23*/ 1036 14, /*ALL_TARGET_HT40_0_8_16*/ 1037 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1038 14, /*ALL_TARGET_HT40_4*/ 1039 14, /*ALL_TARGET_HT40_5*/ 1040 12, /*ALL_TARGET_HT40_6*/ 1041 10, /*ALL_TARGET_HT40_7*/ 1042 0, /*ALL_TARGET_HT40_12*/ 1043 0, /*ALL_TARGET_HT40_13*/ 1044 0, /*ALL_TARGET_HT40_14*/ 1045 0, /*ALL_TARGET_HT40_15*/ 1046 0, /*ALL_TARGET_HT40_20*/ 1047 0, /*ALL_TARGET_HT40_21*/ 1048 0, /*ALL_TARGET_HT40_22*/ 1049 0 /*ALL_TARGET_HT40_23*/ 1050}; 1051 1052/* OLPC DeltaCalibration Offset unit in half dB.*/ 1053static const u_int8_t wb225_gtx_olpc_cal_offset[6] = { 1054 0, /* OB0*/ 1055 16, /* OB1*/ 1056 9, /* OB2*/ 1057 5, /* OB3*/ 1058 2, /* OB4*/ 1059 0, /* OB5*/ 1060}; 1061 1062/* 1063 * Definitions for HwGreenTx 1064 */ 1065#define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ 1066#define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ 1067#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx 1068 BB_powertx_rate9 reg 1069 value in short 1070 distance */ 1071#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx 1072 BB_powertx_rate9 reg 1073 value in middle 1074 distance */ 1075 1076/* Tx power for short distacnce in HwGreenTx.*/ 1077static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { 1078 14, /*ALL_TARGET_LEGACY_6_24*/ 1079 14, /*ALL_TARGET_LEGACY_36*/ 1080 8, /*ALL_TARGET_LEGACY_48*/ 1081 2, /*ALL_TARGET_LEGACY_54*/ 1082 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1083 14, /*ALL_TARGET_LEGACY_5S*/ 1084 14, /*ALL_TARGET_LEGACY_11L*/ 1085 14, /*ALL_TARGET_LEGACY_11S*/ 1086 12, /*ALL_TARGET_HT20_0_8_16*/ 1087 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1088 12, /*ALL_TARGET_HT20_4*/ 1089 12, /*ALL_TARGET_HT20_5*/ 1090 8, /*ALL_TARGET_HT20_6*/ 1091 2, /*ALL_TARGET_HT20_7*/ 1092 0, /*ALL_TARGET_HT20_12*/ 1093 0, /*ALL_TARGET_HT20_13*/ 1094 0, /*ALL_TARGET_HT20_14*/ 1095 0, /*ALL_TARGET_HT20_15*/ 1096 0, /*ALL_TARGET_HT20_20*/ 1097 0, /*ALL_TARGET_HT20_21*/ 1098 0, /*ALL_TARGET_HT20_22*/ 1099 0, /*ALL_TARGET_HT20_23*/ 1100 10, /*ALL_TARGET_HT40_0_8_16*/ 1101 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1102 10, /*ALL_TARGET_HT40_4*/ 1103 10, /*ALL_TARGET_HT40_5*/ 1104 6, /*ALL_TARGET_HT40_6*/ 1105 2, /*ALL_TARGET_HT40_7*/ 1106 0, /*ALL_TARGET_HT40_12*/ 1107 0, /*ALL_TARGET_HT40_13*/ 1108 0, /*ALL_TARGET_HT40_14*/ 1109 0, /*ALL_TARGET_HT40_15*/ 1110 0, /*ALL_TARGET_HT40_20*/ 1111 0, /*ALL_TARGET_HT40_21*/ 1112 0, /*ALL_TARGET_HT40_22*/ 1113 0 /*ALL_TARGET_HT40_23*/ 1114}; 1115 1116/* Tx power for middle distacnce in HwGreenTx.*/ 1117static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { 1118 18, /*ALL_TARGET_LEGACY_6_24*/ 1119 18, /*ALL_TARGET_LEGACY_36*/ 1120 14, /*ALL_TARGET_LEGACY_48*/ 1121 12, /*ALL_TARGET_LEGACY_54*/ 1122 18, /*ALL_TARGET_LEGACY_1L_5L*/ 1123 18, /*ALL_TARGET_LEGACY_5S*/ 1124 18, /*ALL_TARGET_LEGACY_11L*/ 1125 18, /*ALL_TARGET_LEGACY_11S*/ 1126 16, /*ALL_TARGET_HT20_0_8_16*/ 1127 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1128 16, /*ALL_TARGET_HT20_4*/ 1129 16, /*ALL_TARGET_HT20_5*/ 1130 14, /*ALL_TARGET_HT20_6*/ 1131 12, /*ALL_TARGET_HT20_7*/ 1132 0, /*ALL_TARGET_HT20_12*/ 1133 0, /*ALL_TARGET_HT20_13*/ 1134 0, /*ALL_TARGET_HT20_14*/ 1135 0, /*ALL_TARGET_HT20_15*/ 1136 0, /*ALL_TARGET_HT20_20*/ 1137 0, /*ALL_TARGET_HT20_21*/ 1138 0, /*ALL_TARGET_HT20_22*/ 1139 0, /*ALL_TARGET_HT20_23*/ 1140 14, /*ALL_TARGET_HT40_0_8_16*/ 1141 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1142 14, /*ALL_TARGET_HT40_4*/ 1143 14, /*ALL_TARGET_HT40_5*/ 1144 14, /*ALL_TARGET_HT40_6*/ 1145 12, /*ALL_TARGET_HT40_7*/ 1146 0, /*ALL_TARGET_HT40_12*/ 1147 0, /*ALL_TARGET_HT40_13*/ 1148 0, /*ALL_TARGET_HT40_14*/ 1149 0, /*ALL_TARGET_HT40_15*/ 1150 0, /*ALL_TARGET_HT40_20*/ 1151 0, /*ALL_TARGET_HT40_21*/ 1152 0, /*ALL_TARGET_HT40_22*/ 1153 0 /*ALL_TARGET_HT40_23*/ 1154}; 1155 1156/* MIMO Modes used in TPC calculations */ 1157typedef enum { 1158 AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ 1159 AR9300_TXBF_MODE, 1160 AR9300_STBC_MODE 1161} AR9300_TXMODES; 1162typedef enum { 1163 POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ 1164 POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ 1165 POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in 1166 * BB_powertx_rate9 reg 1167 */ 1168 POSEIDON_STORED_REG_SZ /* Can not add anymore */ 1169} POSEIDON_STORED_REGS; 1170 1171typedef enum { 1172 POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ 1173 POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ 1174} POSEIDON_STORED_REGS_G2; 1175 1176#if AH_NEED_TX_DATA_SWAP 1177#if AH_NEED_RX_DATA_SWAP 1178#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) 1179#else 1180#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) 1181#endif 1182#elif AH_NEED_RX_DATA_SWAP 1183#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) 1184#else 1185#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) 1186#endif 1187 1188extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); 1189 1190struct ath_hal; 1191 1192extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, 1193 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1194 HAL_OPS_CONFIG *ah_config, 1195 HAL_STATUS *status); 1196extern struct ath_hal * ar9300_attach(u_int16_t devid, 1197 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1198 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status); 1199extern void ar9300_detach(struct ath_hal *ah); 1200extern void ar9300_read_revisions(struct ath_hal *ah); 1201extern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); 1202extern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, 1203 u_int16_t flags, u_int16_t *low, u_int16_t *high); 1204extern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); 1205 1206extern void ar9300_beacon_init(struct ath_hal *ah, 1207 u_int32_t next_beacon, u_int32_t beacon_period, 1208 u_int32_t beacon_period_fraction, HAL_OPMODE opmode); 1209extern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, 1210 const HAL_BEACON_STATE *); 1211 1212extern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); 1213extern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); 1214extern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); 1215extern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); 1216extern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, 1217 HAL_INT_MITIGATION reg, u_int32_t value); 1218extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, 1219 HAL_INT_MITIGATION reg); 1220extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); 1221extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); 1222extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); 1223extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah, 1224 const struct ieee80211_channel *chan); 1225 1226extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, 1227 u_int16_t entry, const u_int8_t *mac); 1228extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1229 const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); 1230extern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); 1231#if ATH_SUPPORT_KEYPLUMB_WAR 1232extern HAL_BOOL ar9300_check_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1233 const HAL_KEYVAL *k, int xorKey); 1234#endif 1235 1236extern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); 1237extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); 1238extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); 1239extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); 1240extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); 1241#if 0 1242extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 1243#endif 1244extern HAL_BOOL ar9300_ant_swcom_sel(struct ath_hal *ah, u_int8_t ops, 1245 u_int32_t *common_tbl1, u_int32_t *common_tbl2); 1246extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, 1247 u_int16_t reg_domain, HAL_STATUS *stats); 1248extern u_int ar9300_get_wireless_modes(struct ath_hal *ah); 1249extern void ar9300_enable_rf_kill(struct ath_hal *); 1250extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1251extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1252extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); 1253extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); 1254extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); 1255extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); 1256extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); 1257extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); 1258extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); 1259extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); 1260extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); 1261extern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); 1262extern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); 1263extern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); 1264extern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 1265 u_int16_t assoc_id); 1266extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); 1267extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); 1268extern int ar9300_ppm_get_trigger(struct ath_hal *); 1269extern u_int32_t ar9300_ppm_force(struct ath_hal *); 1270extern void ar9300_ppm_un_force(struct ath_hal *); 1271extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); 1272extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); 1273extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); 1274extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); 1275extern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); 1276extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); 1277extern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); 1278extern void ar9300_reset_tsf(struct ath_hal *ah); 1279extern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); 1280extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); 1281extern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); 1282extern void ar9300_update_mib_mac_stats(struct ath_hal *ah); 1283extern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); 1284extern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); 1285extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); 1286extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); 1287extern u_int ar9300_get_def_antenna(struct ath_hal *ah); 1288extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); 1289extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, 1290 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 1291 u_int8_t *, u_int8_t *, u_int8_t *); 1292extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); 1293extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); 1294extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); 1295extern u_int ar9300_get_ack_timeout(struct ath_hal *); 1296extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 1297 u_int32_t next_start, HAL_QUIET_FLAG flag); 1298extern void ar9300_set_pcu_config(struct ath_hal *); 1299extern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1300 u_int32_t, u_int32_t *); 1301extern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1302 u_int32_t, u_int32_t, HAL_STATUS *); 1303extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, 1304 const void *args, u_int32_t argsize, 1305 void **result, u_int32_t *resultsize); 1306extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); 1307extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah); 1308extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); 1309extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); 1310extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); 1311extern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, 1312 int set_chip); 1313extern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); 1314extern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); 1315extern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); 1316 1317extern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); 1318 1319extern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 1320 u_int16_t assoc_id); 1321 1322 1323#if ATH_WOW 1324extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, 1325 u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); 1326//extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); 1327extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); 1328extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, 1329 HAL_BOOL offloadEnable); 1330#if ATH_WOW_OFFLOAD 1331/* ARP offload */ 1332#define WOW_OFFLOAD_ARP_INFO_MAX 2 1333 1334struct hal_wow_offload_arp_info { 1335 u_int32_t valid; 1336 u_int32_t id; 1337 1338 u_int32_t Flags; 1339 union { 1340 u_int8_t u8[4]; 1341 u_int32_t u32; 1342 } RemoteIPv4Address; 1343 union { 1344 u_int8_t u8[4]; 1345 u_int32_t u32; 1346 } HostIPv4Address; 1347 union { 1348 u_int8_t u8[6]; 1349 u_int32_t u32[2]; 1350 } MacAddress; 1351}; 1352 1353/* NS offload */ 1354#define WOW_OFFLOAD_NS_INFO_MAX 2 1355 1356struct hal_wow_offload_ns_info { 1357 u_int32_t valid; 1358 u_int32_t id; 1359 1360 u_int32_t Flags; 1361 union { 1362 u_int8_t u8[16]; 1363 u_int32_t u32[4]; 1364 } RemoteIPv6Address; 1365 union { 1366 u_int8_t u8[16]; 1367 u_int32_t u32[4]; 1368 } SolicitedNodeIPv6Address; 1369 union { 1370 u_int8_t u8[6]; 1371 u_int32_t u32[2]; 1372 } MacAddress; 1373 union { 1374 u_int8_t u8[16]; 1375 u_int32_t u32[4]; 1376 } TargetIPv6Addresses[2]; 1377}; 1378 1379extern void ar9300_wowoffload_prep(struct ath_hal *ah); 1380extern void ar9300_wowoffload_post(struct ath_hal *ah); 1381extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); 1382extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); 1383extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); 1384extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); 1385extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1386extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1387#endif /* ATH_WOW_OFFLOAD */ 1388#endif 1389 1390extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, 1391 struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, 1392 u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, 1393 HAL_BOOL b_channel_change, HAL_STATUS *status, HAL_RESET_TYPE reset_type, int is_scan); 1394extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, 1395 HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); 1396extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); 1397extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan); 1398extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); 1399extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); 1400extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); 1401extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); 1402extern HAL_BOOL ar9300_disable(struct ath_hal *ah); 1403extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *, HAL_RESET_TYPE type); 1404extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1405 u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); 1406extern void ar9300_reset_cal_valid(struct ath_hal *ah, 1407 const struct ieee80211_channel *chan, 1408 HAL_BOOL *isIQdone, u_int32_t cal_type); 1409extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); 1410extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); 1411extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); 1412extern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); 1413extern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); 1414extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); 1415 1416extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, 1417 u_int16_t extra_txpow, u_int16_t tpc_in_db); 1418extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, 1419 struct ieee80211_channel *chan, int is_scan); 1420extern int16_t ar9300_get_nf_from_reg(struct ath_hal *ah, struct ieee80211_channel *chan, int wait_time); 1421extern int ar9300_get_rx_nf_offset(struct ath_hal *ah, struct ieee80211_channel *chan, int8_t *nf_pwr, int8_t *nf_cal); 1422extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); 1423 1424extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); 1425extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); 1426extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, 1427 u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); 1428extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, 1429 const struct ieee80211_channel *chan, 1430 u_int8_t powerPerRate[], 1431 u_int8_t chainmask); 1432extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, 1433 u_int8_t powerPerRate[]); 1434extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, 1435 u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power); 1436 1437extern void ar9300_reset_tx_status_ring(struct ath_hal *ah); 1438extern void ar9300_enable_mib_counters(struct ath_hal *); 1439extern void ar9300_disable_mib_counters(struct ath_hal *); 1440extern void ar9300_ani_attach(struct ath_hal *); 1441extern void ar9300_ani_detach(struct ath_hal *); 1442extern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); 1443extern HAL_ANI_STATS *ar9300_ani_get_current_stats(struct ath_hal *); 1444extern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); 1445struct ath_rx_status; 1446 1447extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); 1448extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, 1449 const struct ieee80211_channel *, HAL_ANISTATS *); 1450extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); 1451extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); 1452extern void ar9300_enable_tpc(struct ath_hal *); 1453 1454extern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); 1455extern void ar9300_rx_gain_table_apply(struct ath_hal *ah); 1456extern void ar9300_tx_gain_table_apply(struct ath_hal *ah); 1457extern void ar9300_mat_enable(struct ath_hal *ah, int enable); 1458extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); 1459extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan); 1460 1461/* BB Panic Watchdog declarations */ 1462#define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ 1463#define HAL_BB_PANIC_WD_TMO_HORNET 85 1464extern void ar9300_config_bb_panic_watchdog(struct ath_hal *); 1465extern void ar9300_handle_bb_panic(struct ath_hal *); 1466extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); 1467extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); 1468extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); 1469 1470/* DFS declarations */ 1471extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan); 1472extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, 1473 u_int64_t nolTime); 1474extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1475extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1476extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan); 1477extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, 1478 u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, 1479 int *numb5radars, HAL_PHYERR_PARAM *pe); 1480extern HAL_BOOL ar9300_get_default_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1481extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); 1482extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); 1483extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); 1484extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); 1485 1486extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah); 1487extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); 1488 1489 1490extern void ar9300_mark_phy_inactive(struct ath_hal *ah); 1491 1492/* Spectral scan declarations */ 1493extern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1494extern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); 1495extern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1496extern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); 1497extern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); 1498extern void ar9300_start_spectral_scan(struct ath_hal *ah); 1499extern void ar9300_stop_spectral_scan(struct ath_hal *ah); 1500extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); 1501extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); 1502int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); 1503int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); 1504/* End spectral scan declarations */ 1505 1506/* Raw ADC capture functions */ 1507extern void ar9300_enable_test_addac_mode(struct ath_hal *ah); 1508extern void ar9300_disable_test_addac_mode(struct ath_hal *ah); 1509extern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); 1510extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); 1511extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); 1512extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); 1513 1514extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, 1515 struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); 1516extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); 1517 1518extern void ar9300_get_channel_centers(struct ath_hal *ah, 1519 const struct ieee80211_channel *chan, 1520 CHAN_CENTERS *centers); 1521extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, 1522 const struct ieee80211_channel *chan); 1523extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, 1524 const struct ieee80211_channel *chan); 1525extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); 1526 1527extern void ar9300_dma_reg_dump(struct ath_hal *); 1528extern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); 1529extern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); 1530extern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); 1531extern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); 1532extern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); 1533 1534#ifdef ATH_BT_COEX 1535extern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); 1536extern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); 1537extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); 1538extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1539extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); 1540extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); 1541extern void ar9300_bt_coex_disable(struct ath_hal *ah); 1542extern int ar9300_bt_coex_enable(struct ath_hal *ah); 1543extern void ar9300_init_bt_coex(struct ath_hal *ah); 1544extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); 1545extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); 1546#endif 1547extern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); 1548extern void ar9300_free_generic_timer(struct ath_hal *ah, int index); 1549extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, 1550 u_int32_t timer_period); 1551extern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); 1552extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, 1553 u_int32_t *thresh); 1554extern void ar9300_start_tsf2(struct ath_hal *ah); 1555 1556extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); 1557extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); 1558extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); 1559extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); 1560extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); 1561extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); 1562extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); 1563extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 1564 u_int32_t rssi_threshold); 1565extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); 1566extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); 1567extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, 1568 u_int8_t); 1569 1570extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); 1571extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); 1572extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); 1573extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *); 1574extern void ar9300_clear_mib_counters(struct ath_hal *ah); 1575 1576/* EEPROM interface functions */ 1577/* Common Interface functions */ 1578extern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); 1579extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); 1580 1581extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, 1582 ar9300_eeprom_t *p_eep_data, 1583 u_int32_t reg, 1584 u_int32_t val); 1585 1586extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, 1587 ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, 1588 u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, 1589 u_int16_t twice_max_regulatory_power, u_int16_t power_limit); 1590extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *); 1591extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); 1592extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *); 1593extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); 1594extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 1595extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); 1596 1597extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); 1598extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); 1599extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); 1600extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); 1601extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan, 1602 u_int8_t index, u_int16_t *config); 1603extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); 1604extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); 1605extern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); 1606extern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); 1607extern void ar9300_disp_tpc_tables(struct ath_hal *ah); 1608extern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); 1609extern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); 1610extern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); 1611 1612/* Common EEPROM Help function */ 1613extern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); 1614extern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); 1615 1616extern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); 1617 1618/* tx_bf interface */ 1619#define ar9300_init_txbf(ah) 1620#define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) 1621#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 1622#define ar9300_txbf_save_cv_from_compress( \ 1623 ah, key_idx, mimo_control, compress_rpt) \ 1624 false 1625#define ar9300_txbf_save_cv_from_non_compress( \ 1626 ah, key_idx, mimo_control, non_compress_rpt) \ 1627 false 1628#define ar9300_txbf_rc_update( \ 1629 ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ 1630 false 1631#define ar9300_fill_csi_frame( \ 1632 ah, rx_status, bandwidth, local_h, csi_frame_body) \ 1633 0 1634#define ar9300_fill_txbf_capabilities(ah) 1635#define ar9300_get_txbf_capabilities(ah) NULL 1636#define ar9300_txbf_set_key( \ 1637 ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) 1638#define ar9300_read_key_cache_mac(ah, entry, mac) false 1639#define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) 1640#define ar9300_set_selfgenrate_limit(ah, ts_ratecode) 1641#define ar9300_reset_lowest_txrate(ah) 1642#define ar9300_txbf_set_basic_set(ah) 1643 1644extern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); 1645extern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); 1646 1647 1648 1649#if ATH_SUPPORT_MCI 1650extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1651extern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); 1652extern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); 1653extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, 1654 void *gpm_buf, u_int16_t len, 1655 u_int32_t sched_addr); 1656extern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); 1657extern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); 1658extern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); 1659extern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, 1660 u_int32_t flag, u_int32_t *payload, u_int8_t len, 1661 HAL_BOOL wait_done, HAL_BOOL check_bt); 1662extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, 1663 u_int32_t *mci_int, 1664 u_int32_t *mci_int_rx_msg); 1665extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); 1666extern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); 1667extern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); 1668extern void ar9300_mci_mute_bt(struct ath_hal *ah); 1669extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); 1670extern void ar9300_mci_enable_interrupt(struct ath_hal *ah); 1671extern void ar9300_mci_disable_interrupt(struct ath_hal *ah); 1672extern void ar9300_mci_detach (struct ath_hal *ah); 1673extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); 1674extern void ar9300_mci_sync_bt_state (struct ath_hal *ah); 1675extern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); 1676extern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); 1677#if ATH_SUPPORT_AIC 1678extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); 1679extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); 1680#endif 1681#endif 1682 1683extern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); 1684 1685extern HAL_BOOL ar9300_regulatory_domain_override( 1686 struct ath_hal *ah, u_int16_t regdmn); 1687#if ATH_ANT_DIV_COMB 1688extern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1689extern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1690#endif /* ATH_ANT_DIV_COMB */ 1691extern void ar9300_disable_phy_restart(struct ath_hal *ah, 1692 int disable_phy_restart); 1693extern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); 1694extern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); 1695extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); 1696extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); 1697 1698#ifdef ATH_TX99_DIAG 1699#ifndef ATH_SUPPORT_HTC 1700extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower); 1701extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); 1702extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); 1703extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); 1704extern void ar9300_tx99_stop(struct ath_hal *ah); 1705#endif /* ATH_SUPPORT_HTC */ 1706#endif /* ATH_TX99_DIAG */ 1707extern HAL_BOOL ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array); 1708extern void ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask); 1709 1710enum { 1711 AR9300_COEFF_TX_TYPE = 0, 1712 AR9300_COEFF_RX_TYPE 1713}; 1714 1715#endif /* _ATH_AR9300_H_ */ 1716