1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22#ifdef AH_DEBUG 23#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24#endif 25 26#include "ar9300/ar9300.h" 27#include "ar9300/ar9300reg.h" 28#include "ar9300/ar9300phy.h" 29#include "ar9300/ar9300desc.h" 30 31static u_int32_t ar9300_read_loc_timer(struct ath_hal *ah); 32 33void 34ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 35{ 36 struct ath_hal_9300 *ahp = AH9300(ah); 37 *hangs = 0; 38 39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 40 *hangs |= HAL_RIFS_BB_HANG_WAR; 41 } 42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 43 *hangs |= HAL_DFS_BB_HANG_WAR; 44 } 45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 46 == HAL_OK) 47 { 48 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 49 } 50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 51 *hangs |= HAL_MAC_HANG_WAR; 52 } 53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 54 == HAL_OK) 55 { 56 *hangs |= HAL_PHYRESTART_CLR_WAR; 57 } 58 59 ahp->ah_hang_wars = *hangs; 60} 61 62/* 63 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 64 * HT20, HT40, fast-clock, turbo mode, etc. 65 */ 66static u_int 67ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 68{ 69#if 0 70 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 71 72 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 73 return (ath_hal_mac_usec(ah, clks) / 2); 74 } else { 75 return (ath_hal_mac_usec(ah, clks)); 76 } 77#endif 78 return (ath_hal_mac_usec(ah, clks)); 79} 80 81u_int 82ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 83{ 84#if 0 85 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 86 87 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 88 return (ath_hal_mac_clks(ah, usecs) * 2); 89 } else { 90 return (ath_hal_mac_clks(ah, usecs)); 91 } 92#endif 93 return (ath_hal_mac_clks(ah, usecs)); 94} 95 96void 97ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 98{ 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 101 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 102} 103 104HAL_BOOL 105ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 106{ 107 struct ath_hal_9300 *ahp = AH9300(ah); 108 109 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 110 return AH_TRUE; 111} 112 113void 114ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 115{ 116 struct ath_hal_9300 *ahp = AH9300(ah); 117 118 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 119} 120 121HAL_BOOL 122ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 123{ 124 struct ath_hal_9300 *ahp = AH9300(ah); 125 126 /* save it since it must be rewritten on reset */ 127 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 128 129 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 130 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 131 return AH_TRUE; 132} 133 134/* 135 * Attempt to change the cards operating regulatory domain to the given value 136 * Returns: A_EINVAL for an unsupported regulatory domain. 137 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 138 */ 139HAL_BOOL 140ar9300_set_regulatory_domain(struct ath_hal *ah, 141 u_int16_t reg_domain, HAL_STATUS *status) 142{ 143 HAL_STATUS ecode; 144 145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 146 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 147 return AH_TRUE; 148 } 149 ecode = HAL_EIO; 150 151#if 0 152bad: 153#endif 154 if (status) { 155 *status = ecode; 156 } 157 return AH_FALSE; 158} 159 160/* 161 * Return the wireless modes (a,b,g,t) supported by hardware. 162 * 163 * This value is what is actually supported by the hardware 164 * and is unaffected by regulatory/country code settings. 165 * 166 */ 167u_int 168ar9300_get_wireless_modes(struct ath_hal *ah) 169{ 170 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 171} 172 173/* 174 * Set the interrupt and GPIO values so the ISR can disable RF 175 * on a switch signal. Assumes GPIO port and interrupt polarity 176 * are set prior to call. 177 */ 178void 179ar9300_enable_rf_kill(struct ath_hal *ah) 180{ 181 /* TODO - can this really be above the hal on the GPIO interface for 182 * TODO - the client only? 183 */ 184 struct ath_hal_9300 *ahp = AH9300(ah); 185 186 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 187 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 188 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 189 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 190 AR_RFSILENT_FORCE); 191 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 192 } 193 else { 194 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 195 AR_RFSILENT_FORCE); 196 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 197 } 198 } 199 else { 200 /* Connect rfsilent_bb_l to baseband */ 201 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 202 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 203 204 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 205 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 AR_GPIO_INPUT_MUX2_RFSILENT); 207 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 208 (ahp->ah_gpio_select & 0x0f) << 4); 209 210 /* 211 * Configure the desired GPIO port for input and 212 * enable baseband rf silence 213 */ 214 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 215 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 216 } 217 218 /* 219 * If radio disable switch connection to GPIO bit x is enabled 220 * program GPIO interrupt. 221 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 222 * verified that it is a later version of eeprom, it has a place for 223 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 224 * connection is present. 225 */ 226 /* 227 * RFKill uses polling not interrupt, 228 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 229 */ 230 if (ath_hal_hasrfkill_int(ah)) { 231 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 232 /* switch already closed, set to interrupt upon open */ 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 234 } else { 235 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 236 } 237 } 238} 239 240/* 241 * Change the LED blinking pattern to correspond to the connectivity 242 */ 243void 244ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 245{ 246 static const u_int32_t ledbits[8] = { 247 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 250 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 251 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 252 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 253 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 254 AR_CFG_LED_ASSOC_NONE, 255 }; 256 257 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 258} 259 260/* 261 * Sets the Power LED on the cardbus without affecting the Network LED. 262 */ 263void 264ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 265{ 266 u_int32_t val; 267 268 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 269 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 270} 271 272/* 273 * Sets the Network LED on the cardbus without affecting the Power LED. 274 */ 275void 276ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 277{ 278 u_int32_t val; 279 280 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 281 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 282} 283 284/* 285 * Change association related fields programmed into the hardware. 286 * Writing a valid BSSID to the hardware effectively enables the hardware 287 * to synchronize its TSF to the correct beacons and receive frames coming 288 * from that BSSID. It is called by the SME JOIN operation. 289 */ 290void 291ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 292 u_int16_t assoc_id) 293{ 294 struct ath_hal_9300 *ahp = AH9300(ah); 295 296 /* save bssid and assoc_id for restore on reset */ 297 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 298 ahp->ah_assoc_id = assoc_id; 299 300 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 301 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 302 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 303} 304 305/* 306 * Get the current hardware tsf for stamlme 307 */ 308u_int64_t 309ar9300_get_tsf64(struct ath_hal *ah) 310{ 311 u_int64_t tsf; 312 313 /* XXX sync multi-word read? */ 314 tsf = OS_REG_READ(ah, AR_TSF_U32); 315 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 316 return tsf; 317} 318 319void 320ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 321{ 322 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 323 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 324} 325 326/* 327 * Get the current hardware tsf for stamlme 328 */ 329u_int32_t 330ar9300_get_tsf32(struct ath_hal *ah) 331{ 332 return OS_REG_READ(ah, AR_TSF_L32); 333} 334 335u_int32_t 336ar9300_get_tsf2_32(struct ath_hal *ah) 337{ 338 return OS_REG_READ(ah, AR_TSF2_L32); 339} 340 341/* 342 * Reset the current hardware tsf for stamlme. 343 */ 344void 345ar9300_reset_tsf(struct ath_hal *ah) 346{ 347 int count; 348 349 count = 0; 350 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 351 count++; 352 if (count > 10) { 353 HALDEBUG(ah, HAL_DEBUG_RESET, 354 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 355 break; 356 } 357 OS_DELAY(10); 358 } 359 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 360} 361 362/* 363 * Set or clear hardware basic rate bit 364 * Set hardware basic rate set if basic rate is found 365 * and basic rate is equal or less than 2Mbps 366 */ 367void 368ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 369{ 370 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 371 u_int32_t reg; 372 u_int8_t xset; 373 int i; 374 375 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 376 return; 377 } 378 xset = 0; 379 for (i = 0; i < rs->rs_count; i++) { 380 u_int8_t rset = rs->rs_rates[i]; 381 /* Basic rate defined? */ 382 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 383 xset = rset; 384 } 385 } 386 /* 387 * Set the h/w bit to reflect whether or not the basic 388 * rate is found to be equal or less than 2Mbps. 389 */ 390 reg = OS_REG_READ(ah, AR_STA_ID1); 391 if (xset && xset / 2 <= 2) { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 393 } else { 394 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 395 } 396} 397 398/* 399 * Grab a semi-random value from hardware registers - may not 400 * change often 401 */ 402u_int32_t 403ar9300_get_random_seed(struct ath_hal *ah) 404{ 405 u_int32_t nf; 406 407 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 408 if (nf & 0x100) { 409 nf = 0 - ((nf ^ 0x1ff) + 1); 410 } 411 return (OS_REG_READ(ah, AR_TSF_U32) ^ 412 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 413} 414 415/* 416 * Detect if our card is present 417 */ 418HAL_BOOL 419ar9300_detect_card_present(struct ath_hal *ah) 420{ 421 u_int16_t mac_version, mac_rev; 422 u_int32_t v; 423 424 /* 425 * Read the Silicon Revision register and compare that 426 * to what we read at attach time. If the same, we say 427 * a card/device is present. 428 */ 429 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 430 if (v == 0xFF) { 431 /* new SREV format */ 432 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 433 /* 434 * Include 6-bit Chip Type (masked to 0) to differentiate 435 * from pre-Sowl versions 436 */ 437 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 438 mac_rev = MS(v, AR_SREV_REVISION2); 439 } else { 440 mac_version = MS(v, AR_SREV_VERSION); 441 mac_rev = v & AR_SREV_REVISION; 442 } 443 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 444 AH_PRIVATE(ah)->ah_macRev == mac_rev); 445} 446 447/* 448 * Update MIB Counters 449 */ 450void 451ar9300_update_mib_mac_stats(struct ath_hal *ah) 452{ 453 struct ath_hal_9300 *ahp = AH9300(ah); 454 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 455 456 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 457 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 458 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 459 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 460 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 461} 462 463void 464ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 465{ 466 struct ath_hal_9300 *ahp = AH9300(ah); 467 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 468 469 stats->ackrcv_bad = istats->ackrcv_bad; 470 stats->rts_bad = istats->rts_bad; 471 stats->fcs_bad = istats->fcs_bad; 472 stats->rts_good = istats->rts_good; 473 stats->beacons = istats->beacons; 474} 475 476/* 477 * Detect if the HW supports spreading a CCK signal on channel 14 478 */ 479HAL_BOOL 480ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 481{ 482 return AH_TRUE; 483} 484 485/* 486 * Get the rssi of frame curently being received. 487 */ 488u_int32_t 489ar9300_get_cur_rssi(struct ath_hal *ah) 490{ 491 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 492 /* get combined RSSI */ 493 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 494} 495 496#if ATH_GEN_RANDOMNESS 497/* 498 * Get the rssi value from BB on ctl chain0. 499 */ 500u_int32_t 501ar9300_get_rssi_chain0(struct ath_hal *ah) 502{ 503 /* get ctl chain0 RSSI */ 504 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 505} 506#endif 507 508u_int 509ar9300_get_def_antenna(struct ath_hal *ah) 510{ 511 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 512} 513 514/* Setup coverage class */ 515void 516ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 517{ 518} 519 520void 521ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 522{ 523 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 524} 525 526HAL_BOOL 527ar9300_set_antenna_switch(struct ath_hal *ah, 528 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 529 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 530{ 531 struct ath_hal_9300 *ahp = AH9300(ah); 532 533 /* 534 * Owl does not support diversity or changing antennas. 535 * 536 * Instead this API and function are defined differently for AR9300. 537 * To support Tablet PC's, this interface allows the system 538 * to dramatically reduce the TX power on a particular chain. 539 * 540 * Based on the value of (redefined) diversity_control, the 541 * reset code will decrease power on chain 0 or chain 1/2. 542 * 543 * Based on the value of bit 0 of antenna_switch_swap, 544 * the mapping between OID call and chain is defined as: 545 * 0: map A -> 0, B -> 1; 546 * 1: map A -> 1, B -> 0; 547 * 548 * NOTE: 549 * The devices that use this OID should use a tx_chain_mask and 550 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 551 * used in order to ensure an active transmit antenna. This 552 * API will allow the host to turn off the only transmitting 553 * antenna to ensure the antenna closest to the user's body is 554 * powered-down. 555 */ 556 /* 557 * Set antenna control for use during reset sequence by 558 * ar9300_decrease_chain_power() 559 */ 560 ahp->ah_diversity_control = settings; 561 562 return AH_TRUE; 563} 564 565HAL_BOOL 566ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 567{ 568 return AH_TRUE; 569} 570 571HAL_BOOL 572ar9300_set_slot_time(struct ath_hal *ah, u_int us) 573{ 574 struct ath_hal_9300 *ahp = AH9300(ah); 575 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 576 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 577 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 578 return AH_FALSE; 579 } else { 580 /* convert to system clocks */ 581 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 582 ahp->ah_slot_time = us; 583 return AH_TRUE; 584 } 585} 586 587HAL_BOOL 588ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 589{ 590 struct ath_hal_9300 *ahp = AH9300(ah); 591 592 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 593 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 594 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 595 return AH_FALSE; 596 } else { 597 /* convert to system clocks */ 598 OS_REG_RMW_FIELD(ah, 599 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 600 ahp->ah_ack_timeout = us; 601 return AH_TRUE; 602 } 603} 604 605u_int 606ar9300_get_ack_timeout(struct ath_hal *ah) 607{ 608 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 609 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 610} 611 612HAL_STATUS 613ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 614 u_int32_t next_start, HAL_QUIET_FLAG flag) 615{ 616#define TU_TO_USEC(_tu) ((_tu) << 10) 617 HAL_STATUS status = HAL_EIO; 618 u_int32_t tsf = 0, j, next_start_us = 0; 619 if (flag & HAL_QUIET_ENABLE) { 620 for (j = 0; j < 2; j++) { 621 next_start_us = TU_TO_USEC(next_start); 622 tsf = OS_REG_READ(ah, AR_TSF_L32); 623 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 624 next_start_us += tsf; 625 } 626 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 627 next_start_us += 628 ah->ah_config.ah_sw_beacon_response_time; 629 } 630 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 631 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 632 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 633 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 634 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 635 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 636 status = HAL_OK; 637 break; 638 } 639 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 640 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 641 /* TSF shouldn't count twice or reg access is taking forever */ 642 HALASSERT(j < 1); 643 } 644 } else { 645 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 646 status = HAL_OK; 647 } 648 649 return status; 650#undef TU_TO_USEC 651} 652 653//#ifdef ATH_SUPPORT_DFS 654void 655ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 656{ 657 uint32_t reg1, reg2; 658 659 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 660 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 661 AH9300(ah)->ah_cac_quiet_enabled = enable; 662 663 if (enable) { 664 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 665 reg1 | AR_PCU_FORCE_QUIET_COLL); 666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 667 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 668 } else { 669 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 670 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 671 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 672 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 673 } 674} 675//#endif /* ATH_SUPPORT_DFS */ 676 677void 678ar9300_set_pcu_config(struct ath_hal *ah) 679{ 680 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 681} 682 683HAL_STATUS 684ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 685 u_int32_t capability, u_int32_t *result) 686{ 687 struct ath_hal_9300 *ahp = AH9300(ah); 688 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 689 struct ar9300_ani_state *ani; 690 691 switch (type) { 692 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 693 switch (capability) { 694 case HAL_CIPHER_AES_CCM: 695 case HAL_CIPHER_AES_OCB: 696 case HAL_CIPHER_TKIP: 697 case HAL_CIPHER_WEP: 698 case HAL_CIPHER_MIC: 699 case HAL_CIPHER_CLR: 700 return HAL_OK; 701 default: 702 return HAL_ENOTSUPP; 703 } 704 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 705 switch (capability) { 706 case 0: /* hardware capability */ 707 return HAL_OK; 708 case 1: 709 return (ahp->ah_sta_id1_defaults & 710 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 711 default: 712 return HAL_ENOTSUPP; 713 } 714 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 715 switch (capability) { 716 case 0: /* hardware capability */ 717 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 718 case 1: /* current setting */ 719 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 720 HAL_ENXIO : HAL_OK; 721 default: 722 return HAL_ENOTSUPP; 723 } 724 case HAL_CAP_WME_TKIPMIC: 725 /* hardware can do TKIP MIC when WMM is turned on */ 726 return HAL_OK; 727 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 728 return HAL_OK; 729 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 730 switch (capability) { 731 case 0: /* hardware capability */ 732 return HAL_OK; 733 case 1: /* current setting */ 734 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 735 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 736 HAL_OK : HAL_ENXIO; 737 } 738 return HAL_EINVAL; 739 case HAL_CAP_TPC: 740 switch (capability) { 741 case 0: /* hardware capability */ 742 return HAL_OK; 743 case 1: 744 return ah->ah_config.ath_hal_desc_tpc ? 745 HAL_OK : HAL_ENXIO; 746 } 747 return HAL_OK; 748 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 749 return HAL_OK; 750 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 751 switch (capability) { 752 case 0: /* hardware capability */ 753 return HAL_OK; 754 case 1: 755 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 756 /* 757 * Owl and Merlin have problems in mcast key search. 758 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 759 * 26802 760 */ 761 return HAL_ENXIO; 762 } else { 763 return (ahp->ah_sta_id1_defaults & 764 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 765 } 766 } 767 return HAL_EINVAL; 768 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 769 switch (capability) { 770 case 0: /* hardware capability */ 771 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 772 case 1: 773 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 774 HAL_OK : HAL_ENXIO; 775 } 776 return HAL_EINVAL; 777 case HAL_CAP_RFSILENT: /* rfsilent support */ 778 if (capability == 3) { /* rfkill interrupt */ 779 /* 780 * XXX: Interrupt-based notification of RF Kill state 781 * changes not working yet. Report that this feature 782 * is not supported so that polling is used instead. 783 */ 784 return (HAL_ENOTSUPP); 785 } 786 return ath_hal_getcapability(ah, type, capability, result); 787 case HAL_CAP_4ADDR_AGGR: 788 return HAL_OK; 789 case HAL_CAP_BB_RIFS_HANG: 790 return HAL_ENOTSUPP; 791 case HAL_CAP_BB_DFS_HANG: 792 return HAL_ENOTSUPP; 793 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 794 /* Track chips that are known to have BB hangs related 795 * to rx_clear stuck low. 796 */ 797 return HAL_ENOTSUPP; 798 case HAL_CAP_MAC_HANG: 799 /* Track chips that are known to have MAC hangs. 800 */ 801 return HAL_OK; 802 case HAL_CAP_RIFS_RX_ENABLED: 803 /* Is RIFS RX currently enabled */ 804 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 805#if 0 806 case HAL_CAP_ANT_CFG_2GHZ: 807 *result = p_cap->halNumAntCfg2Ghz; 808 return HAL_OK; 809 case HAL_CAP_ANT_CFG_5GHZ: 810 *result = p_cap->halNumAntCfg5Ghz; 811 return HAL_OK; 812 case HAL_CAP_RX_STBC: 813 *result = p_cap->hal_rx_stbc_support; 814 return HAL_OK; 815 case HAL_CAP_TX_STBC: 816 *result = p_cap->hal_tx_stbc_support; 817 return HAL_OK; 818#endif 819 case HAL_CAP_LDPC: 820 *result = p_cap->halLDPCSupport; 821 return HAL_OK; 822 case HAL_CAP_DYNAMIC_SMPS: 823 return HAL_OK; 824 case HAL_CAP_DS: 825 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 826 (p_cap->halTxChainMask & 0x3) != 0x3 || 827 (p_cap->halRxChainMask & 0x3) != 0x3) ? 828 HAL_ENOTSUPP : HAL_OK; 829 case HAL_CAP_TS: 830 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 831 (p_cap->halTxChainMask & 0x7) != 0x7 || 832 (p_cap->halRxChainMask & 0x7) != 0x7) ? 833 HAL_ENOTSUPP : HAL_OK; 834 case HAL_CAP_OL_PWRCTRL: 835 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 836 HAL_OK : HAL_ENOTSUPP; 837 case HAL_CAP_CRDC: 838#if ATH_SUPPORT_CRDC 839 return (AR_SREV_WASP(ah) && 840 ah->ah_config.ath_hal_crdc_enable) ? 841 HAL_OK : HAL_ENOTSUPP; 842#else 843 return HAL_ENOTSUPP; 844#endif 845#if 0 846 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 847 *result = (u_int32_t)(-1); 848 return HAL_OK; 849 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 850 *result = (u_int32_t)(-1); 851 return HAL_OK; 852#endif 853 case HAL_CAP_BB_PANIC_WATCHDOG: 854 return HAL_OK; 855 case HAL_CAP_PHYRESTART_CLR_WAR: 856 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 857 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 858 { 859 return HAL_OK; 860 } 861 else 862 { 863 return HAL_ENOTSUPP; 864 } 865 case HAL_CAP_ENTERPRISE_MODE: 866 *result = ahp->ah_enterprise_mode >> 16; 867 /* 868 * WAR for EV 77658 - Add delimiters to first sub-frame when using 869 * RTS/CTS with aggregation and non-enterprise Osprey. 870 * 871 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 872 */ 873 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 874 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 875 AR_SREV_WASP_10(ah))) { 876 *result |= AH_ENT_RTSCTS_DELIM_WAR; 877 } 878 return HAL_OK; 879 case HAL_CAP_LDPCWAR: 880 /* WAR for RIFS+LDPC issue is required for all chips currently 881 * supported by ar9300 HAL. 882 */ 883 return HAL_OK; 884 case HAL_CAP_ENABLE_APM: 885 *result = p_cap->halApmEnable; 886 return HAL_OK; 887 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 888 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 889 case HAL_CAP_PCIE_LCR_OFFSET: 890 *result = p_cap->hal_pcie_lcr_offset; 891 return HAL_OK; 892 case HAL_CAP_SMARTANTENNA: 893 /* FIXME A request is pending with h/w team to add feature bit in 894 * caldata to detect if board has smart antenna or not, once added 895 * we need to fix his piece of code to read and return value without 896 * any compile flags 897 */ 898#if UMAC_SUPPORT_SMARTANTENNA 899 /* enable smart antenna for Peacock, Wasp and scorpion 900 for future chips need to modify */ 901 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 902 return HAL_OK; 903 } else { 904 return HAL_ENOTSUPP; 905 } 906#else 907 return HAL_ENOTSUPP; 908#endif 909 910#ifdef ATH_TRAFFIC_FAST_RECOVER 911 case HAL_CAP_TRAFFIC_FAST_RECOVER: 912 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 913 return HAL_OK; 914 } else { 915 return HAL_ENOTSUPP; 916 } 917#endif 918 919 /* FreeBSD ANI */ 920 case HAL_CAP_INTMIT: /* interference mitigation */ 921 switch (capability) { 922 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 923 return HAL_OK; 924 case HAL_CAP_INTMIT_ENABLE: 925 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 926 HAL_OK : HAL_ENXIO; 927 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 928 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 929// case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 930 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 931 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 932 ani = ar9300_ani_get_current_state(ah); 933 if (ani == AH_NULL) 934 return HAL_ENXIO; 935 switch (capability) { 936 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 937 case 2: *result = ani->ofdm_noise_immunity_level; break; 938 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 939 // case 4: *result = ani->cck_weak_sig_threshold; break; 940 case 5: *result = ani->firstep_level; break; 941 case 6: *result = ani->spur_immunity_level; break; 942 } 943 return HAL_OK; 944 } 945 return HAL_EINVAL; 946 case HAL_CAP_ENFORCE_TXOP: 947 if (capability == 0) 948 return (HAL_OK); 949 if (capability != 1) 950 return (HAL_ENOTSUPP); 951 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA); 952 return (HAL_OK); 953 case HAL_CAP_TOA_LOCATIONING: 954 if (capability == 0) 955 return HAL_OK; 956 if (capability == 2) { 957 *result = ar9300_read_loc_timer(ah); 958 return (HAL_OK); 959 } 960 return HAL_ENOTSUPP; 961 default: 962 return ath_hal_getcapability(ah, type, capability, result); 963 } 964} 965 966HAL_BOOL 967ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 968 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 969{ 970 struct ath_hal_9300 *ahp = AH9300(ah); 971 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 972 u_int32_t v; 973 974 switch (type) { 975 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 976 if (! p_cap->halTkipMicTxRxKeySupport) 977 return AH_FALSE; 978 979 if (setting) 980 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 981 else 982 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 983 984 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 985 return AH_TRUE; 986 987 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 988 if (setting) { 989 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 990 } else { 991 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 992 } 993 return AH_TRUE; 994 case HAL_CAP_DIVERSITY: 995 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 996 if (setting) { 997 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 998 } else { 999 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 1000 } 1001 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 1002 return AH_TRUE; 1003 case HAL_CAP_DIAG: /* hardware diagnostic support */ 1004 /* 1005 * NB: could split this up into virtual capabilities, 1006 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 1007 * seems worth the additional complexity. 1008 */ 1009#ifdef AH_DEBUG 1010 AH_PRIVATE(ah)->ah_diagreg = setting; 1011#else 1012 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 1013#endif 1014 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 1015 return AH_TRUE; 1016 case HAL_CAP_TPC: 1017 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1018 return AH_TRUE; 1019 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1020 if (setting) { 1021 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1022 } else { 1023 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1024 } 1025 return AH_TRUE; 1026 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1027 if (p_cap->halTsfAddSupport) { 1028 if (setting) { 1029 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1030 } else { 1031 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1032 } 1033 return AH_TRUE; 1034 } 1035 return AH_FALSE; 1036 1037 /* FreeBSD interrupt mitigation / ANI */ 1038 case HAL_CAP_INTMIT: { /* interference mitigation */ 1039 /* This maps the public ANI commands to the internal ANI commands */ 1040 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1041 static const HAL_ANI_CMD cmds[] = { 1042 HAL_ANI_PRESENT, 1043 HAL_ANI_MODE, 1044 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1045 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1046 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1047 HAL_ANI_FIRSTEP_LEVEL, 1048 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1049 }; 1050#define N(a) (sizeof(a) / sizeof(a[0])) 1051 return capability < N(cmds) ? 1052 ar9300_ani_control(ah, cmds[capability], setting) : 1053 AH_FALSE; 1054#undef N 1055 } 1056 1057 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1058 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1059 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1060 return AH_TRUE; 1061 1062 case HAL_CAP_ENFORCE_TXOP: 1063 if (capability != 1) 1064 return AH_FALSE; 1065 if (setting) { 1066 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA; 1067 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1068 } else { 1069 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA; 1070 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1071 } 1072 return AH_TRUE; 1073 1074 case HAL_CAP_TOA_LOCATIONING: 1075 if (capability == 0) 1076 return AH_TRUE; 1077 if (capability == 1) { 1078 ar9300_update_loc_ctl_reg(ah, setting); 1079 return AH_TRUE; 1080 } 1081 return AH_FALSE; 1082 /* fall thru... */ 1083 default: 1084 return ath_hal_setcapability(ah, type, capability, setting, status); 1085 } 1086} 1087 1088#ifdef AH_DEBUG 1089static void 1090ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1091{ 1092 u_int32_t i = 0; 1093 1094 /* Read 0x80d0 to trigger pcie analyzer */ 1095 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1096 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1097 1098 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1099 struct ath_hal_9300 *ahp = AH9300(ah); 1100 u_int32_t tf, rf, rc, cc; 1101 1102 tf = OS_REG_READ(ah, AR_TFCNT); 1103 rf = OS_REG_READ(ah, AR_RFCNT); 1104 rc = OS_REG_READ(ah, AR_RCCNT); 1105 cc = OS_REG_READ(ah, AR_CCCNT); 1106 1107 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1108 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1109 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1110 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1111 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1112 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1113 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1114 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1115 1116 ahp->last_tf = tf; 1117 ahp->last_rf = rf; 1118 ahp->last_rc = rc; 1119 ahp->last_cc = cc; 1120 1121 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1122 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1123 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1124 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1125 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1126 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1127 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1128 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1129 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1130 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1131 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1132 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1133 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1134 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1135 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1136 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1137 } 1138 1139 if (args & HAL_DIAG_PRINT_REG_ALL) { 1140 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1141 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1142 i, OS_REG_READ(ah, i)); 1143 } 1144 1145 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1146 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1147 i, OS_REG_READ(ah, i)); 1148 } 1149 1150 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1151 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1152 1153 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1154 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1155 1156 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1157 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1158 i, OS_REG_READ(ah, i)); 1159 } 1160 1161 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1162 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1163 i, OS_REG_READ(ah, i)); 1164 } 1165 1166 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1167 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1168 i, OS_REG_READ(ah, i)); 1169 } 1170 1171 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1172 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1173 i, OS_REG_READ(ah, i)); 1174 } 1175 1176 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1177 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1178 i, OS_REG_READ(ah, i)); 1179 } 1180 1181 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1182 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1183 i, OS_REG_READ(ah, i)); 1184 } 1185 1186 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1187 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1188 i, OS_REG_READ(ah, i)); 1189 } 1190 1191 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1192 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1193 i, OS_REG_READ(ah, i)); 1194 } 1195 1196 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1197 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1198 i, OS_REG_READ(ah, i)); 1199 } 1200 1201 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1202 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1203 i, OS_REG_READ(ah, i)); 1204 } 1205 1206 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1207 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1208 i, OS_REG_READ(ah, i)); 1209 } 1210 } 1211} 1212#endif 1213 1214HAL_BOOL 1215ar9300_get_diag_state(struct ath_hal *ah, int request, 1216 const void *args, u_int32_t argsize, 1217 void **result, u_int32_t *resultsize) 1218{ 1219 struct ath_hal_9300 *ahp = AH9300(ah); 1220 struct ar9300_ani_state *ani; 1221 1222 (void) ahp; 1223 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1224 return AH_TRUE; 1225 } 1226 switch (request) { 1227#ifdef AH_PRIVATE_DIAG 1228 case HAL_DIAG_EEPROM: 1229 *result = &ahp->ah_eeprom; 1230 *resultsize = sizeof(ar9300_eeprom_t); 1231 return AH_TRUE; 1232 1233#if 0 /* XXX - TODO */ 1234 case HAL_DIAG_EEPROM_EXP_11A: 1235 case HAL_DIAG_EEPROM_EXP_11B: 1236 case HAL_DIAG_EEPROM_EXP_11G: 1237 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1238 *result = pe->p_channels; 1239 *resultsize = (*result == AH_NULL) ? 0 : 1240 roundup(sizeof(u_int16_t) * pe->num_channels, 1241 sizeof(u_int32_t)) + 1242 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1243 return AH_TRUE; 1244#endif 1245 case HAL_DIAG_RFGAIN: 1246 *result = &ahp->ah_gain_values; 1247 *resultsize = sizeof(GAIN_VALUES); 1248 return AH_TRUE; 1249 case HAL_DIAG_RFGAIN_CURSTEP: 1250 *result = (void *) ahp->ah_gain_values.curr_step; 1251 *resultsize = (*result == AH_NULL) ? 1252 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1253 return AH_TRUE; 1254#if 0 /* XXX - TODO */ 1255 case HAL_DIAG_PCDAC: 1256 *result = ahp->ah_pcdac_table; 1257 *resultsize = ahp->ah_pcdac_table_size; 1258 return AH_TRUE; 1259#endif 1260 case HAL_DIAG_ANI_CURRENT: 1261 1262 ani = ar9300_ani_get_current_state(ah); 1263 if (ani == AH_NULL) 1264 return AH_FALSE; 1265 /* Convert ar9300 HAL to FreeBSD HAL ANI state */ 1266 /* XXX TODO: add all of these to the HAL ANI state structure */ 1267 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state)); 1268 /* XXX should this be OFDM or CCK noise immunity level? */ 1269 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level; 1270 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level; 1271 ahp->ext_ani_state.firstepLevel = ani->firstep_level; 1272 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off; 1273 /* mrc_cck_off */ 1274 /* cck_noise_immunity_level */ 1275 1276 ahp->ext_ani_state.listenTime = ani->listen_time; 1277 1278 *result = &ahp->ext_ani_state; 1279 *resultsize = sizeof(ahp->ext_ani_state); 1280#if 0 1281 *result = ar9300_ani_get_current_state(ah); 1282 *resultsize = (*result == AH_NULL) ? 1283 0 : sizeof(struct ar9300_ani_state); 1284#endif 1285 return AH_TRUE; 1286 case HAL_DIAG_ANI_STATS: 1287 *result = ar9300_ani_get_current_stats(ah); 1288 *resultsize = (*result == AH_NULL) ? 1289 0 : sizeof(HAL_ANI_STATS); 1290 return AH_TRUE; 1291 case HAL_DIAG_ANI_CMD: 1292 if (argsize != 2*sizeof(u_int32_t)) { 1293 return AH_FALSE; 1294 } 1295 ar9300_ani_control( 1296 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1297 return AH_TRUE; 1298#if 0 1299 case HAL_DIAG_TXCONT: 1300 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1301 return AH_TRUE; 1302#endif /* 0 */ 1303#endif /* AH_PRIVATE_DIAG */ 1304 case HAL_DIAG_CHANNELS: 1305#if 0 1306 *result = &(ahp->ah_priv.ah_channels[0]); 1307 *resultsize = 1308 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1309#endif 1310 return AH_TRUE; 1311#ifdef AH_DEBUG 1312 case HAL_DIAG_PRINT_REG: 1313 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1314 return AH_TRUE; 1315#endif 1316 default: 1317 break; 1318 } 1319 1320 return AH_FALSE; 1321} 1322 1323void 1324ar9300_dma_reg_dump(struct ath_hal *ah) 1325{ 1326#ifdef AH_DEBUG 1327#define NUM_DMA_DEBUG_REGS 8 1328#define NUM_QUEUES 10 1329 1330 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1331 int qcu_offset = 0, dcu_offset = 0; 1332 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1333 int i, j, k; 1334 int16_t nfarray[HAL_NUM_NF_READINGS]; 1335#ifdef ATH_NF_PER_CHAN 1336 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1337#endif /* ATH_NF_PER_CHAN */ 1338 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1339 1340 /* selecting DMA OBS 8 */ 1341 OS_REG_WRITE(ah, AR_MACMISC, 1342 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1343 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1344 1345 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1346 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1347 if (i % 4 == 0) { 1348 ath_hal_printf(ah, "\n"); 1349 } 1350 1351 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1352 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1353 } 1354 1355 ath_hal_printf(ah, "\n\n"); 1356 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1357 1358 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1359 if (i == 8) { 1360 /* only 8 QCU entries in val[0] */ 1361 qcu_offset = 0; 1362 qcu_base++; 1363 } 1364 1365 if (i == 6) { 1366 /* only 6 DCU entries in val[4] */ 1367 dcu_offset = 0; 1368 dcu_base++; 1369 } 1370 1371 ath_hal_printf(ah, 1372 "%2d %2x %1x %2x %2x\n", 1373 i, 1374 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1375 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1376 val[2] & (0x7 << (i * 3)) >> (i * 3), 1377 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1378 } 1379 1380 ath_hal_printf(ah, "\n"); 1381 ath_hal_printf(ah, 1382 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1383 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1384 ath_hal_printf(ah, 1385 "qcu_complete state: %2x dcu_complete state: %2x\n", 1386 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1387 ath_hal_printf(ah, 1388 "dcu_arb state: %2x dcu_fp state: %2x\n", 1389 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1390 ath_hal_printf(ah, 1391 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1392 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1393 ath_hal_printf(ah, 1394 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1395 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1396 ath_hal_printf(ah, 1397 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1398 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1399 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1400 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1401 1402 ar9300_upload_noise_floor(ah, 1, nfarray); 1403 ath_hal_printf(ah, "2G:\n"); 1404 ath_hal_printf(ah, "Min CCA Out:\n"); 1405 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1406 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1407 nfarray[0], nfarray[1], nfarray[2]); 1408 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1409 nfarray[3], nfarray[4], nfarray[5]); 1410 1411 ar9300_upload_noise_floor(ah, 0, nfarray); 1412 ath_hal_printf(ah, "5G:\n"); 1413 ath_hal_printf(ah, "Min CCA Out:\n"); 1414 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1415 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1416 nfarray[0], nfarray[1], nfarray[2]); 1417 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1418 nfarray[3], nfarray[4], nfarray[5]); 1419 1420 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1421 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1422 ((i < 3) ? "Control " : "Extension "), i%3); 1423 for (j = 0, k = h->base.curr_index; 1424 j < HAL_NF_CAL_HIST_LEN_FULL; 1425 j++, k++) { 1426 ath_hal_printf(ah, "Element %d: %d\n", 1427 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1428 } 1429 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1430 } 1431 1432 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1433 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1434 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1435 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1436 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1437 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1438 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1439 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1440 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1441 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1442 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1443 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1444 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1445 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1446 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1447 reg = OS_REG_READ(ah, AR_PHY_AGC); 1448 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1449 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1450 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1451 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1452 MS(reg, AR_PHY_AGC_COARSE_LOW), 1453 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1454 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1455 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1456 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1457 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1458 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1459 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1460 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1461 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1462 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1463 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1464 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1465 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1466 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1467 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1468 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1469 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1470 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1471 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1472 1473 1474 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1475 reg = OS_REG_READ(ah, 0xa360); 1476 reg &= ~0x00800000; 1477 OS_REG_WRITE(ah, 0xa360, reg); 1478 1479 /* Step 2a: Set register 0xa364 to 0x1000 */ 1480 reg = 0x1000; 1481 OS_REG_WRITE(ah, 0xa364, reg); 1482 1483 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1484 reg = OS_REG_READ(ah, 0x9c20); 1485 reg &= 0x0003ffff; 1486 ath_hal_printf(ah, 1487 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1488 __func__, reg); 1489 1490 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1491 reg = OS_REG_READ(ah, 0xa360); 1492 reg &= ~0x00800000; 1493 OS_REG_WRITE(ah, 0xa360, reg); 1494 1495 /* Step 2b: Set register 0xa364 to 0x1400 */ 1496 reg = 0x1400; 1497 OS_REG_WRITE(ah, 0xa364, reg); 1498 1499 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1500 reg = OS_REG_READ(ah, 0x9c20); 1501 reg &= 0x0003ffff; 1502 ath_hal_printf(ah, 1503 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1504 __func__, reg); 1505 1506 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1507 reg = OS_REG_READ(ah, 0xa360); 1508 reg &= ~0x00800000; 1509 OS_REG_WRITE(ah, 0xa360, reg); 1510 1511 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1512 reg = 0x3c00; 1513 OS_REG_WRITE(ah, 0xa364, reg); 1514 1515 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1516 reg = OS_REG_READ(ah, 0x9c20); 1517 reg &= 0x0003ffff; 1518 ath_hal_printf(ah, 1519 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1520 __func__, reg); 1521 1522 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1523 reg = OS_REG_READ(ah, 0xa360); 1524 reg &= ~0x001040000; 1525 OS_REG_WRITE(ah, 0xa360, reg); 1526 1527 /* Step 2d: Set register 0xa364 to 0x5005D */ 1528 reg = 0x5005D; 1529 OS_REG_WRITE(ah, 0xa364, reg); 1530 1531 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1532 reg = OS_REG_READ(ah, 0xa368); 1533 reg &= 0x0003ffff; 1534 ath_hal_printf(ah, 1535 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1536 __func__, reg); 1537 1538 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1539 reg = OS_REG_READ(ah, 0xa360); 1540 reg &= ~0x001040000; 1541 OS_REG_WRITE(ah, 0xa360, reg); 1542 1543 /* Step 2e: Set register 0xa364 to 0x7005D */ 1544 reg = 0x7005D; 1545 OS_REG_WRITE(ah, 0xa364, reg); 1546 1547 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1548 reg = OS_REG_READ(ah, 0xa368); 1549 reg &= 0x0003ffff; 1550 ath_hal_printf(ah, 1551 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1552 __func__, reg); 1553 1554 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1555 reg = OS_REG_READ(ah, 0xa360); 1556 reg &= ~0x001000000; 1557 reg |= 0x40000; 1558 OS_REG_WRITE(ah, 0xa360, reg); 1559 1560 /* Step 2f: Set register 0xa364 to 0x3005D */ 1561 reg = 0x3005D; 1562 OS_REG_WRITE(ah, 0xa364, reg); 1563 1564 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1565 reg = OS_REG_READ(ah, 0xa368); 1566 reg &= 0x0003ffff; 1567 ath_hal_printf(ah, 1568 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1569 __func__, reg); 1570 1571 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1572 reg = OS_REG_READ(ah, 0xa360); 1573 reg &= ~0x001000000; 1574 reg |= 0x40000; 1575 OS_REG_WRITE(ah, 0xa360, reg); 1576 1577 /* Step 2g: Set register 0xa364 to 0x6005D */ 1578 reg = 0x6005D; 1579 OS_REG_WRITE(ah, 0xa364, reg); 1580 1581 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1582 reg = OS_REG_READ(ah, 0xa368); 1583 reg &= 0x0003ffff; 1584 ath_hal_printf(ah, 1585 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1586 __func__, reg); 1587#endif /* AH_DEBUG */ 1588} 1589 1590/* 1591 * Return the busy for rx_frame, rx_clear, and tx_frame 1592 */ 1593u_int32_t 1594ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1595 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1596{ 1597 struct ath_hal_9300 *ahp = AH9300(ah); 1598 u_int32_t good = 1; 1599 1600 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1601 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1602 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1603 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1604 1605 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1606 /* 1607 * Cycle counter wrap (or initial call); it's not possible 1608 * to accurately calculate a value because the registers 1609 * right shift rather than wrap--so punt and return 0. 1610 */ 1611 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1612 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1613 good = 0; 1614 } else { 1615 u_int32_t cc_d = cc - ahp->ah_cycles; 1616 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1617 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1618 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1619 1620 if (cc_d != 0) { 1621 *rxc_pcnt = rc_d * 100 / cc_d; 1622 *rxf_pcnt = rf_d * 100 / cc_d; 1623 *txf_pcnt = tf_d * 100 / cc_d; 1624 } else { 1625 good = 0; 1626 } 1627 } 1628 1629 ahp->ah_cycles = cc; 1630 ahp->ah_rx_frame = rf; 1631 ahp->ah_rx_clear = rc; 1632 ahp->ah_tx_frame = tf; 1633 1634 return good; 1635} 1636 1637/* 1638 * Return approximation of extension channel busy over an time interval 1639 * 0% (clear) -> 100% (busy) 1640 * -1 for invalid estimate 1641 */ 1642uint32_t 1643ar9300_get_11n_ext_busy(struct ath_hal *ah) 1644{ 1645 /* 1646 * Overflow condition to check before multiplying to get % 1647 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1648 */ 1649#define OVERFLOW_LIMIT 0x28F5C28 1650#define ERROR_CODE -1 1651 1652 struct ath_hal_9300 *ahp = AH9300(ah); 1653 u_int32_t busy = 0; /* percentage */ 1654 int8_t busyper = 0; 1655 u_int32_t cycle_count, ctl_busy, ext_busy; 1656 1657 /* cycle_count will always be the first to wrap; therefore, read it last 1658 * This sequence of reads is not atomic, and MIB counter wrap 1659 * could happen during it ? 1660 */ 1661 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1662 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1663 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1664 1665 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1666 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1667 { 1668 /* 1669 * Cycle counter wrap (or initial call); it's not possible 1670 * to accurately calculate a value because the registers 1671 * right shift rather than wrap--so punt and return 0. 1672 */ 1673 busyper = ERROR_CODE; 1674 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1675 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1676 } else { 1677 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1678 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1679 1680 /* 1681 * Compute extension channel busy percentage 1682 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1683 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1684 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1685 * and shift necessitated by large ext_busy_delta. 1686 * Due to timing difference to read the registers and counter overflow, 1687 * it may still happen that cycle_delta >> 7 = 0. 1688 * 1689 */ 1690 if (cycle_delta) { 1691 if (ext_busy_delta > OVERFLOW_LIMIT) { 1692 if (cycle_delta >> 7) { 1693 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1694 } else { 1695 busyper = ERROR_CODE; 1696 } 1697 } else { 1698 busy = (ext_busy_delta * 100) / cycle_delta; 1699 } 1700 } else { 1701 busyper = ERROR_CODE; 1702 } 1703 1704 if (busy > 100) { 1705 busy = 100; 1706 } 1707 if ( busyper != ERROR_CODE ) { 1708 busyper = busy; 1709 } 1710 } 1711 1712 ahp->ah_cycle_count = cycle_count; 1713 ahp->ah_ctl_busy = ctl_busy; 1714 ahp->ah_ext_busy = ext_busy; 1715 1716 return busyper; 1717#undef OVERFLOW_LIMIT 1718#undef ERROR_CODE 1719} 1720 1721/* BB Panic Watchdog declarations */ 1722#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1723#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1724 1725void 1726ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1727{ 1728#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1729 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1730 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1731 u_int32_t val, idle_count; 1732 1733 if (idle_tmo_ms != 0) { 1734 /* enable IRQ, disable chip-reset for BB panic */ 1735 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1736 AR_PHY_BB_PANIC_CNTL2_MASK; 1737 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1738 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1739 /* bound limit to 10 secs */ 1740 if (idle_tmo_ms > 10000) { 1741 idle_tmo_ms = 10000; 1742 } 1743 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1744 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1745 } else { 1746 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1747 } 1748 /* 1749 * enable panic in non-IDLE mode, 1750 * disable in IDLE mode, 1751 * set idle time-out 1752 */ 1753 1754 // EV92527 : Enable IDLE mode panic 1755 1756 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1757 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1758 AR_PHY_BB_PANIC_IDLE_ENABLE | 1759 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1760 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1761 } else { 1762 /* disable IRQ, disable chip-reset for BB panic */ 1763 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1764 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1765 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1766 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1767 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1768 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1769 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1770 } 1771 1772 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1773 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1774#undef HAL_BB_PANIC_IDLE_TIME_OUT 1775} 1776 1777 1778void 1779ar9300_handle_bb_panic(struct ath_hal *ah) 1780{ 1781 u_int32_t status; 1782 /* 1783 * we want to avoid printing in ISR context so we save 1784 * panic watchdog status to be printed later in DPC context 1785 */ 1786 AH9300(ah)->ah_bb_panic_last_status = status = 1787 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1788 /* 1789 * panic watchdog timer should reset on status read 1790 * but to make sure we write 0 to the watchdog status bit 1791 */ 1792 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1793} 1794 1795int 1796ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1797{ 1798 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1799 1800 /* 1801 * For signature 04000539 do not print anything. 1802 * This is a very common occurence as a compromise between 1803 * BB Panic and AH_FALSE detects (EV71009). It indicates 1804 * radar hang, which can be cleared by reprogramming 1805 * radar related register and does not requre a chip reset 1806 */ 1807 1808 /* Suppress BB Status mesg following signature */ 1809 switch (bb_panic->status) { 1810 case 0x04000539: 1811 case 0x04008009: 1812 case 0x04000b09: 1813 case 0x1300000a: 1814 return -1; 1815 } 1816 1817 bb_panic->tsf = ar9300_get_tsf32(ah); 1818 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1819 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1820 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1821 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1822 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1823 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1824 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1825 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1826 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1827 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1828 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1829 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1830 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1831 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1832 &bb_panic->rxc_pcnt, 1833 &bb_panic->rxf_pcnt, 1834 &bb_panic->txf_pcnt); 1835 1836 if (ah->ah_config.ath_hal_show_bb_panic) { 1837 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1838 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1839 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1840 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1841 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1842 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1843 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1844 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1845 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1846 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1847 bb_panic->phy_gen_ctrl); 1848 if (bb_panic->cycles) { 1849 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1850 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1851 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1852 } 1853 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1854 } 1855 1856 return 0; //The returned data will be stored for athstats to retrieve it 1857} 1858 1859/* set the reason for HAL reset */ 1860void 1861ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1862{ 1863 AH9300(ah)->ah_reset_reason = resetreason; 1864} 1865 1866/* 1867 * Configure 20/40 operation 1868 * 1869 * 20/40 = joint rx clear (control and extension) 1870 * 20 = rx clear (control) 1871 * 1872 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1873 * when changing from 20/40 => 20 only 1874 */ 1875void 1876ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1877{ 1878 u_int32_t macmode; 1879 1880 /* Configure MAC for 20/40 operation */ 1881 if (mode == HAL_HT_MACMODE_2040 && 1882 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1883 macmode = AR_2040_JOINED_RX_CLEAR; 1884 } else { 1885 macmode = 0; 1886 } 1887 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1888} 1889 1890/* 1891 * Get Rx clear (control/extension channel) 1892 * 1893 * Returns active low (busy) for ctrl/ext channel 1894 * Owl 2.0 1895 */ 1896HAL_HT_RXCLEAR 1897ar9300_get_11n_rx_clear(struct ath_hal *ah) 1898{ 1899 HAL_HT_RXCLEAR rxclear = 0; 1900 u_int32_t val; 1901 1902 val = OS_REG_READ(ah, AR_DIAG_SW); 1903 1904 /* control channel */ 1905 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1906 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1907 } 1908 /* extension channel */ 1909 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1910 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1911 } 1912 return rxclear; 1913} 1914 1915/* 1916 * Set Rx clear (control/extension channel) 1917 * 1918 * Useful for forcing the channel to appear busy for 1919 * debugging/diagnostics 1920 * Owl 2.0 1921 */ 1922void 1923ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1924{ 1925 /* control channel */ 1926 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1927 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1928 } else { 1929 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1930 } 1931 /* extension channel */ 1932 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1933 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1934 } else { 1935 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1936 } 1937} 1938 1939 1940/* 1941 * HAL support code for force ppm tracking workaround. 1942 */ 1943 1944u_int32_t 1945ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1946{ 1947 u_int32_t retval; 1948 u_int32_t off1; 1949 u_int32_t off2; 1950 1951 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1952 off1 = 0x2000; 1953 off2 = 0x1000; 1954 } else { 1955 off1 = 0x1000; 1956 off2 = 0x2000; 1957 } 1958 1959 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1960 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1961 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1962 1963 return retval; 1964} 1965 1966u_int32_t 1967ar9300_ppm_force(struct ath_hal *ah) 1968{ 1969 u_int32_t data_fine; 1970 u_int32_t data4; 1971 //u_int32_t off1; 1972 //u_int32_t off2; 1973 HAL_BOOL signed_val = AH_FALSE; 1974 1975// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1976// off1 = 0x2000; 1977// off2 = 0x1000; 1978// } else { 1979// off1 = 0x1000; 1980// off2 = 0x2000; 1981// } 1982 data_fine = 1983 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1984 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1985 1986 /* 1987 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1988 * So check value from bit[10:0]. 1989 * Now get the abs val of the ppm value read in bit[0:11]. 1990 * After that do bound check on abs value. 1991 * if value is off limit, CAP the value and and restore signed bit. 1992 */ 1993 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1994 { 1995 /* get the positive value */ 1996 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1997 signed_val = AH_TRUE; 1998 } 1999 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 2000 { 2001 HALDEBUG(ah, HAL_DEBUG_REGIO, 2002 "%s Correcting ppm out of range %x\n", 2003 __func__, (data_fine & 0x7ff)); 2004 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 2005 } 2006 /* 2007 * Restore signed value if changed above. 2008 * Use typecast to avoid compilation errors 2009 */ 2010 if (signed_val) { 2011 data_fine = (-(int32_t)data_fine) & 2012 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 2013 } 2014 2015 /* write value */ 2016 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 2017 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2018 OS_REG_WRITE(ah, AR_PHY_TIMING2, 2019 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 2020 2021 return data_fine; 2022} 2023 2024void 2025ar9300_ppm_un_force(struct ath_hal *ah) 2026{ 2027 u_int32_t data4; 2028 2029 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 2030 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 2031} 2032 2033u_int32_t 2034ar9300_ppm_arm_trigger(struct ath_hal *ah) 2035{ 2036 u_int32_t val; 2037 u_int32_t ret; 2038 2039 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 2040 ret = OS_REG_READ(ah, AR_TSF_L32); 2041 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 2042 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 2043 2044 /* return low word of TSF at arm time */ 2045 return ret; 2046} 2047 2048int 2049ar9300_ppm_get_trigger(struct ath_hal *ah) 2050{ 2051 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 2052 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 2053 { 2054 /* has not triggered yet, return AH_FALSE */ 2055 return 0; 2056 } 2057 2058 /* else triggered, return AH_TRUE */ 2059 return 1; 2060} 2061 2062void 2063ar9300_mark_phy_inactive(struct ath_hal *ah) 2064{ 2065 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2066} 2067 2068/* DEBUG */ 2069u_int32_t 2070ar9300_ppm_get_force_state(struct ath_hal *ah) 2071{ 2072 return 2073 OS_REG_READ(ah, AR_PHY_TIMING2) & 2074 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2075} 2076 2077/* 2078 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2079 */ 2080HAL_BOOL 2081ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2082{ 2083 /* 2084 * XXX FreeBSD todo: reimplement this 2085 */ 2086#if 0 2087 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2088 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2089 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2090 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2091 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2092 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2093 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2094 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2095#endif 2096 return AH_FALSE; 2097} 2098 2099void 2100ar9300_clear_mib_counters(struct ath_hal *ah) 2101{ 2102 u_int32_t reg_val; 2103 2104 reg_val = OS_REG_READ(ah, AR_MIBC); 2105 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2106 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2107} 2108 2109 2110/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2111HAL_BOOL 2112ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2113{ 2114 struct ath_hal_9300 *ahp = AH9300(ah); 2115 HAL_CHANNEL_INTERNAL *ichan = 2116 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2117 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2118 u_int32_t tmp = 0; 2119 2120 if (enable) { 2121 if (ahp->ah_rifs_enabled == AH_TRUE) { 2122 return AH_TRUE; 2123 } 2124 2125 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2126 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2127 ahp->ah_rifs_reg[1]); 2128 2129 ahp->ah_rifs_enabled = AH_TRUE; 2130 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2131 } else { 2132 if (ahp->ah_rifs_enabled == AH_TRUE) { 2133 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2134 AR_PHY_SEARCH_START_DELAY); 2135 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2136 } 2137 /* Change rifs init delay to 0 */ 2138 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2139 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2140 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2141 if (is_chan_2g) { 2142 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2143 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2144 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2145 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2146 } 2147 } else { 2148 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2149 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2150 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2151 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2152 } 2153 } 2154 2155 ahp->ah_rifs_enabled = AH_FALSE; 2156 } 2157 return AH_TRUE; 2158 2159} /* ar9300_set_rifs_delay () */ 2160 2161/* Set the current RIFS Rx setting */ 2162HAL_BOOL 2163ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2164{ 2165 /* Non-Owl 11n chips */ 2166 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2167 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2168 return ar9300_set_rifs_delay(ah, enable); 2169 } 2170 return AH_FALSE; 2171 } 2172 2173 return AH_TRUE; 2174} /* ar9300_set_11n_rx_rifs () */ 2175 2176static hal_mac_hangs_t 2177ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2178 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2179{ 2180 int i = 0; 2181 hal_mac_hangs_t found_hangs = 0; 2182 2183 if (hangs & dcu_chain_state) { 2184 for (i = 0; i < 6; i++) { 2185 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2186 hang_check.dcu_chain_state) 2187 { 2188 found_hangs |= dcu_chain_state; 2189 *dcu_chain = i; 2190 } 2191 } 2192 for (i = 0; i < 4; i++) { 2193 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2194 hang_check.dcu_chain_state) 2195 { 2196 found_hangs |= dcu_chain_state; 2197 *dcu_chain = i + 6; 2198 } 2199 } 2200 } 2201 2202 if (hangs & dcu_complete_state) { 2203 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2204 found_hangs |= dcu_complete_state; 2205 } 2206 } 2207 2208 return found_hangs; 2209 2210} /* end - ar9300_compare_dbg_hang */ 2211 2212#define NUM_STATUS_READS 50 2213HAL_BOOL 2214ar9300_detect_mac_hang(struct ath_hal *ah) 2215{ 2216 struct ath_hal_9300 *ahp = AH9300(ah); 2217 mac_dbg_regs_t mac_dbg; 2218 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2219 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2220 int i = 0; 2221 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2222 2223 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2224 return AH_FALSE; 2225 } 2226 2227 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2228 2229 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2230 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2231 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2232 2233 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2234 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2235 mac_dbg.dma_dbg_6); 2236 2237 if (hang_sig1 != 2238 ar9300_compare_dbg_hang(ah, mac_dbg, 2239 hang_sig1_val, hang_sig1, &dcu_chain)) 2240 { 2241 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2242 return AH_FALSE; 2243 } 2244 2245 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2246 shift_val *= 5; 2247 2248 for (i = 1; i <= NUM_STATUS_READS; i++) { 2249 if (dcu_chain < 6) { 2250 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2251 current_dcu_chain_state = 2252 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2253 } else { 2254 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2255 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2256 } 2257 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2258 2259 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2260 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2261 return AH_FALSE; 2262 } 2263 } 2264 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2265 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2266 ahp->ah_hang[MAC_HANG_SIG1]++; 2267 return AH_TRUE; 2268 2269} /* end - ar9300_detect_mac_hang */ 2270 2271/* Determine if the baseband is hung by reading the Observation Bus Register */ 2272HAL_BOOL 2273ar9300_detect_bb_hang(struct ath_hal *ah) 2274{ 2275#define N(a) (sizeof(a) / sizeof(a[0])) 2276 struct ath_hal_9300 *ahp = AH9300(ah); 2277 u_int32_t hang_sig = 0; 2278 int i = 0; 2279 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2280 * 2281 * 4 known BB hang signatures - 2282 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2283 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2284 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2285 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2286 * Rx State (bits 20-24) is 0x7. 2287 */ 2288 hal_hw_hang_check_t hang_list [] = 2289 { 2290 /* Offset Reg Value Reg Mask Hang Offset */ 2291 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2292 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2293 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2294 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2295 }; 2296 2297 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2298 HAL_DFS_BB_HANG_WAR | 2299 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2300 return AH_FALSE; 2301 } 2302 2303 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2304 for (i = 1; i <= NUM_STATUS_READS; i++) { 2305 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2306 return AH_FALSE; 2307 } 2308 } 2309 2310 for (i = 0; i < N(hang_list); i++) { 2311 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2312 ahp->ah_hang[hang_list[i].hang_offset]++; 2313 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2314 "sig3count=%d sig4count=%d\n", __func__, 2315 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2316 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2317 return AH_TRUE; 2318 } 2319 } 2320 2321 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2322 "<0x806c>=0x%x\n", __func__, hang_sig); 2323 2324 return AH_FALSE; 2325 2326#undef N 2327} /* end - ar9300_detect_bb_hang () */ 2328 2329#undef NUM_STATUS_READS 2330 2331HAL_STATUS 2332ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2333{ 2334 struct ath_hal_9300 *ahp = AH9300(ah); 2335 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2336 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2337 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2338 u_int16_t ant_config; 2339 u_int32_t hal_num_ant_config; 2340 2341 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2342 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2343 2344 if (cfg < hal_num_ant_config) { 2345 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2346 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2347 return HAL_OK; 2348 } 2349 } 2350 2351 return HAL_EINVAL; 2352} 2353 2354/* 2355 * Functions to get/set DCS mode 2356 */ 2357void 2358ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2359{ 2360 AH9300(ah)->ah_dcs_enable = mode; 2361} 2362 2363u_int32_t 2364ar9300_get_dcs_mode(struct ath_hal *ah) 2365{ 2366 return AH9300(ah)->ah_dcs_enable; 2367} 2368 2369#if ATH_BT_COEX 2370void 2371ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2372{ 2373 struct ath_hal_9300 *ahp = AH9300(ah); 2374 2375 ahp->ah_bt_module = btinfo->bt_module; 2376 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2377 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2378 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2379 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2380 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2381 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2382 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2383} 2384 2385void 2386ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2387{ 2388 struct ath_hal_9300 *ahp = AH9300(ah); 2389 HAL_BOOL rx_clear_polarity; 2390 2391 /* 2392 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2393 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2394 */ 2395 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2396 2397 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2398 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2399 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2400 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2401 SM(btconf->bt_mode, AR_BT_MODE) | 2402 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2403 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2404 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2405 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2406 2407 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2408 2409 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2410 /* Enable ACK to go out even though BT has higher priority. */ 2411 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2412 } 2413} 2414 2415void 2416ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2417{ 2418 struct ath_hal_9300 *ahp = AH9300(ah); 2419 2420 /* clear the old value, then set the new value */ 2421 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2422 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2423} 2424 2425void 2426ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2427{ 2428 struct ath_hal_9300 *ahp = AH9300(ah); 2429 2430 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2431 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2432 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2433 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2434 2435 switch (stomp_type) { 2436 case HAL_BT_COEX_STOMP_ALL: 2437 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2438 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2439 break; 2440 case HAL_BT_COEX_STOMP_LOW: 2441 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2442 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2443 break; 2444 case HAL_BT_COEX_STOMP_ALL_FORCE: 2445 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2446 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2447 break; 2448 case HAL_BT_COEX_STOMP_LOW_FORCE: 2449 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2450 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2451 break; 2452 case HAL_BT_COEX_STOMP_NONE: 2453 case HAL_BT_COEX_NO_STOMP: 2454 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2455 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2456 break; 2457 default: 2458 /* There is a force_weight from registry */ 2459 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2460 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2461 break; 2462 } 2463} 2464 2465void 2466ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2467{ 2468 struct ath_hal_9300 *ahp = AH9300(ah); 2469 2470 /* clear the old value, then set the new value */ 2471 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2472 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2473} 2474 2475static void 2476ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2477{ 2478 struct ath_hal_9300 *ahp = AH9300(ah); 2479#if ATH_ANT_DIV_COMB 2480 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2481 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2482#endif 2483 2484 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called, value=%d\n", __func__, value); 2485 2486 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2487 { 2488 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2489 { 2490 /* Config antenna diversity */ 2491#if ATH_ANT_DIV_COMB 2492 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2493#endif 2494 } 2495 } 2496} 2497 2498 2499void 2500ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2501 u_int32_t value) 2502{ 2503 struct ath_hal_9300 *ahp = AH9300(ah); 2504 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2505 2506 switch (type) { 2507 case HAL_BT_COEX_SET_ACK_PWR: 2508 if (value) { 2509 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2510 } else { 2511 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2512 } 2513 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2514 ahpriv->ah_extraTxPow, 0); 2515 break; 2516 2517 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2518 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2519 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2520 if (value) { 2521 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2522 } 2523 else { 2524 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2525 } 2526 ar9300_bt_coex_antenna_diversity(ah, value); 2527 } 2528 break; 2529 case HAL_BT_COEX_LOWER_TX_PWR: 2530 if (value) { 2531 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2532 } 2533 else { 2534 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2535 } 2536 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2537 ahpriv->ah_extraTxPow, 0); 2538 break; 2539#if ATH_SUPPORT_MCI 2540 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2541 if ((ah->ah_config.ath_hal_mci_config & 2542 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2543 { 2544 if (value) { 2545 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2546 ahp->ah_mci_concur_tx_en = AH_TRUE; 2547 } 2548 else { 2549 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2550 ahp->ah_mci_concur_tx_en = AH_FALSE; 2551 } 2552 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2553 ahpriv->ah_extraTxPow, 0); 2554 } 2555 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2556 ahp->ah_mci_concur_tx_en); 2557 break; 2558 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2559 if (value) { 2560 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2561 } 2562 else { 2563 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2564 } 2565 break; 2566#endif 2567 default: 2568 break; 2569 } 2570} 2571 2572void 2573ar9300_bt_coex_disable(struct ath_hal *ah) 2574{ 2575 struct ath_hal_9300 *ahp = AH9300(ah); 2576 2577 /* Always drive rx_clear_external output as 0 */ 2578 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2579 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2580 2581 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2582 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2583 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2584 } 2585 2586 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2587 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2588 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2589 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2590 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2591 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2592 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2593 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2594 2595 ahp->ah_bt_coex_enabled = AH_FALSE; 2596} 2597 2598int 2599ar9300_bt_coex_enable(struct ath_hal *ah) 2600{ 2601 struct ath_hal_9300 *ahp = AH9300(ah); 2602 2603 /* Program coex mode and weight registers to actually enable coex */ 2604 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2605 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2606 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2607 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2608 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2609 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2610 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2611 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2612 2613 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2614 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2615 } else { 2616 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2617 } 2618 2619 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2620 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2621 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2622 } else { 2623 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2624 } 2625 2626 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2627 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2628 ath_hal_gpioCfgOutput(ah, 2629 ahp->ah_wlan_active_gpio_select, 2630 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2631 } 2632 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2633 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2634 { 2635 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2636 ath_hal_gpioCfgOutput(ah, 2637 ahp->ah_wlan_active_gpio_select, 2638 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2639 } 2640 2641 /* 2642 * Enable a weak pull down on BT_ACTIVE. 2643 * When BT device is disabled, BT_ACTIVE might be floating. 2644 */ 2645 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2646 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2647 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2648 2649 ahp->ah_bt_coex_enabled = AH_TRUE; 2650 2651 return 0; 2652} 2653 2654u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2655{ 2656 return 0; 2657} 2658 2659u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2660{ 2661 return bOn; 2662} 2663 2664void 2665ar9300_init_bt_coex(struct ath_hal *ah) 2666{ 2667 struct ath_hal_9300 *ahp = AH9300(ah); 2668 2669 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2670 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2671 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2672 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2673 2674 /* 2675 * Set input mux for bt_prority_async and 2676 * bt_active_async to GPIO pins 2677 */ 2678 OS_REG_RMW_FIELD(ah, 2679 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2680 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2681 ahp->ah_bt_active_gpio_select); 2682 OS_REG_RMW_FIELD(ah, 2683 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2684 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2685 ahp->ah_bt_priority_gpio_select); 2686 2687 /* Configure the desired GPIO ports for input */ 2688 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2689 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2690 2691 if (ahp->ah_bt_coex_enabled) { 2692 ar9300_bt_coex_enable(ah); 2693 } else { 2694 ar9300_bt_coex_disable(ah); 2695 } 2696 } 2697 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2698 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2699 { 2700 /* 2-wire */ 2701 if (ahp->ah_bt_coex_enabled) { 2702 /* Connect bt_active_async to baseband */ 2703 OS_REG_CLR_BIT(ah, 2704 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2705 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2706 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2707 OS_REG_SET_BIT(ah, 2708 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2709 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2710 2711 /* 2712 * Set input mux for bt_prority_async and 2713 * bt_active_async to GPIO pins 2714 */ 2715 OS_REG_RMW_FIELD(ah, 2716 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2717 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2718 ahp->ah_bt_active_gpio_select); 2719 2720 /* Configure the desired GPIO ports for input */ 2721 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2722 2723 /* Enable coexistence on initialization */ 2724 ar9300_bt_coex_enable(ah); 2725 } 2726 } 2727#if ATH_SUPPORT_MCI 2728 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2729 if (ahp->ah_bt_coex_enabled) { 2730 ar9300_mci_bt_coex_enable(ah); 2731 } 2732 else { 2733 ar9300_mci_bt_coex_disable(ah); 2734 } 2735 } 2736#endif /* ATH_SUPPORT_MCI */ 2737} 2738 2739#endif /* ATH_BT_COEX */ 2740 2741HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2742{ 2743 u_int32_t val; 2744 int wasp_mm_rev; 2745 2746#define AR_SOC_RST_REVISION_ID 0xB8060090 2747#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2748 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2749 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2750 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2751#undef AR_SOC_RST_REVISION_ID 2752#undef REG_READ 2753 2754 /* 2755 * Azimuth (ProxySTA) Mode is only supported correctly by 2756 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2757 * 2758 * Enable this feature for Scorpion at this time. The silicon 2759 * still needs to be validated. 2760 */ 2761 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2762 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2763 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2764 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2765 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2766 wasp_mm_rev >= 0 /* 1 */)))) 2767 { 2768 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2769 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2770 __func__, AH_PRIVATE((ah))->ah_macVersion, 2771 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2772 return HAL_ENOTSUPP; 2773 } 2774 2775 OS_REG_WRITE(ah, 2776 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2777 2778 /* turn on mode bit[24] for proxy sta */ 2779 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2780 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2781 2782 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2783 if (enable) { 2784 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2785 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2786 AR_AZIMUTH_BA_USES_AD1; 2787 /* turn off filter pass hold (bit 9) */ 2788 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2789 } else { 2790 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2791 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2792 AR_AZIMUTH_BA_USES_AD1); 2793 } 2794 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2795 2796 /* enable promiscous mode */ 2797 OS_REG_WRITE(ah, AR_RX_FILTER, 2798 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2799 /* enable promiscous in azimuth mode */ 2800 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2801 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2802 2803 /* turn on filter pass hold (bit 9) */ 2804 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2805 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2806 2807 return HAL_OK; 2808} 2809 2810#if 0 2811void ar9300_mat_enable(struct ath_hal *ah, int enable) 2812{ 2813 /* 2814 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2815 * mitigation and turn on key search always for better performance. 2816 */ 2817 struct ath_hal_9300 *ahp = AH9300(ah); 2818 struct ath_hal_private *ap = AH_PRIVATE(ah); 2819 2820 ahp->ah_intr_mitigation_rx = !enable; 2821 if (ahp->ah_intr_mitigation_rx) { 2822 /* 2823 * Enable Interrupt Mitigation for Rx. 2824 * If no build-specific limits for the rx interrupt mitigation 2825 * timer have been specified, use conservative defaults. 2826 */ 2827 #ifndef AH_RIMT_VAL_LAST 2828 #define AH_RIMT_LAST_MICROSEC 500 2829 #endif 2830 #ifndef AH_RIMT_VAL_FIRST 2831 #define AH_RIMT_FIRST_MICROSEC 2000 2832 #endif 2833 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2834 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2835 } else { 2836 OS_REG_WRITE(ah, AR_RIMT, 0); 2837 } 2838 2839 ahp->ah_enable_keysearch_always = !!enable; 2840 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2841} 2842#endif 2843 2844void ar9300_enable_tpc(struct ath_hal *ah) 2845{ 2846 u_int32_t val = 0; 2847 2848 ah->ah_config.ath_hal_desc_tpc = 1; 2849 2850 /* Enable TPC */ 2851 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2852 2853 /* 2854 * Disable per chain power reduction since we are already 2855 * accounting for this in our calculations 2856 */ 2857 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2858 if (AR_SREV_WASP(ah)) { 2859 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2860 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2861 } else { 2862 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2863 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2864 } 2865} 2866 2867 2868/* 2869 * ar9300_force_tsf_sync 2870 * This function forces the TSF sync to the given bssid, this is implemented 2871 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2872 * mode of operation, where we sync the TSF to RootAP TSF values 2873 */ 2874void 2875ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2876 u_int16_t assoc_id) 2877{ 2878 ar9300_set_operating_mode(ah, HAL_M_STA); 2879 ar9300_write_associd(ah, bssid, assoc_id); 2880} 2881 2882void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2883{ 2884 struct ath_hal_9300 *ahp = AH9300(ah); 2885 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2886 u_int32_t temp_powertx_rate9_reg_val; 2887 int8_t olpc_power_offset = 0; 2888 int8_t tmp_olpc_val = 0; 2889 HAL_RSSI_TX_POWER old_greentx_status; 2890 u_int8_t target_power_val_t[ar9300_rate_size]; 2891 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2892 2893 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2894 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2895 return; 2896 } 2897 2898 old_greentx_status = AH9300(ah)->green_tx_status; 2899 if (ahp->ah_hw_green_tx_enable) { 2900 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2901 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2902 } else { 2903 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2904 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2905 } 2906 2907 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2908 && (rssi > tmp_rss1_thr1)) 2909 { 2910 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2911 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2912 } 2913 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2914 && (rssi > tmp_rss1_thr2)) 2915 { 2916 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2917 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2918 } 2919 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2920 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2921 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2922 } 2923 } 2924 2925 /* If status is not change, don't do anything */ 2926 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2927 return; 2928 } 2929 2930 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2931 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2932 && AR_SREV_POSEIDON(ah)) 2933 { 2934 if (ahp->ah_hw_green_tx_enable) { 2935 switch (AH9300(ah)->green_tx_status) { 2936 case HAL_RSSI_TX_POWER_SHORT: 2937 /* 1. TxPower Config */ 2938 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2939 sizeof(target_power_val_t)); 2940 /* 1.1 Store OLPC Delta Calibration Offset*/ 2941 olpc_power_offset = 0; 2942 /* 2. Store OB/DB */ 2943 /* 3. Store TPC settting */ 2944 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2945 SM(14, AR_TPC_CTS) | 2946 SM(14, AR_TPC_CHIRP) | 2947 SM(14, AR_TPC_RPT)); 2948 /* 4. Store BB_powertx_rate9 value */ 2949 temp_powertx_rate9_reg_val = 2950 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2951 break; 2952 case HAL_RSSI_TX_POWER_MIDDLE: 2953 /* 1. TxPower Config */ 2954 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2955 sizeof(target_power_val_t)); 2956 /* 1.1 Store OLPC Delta Calibration Offset*/ 2957 olpc_power_offset = 0; 2958 /* 2. Store OB/DB */ 2959 /* 3. Store TPC settting */ 2960 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2961 SM(18, AR_TPC_CTS) | 2962 SM(18, AR_TPC_CHIRP) | 2963 SM(18, AR_TPC_RPT)); 2964 /* 4. Store BB_powertx_rate9 value */ 2965 temp_powertx_rate9_reg_val = 2966 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2967 break; 2968 case HAL_RSSI_TX_POWER_LONG: 2969 default: 2970 /* 1. TxPower Config */ 2971 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2972 sizeof(target_power_val_t)); 2973 /* 1.1 Store OLPC Delta Calibration Offset*/ 2974 olpc_power_offset = 0; 2975 /* 2. Store OB/DB1/DB2 */ 2976 /* 3. Store TPC settting */ 2977 temp_tcp_reg_val = 2978 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2979 /* 4. Store BB_powertx_rate9 value */ 2980 temp_powertx_rate9_reg_val = 2981 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2982 break; 2983 } 2984 } else { 2985 switch (AH9300(ah)->green_tx_status) { 2986 case HAL_RSSI_TX_POWER_SHORT: 2987 /* 1. TxPower Config */ 2988 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2989 sizeof(target_power_val_t)); 2990 /* 1.1 Store OLPC Delta Calibration Offset*/ 2991 olpc_power_offset = 2992 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2993 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2994 /* 2. Store OB/DB */ 2995 temp_obdb_reg_val = 2996 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2997 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2998 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2999 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3000 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3001 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3002 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3003 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3004 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3005 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3006 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 3007 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3008 /* 3. Store TPC settting */ 3009 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 3010 SM(6, AR_TPC_CTS) | 3011 SM(6, AR_TPC_CHIRP) | 3012 SM(6, AR_TPC_RPT)); 3013 /* 4. Store BB_powertx_rate9 value */ 3014 temp_powertx_rate9_reg_val = 3015 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 3016 break; 3017 case HAL_RSSI_TX_POWER_MIDDLE: 3018 /* 1. TxPower Config */ 3019 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 3020 sizeof(target_power_val_t)); 3021 /* 1.1 Store OLPC Delta Calibration Offset*/ 3022 olpc_power_offset = 3023 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 3024 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3025 /* 2. Store OB/DB */ 3026 temp_obdb_reg_val = 3027 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3028 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 3029 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 3030 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3031 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3032 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3033 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3034 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3035 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3036 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3037 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3038 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3039 /* 3. Store TPC settting */ 3040 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 3041 SM(14, AR_TPC_CTS) | 3042 SM(14, AR_TPC_CHIRP) | 3043 SM(14, AR_TPC_RPT)); 3044 /* 4. Store BB_powertx_rate9 value */ 3045 temp_powertx_rate9_reg_val = 3046 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 3047 break; 3048 case HAL_RSSI_TX_POWER_LONG: 3049 default: 3050 /* 1. TxPower Config */ 3051 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3052 sizeof(target_power_val_t)); 3053 /* 1.1 Store OLPC Delta Calibration Offset*/ 3054 olpc_power_offset = 3055 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 3056 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3057 /* 2. Store OB/DB1/DB2 */ 3058 temp_obdb_reg_val = 3059 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3060 /* 3. Store TPC settting */ 3061 temp_tcp_reg_val = 3062 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3063 /* 4. Store BB_powertx_rate9 value */ 3064 temp_powertx_rate9_reg_val = 3065 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3066 break; 3067 } 3068 } 3069 /* 1.1 Do OLPC Delta Calibration Offset */ 3070 tmp_olpc_val = 3071 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3072 tmp_olpc_val += olpc_power_offset; 3073 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3074 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3075 AR_PHY_TPC_OLPC_GAIN_DELTA); 3076 3077 /* 1.2 TxPower Config */ 3078 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3079 /* 2. Config OB/DB */ 3080 if (!ahp->ah_hw_green_tx_enable) { 3081 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3082 } 3083 /* 3. config TPC settting */ 3084 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3085 /* 4. config BB_powertx_rate9 value */ 3086 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3087 } 3088} 3089 3090#if 0 3091void 3092ar9300_get_vow_stats( 3093 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3094{ 3095 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3096 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3097 } 3098 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3099 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3100 } 3101 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3102 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3103 } 3104 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3105 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3106 } 3107 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3108 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3109 } 3110} 3111#endif 3112 3113/* 3114 * ar9300_is_skip_paprd_by_greentx 3115 * 3116 * This function check if we need to skip PAPRD tuning 3117 * when GreenTx in specific state. 3118 */ 3119HAL_BOOL 3120ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3121{ 3122 if (AR_SREV_POSEIDON(ah) && 3123 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3124 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3125 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3126 { 3127 return AH_TRUE; 3128 } 3129 return AH_FALSE; 3130} 3131 3132void 3133ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3134{ 3135 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3136 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3137 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3138 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3139 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3140 struct ath_hal_9300 *ahp = AH9300(ah); 3141 3142 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3143 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3144 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3145 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3146 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3147 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3148 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3149 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3150 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3151 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3152 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3153 } 3154} 3155 3156void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3157{ 3158 struct ath_hal_9300 *ahp = AH9300(ah); 3159 3160 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3161 if ((value == 0) || (value == 1)) { 3162 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3163 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3164 } 3165 } 3166} 3167 3168void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3169{ 3170 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3171} 3172 3173int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3174{ 3175 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3176 3177 /* RSSI format is 8.4. Ignore lowest four bits */ 3178 val = val >> 4; 3179 return val; 3180} 3181 3182void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3183 u_int32_t rssi_threshold) 3184{ 3185 struct ath_hal_9300 *ahp = AH9300(ah); 3186 3187 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3188 3189 /* save value for restoring after chip reset */ 3190 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3191} 3192 3193void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3194{ 3195 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3196} 3197 3198void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3199{ 3200 if (on) { 3201 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3202 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3203 } 3204 else { 3205 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3206 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3207 } 3208} 3209/* 3210 * Gets the contents of the specified key cache entry. 3211 */ 3212HAL_BOOL 3213ar9300_print_keycache(struct ath_hal *ah) 3214{ 3215 3216 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3217 u_int32_t key0, key1, key2, key3, key4; 3218 u_int32_t mac_hi, mac_lo; 3219 u_int16_t entry = 0; 3220 u_int32_t valid = 0; 3221 u_int32_t key_type; 3222 3223 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3224 3225 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3226 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3227 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3228 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3229 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3230 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3231 3232 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3233 3234 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3235 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3236 3237 if (mac_hi & AR_KEYTABLE_VALID) { 3238 valid = 1; 3239 } else { 3240 valid = 0; 3241 } 3242 3243 if ((mac_hi != 0) && (mac_lo != 0)) { 3244 mac_hi &= ~0x8000; 3245 mac_hi <<= 1; 3246 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3247 mac_lo <<= 1; 3248 } 3249 3250 ath_hal_printf(ah, 3251 "%03d " 3252 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3253 " %02d %02d " 3254 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3255 entry, 3256 (key0 << 24) >> 24, (key0 << 16) >> 24, 3257 (key0 << 8) >> 24, key0 >> 24, 3258 (key1 << 24) >> 24, (key1 << 16) >> 24, 3259 //(key1 << 8) >> 24, key1 >> 24, 3260 (key2 << 24) >> 24, (key2 << 16) >> 24, 3261 (key2 << 8) >> 24, key2 >> 24, 3262 (key3 << 24) >> 24, (key3 << 16) >> 24, 3263 //(key3 << 8) >> 24, key3 >> 24, 3264 (key4 << 24) >> 24, (key4 << 16) >> 24, 3265 (key4 << 8) >> 24, key4 >> 24, 3266 valid, key_type, 3267 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3268 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3269 } 3270 3271 return AH_TRUE; 3272} 3273 3274/* enable/disable smart antenna mode */ 3275HAL_BOOL 3276ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3277{ 3278 struct ath_hal_9300 *ahp = AH9300(ah); 3279 3280 if (enable) { 3281 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3282 } else { 3283 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3284 } 3285 3286 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3287 * and swcom2 with 0 3288 * FIXME Ideally these registers need to be made read from caldata. 3289 * Until the calibration team gets them, keep them along with board 3290 * configuration. 3291 */ 3292 if (enable && AR_SREV_SCORPION(ah) && 3293 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3294 3295 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3296 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3297 } 3298 3299 ahp->ah_smartantenna_enable = enable; 3300 return 1; 3301} 3302 3303#ifdef ATH_TX99_DIAG 3304#ifndef ATH_SUPPORT_HTC 3305void 3306ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3307 u_int32_t txpower) 3308{ 3309#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3310 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3311 int32_t i; 3312 3313 /* The max power is limited to 63 */ 3314 if (txpower <= AR9300_MAX_RATE_POWER) { 3315 for (i = 0; i < ar9300_rate_size; i++) { 3316 p_pwr_array[i] = txpower; 3317 } 3318 } else { 3319 for (i = 0; i < ar9300_rate_size; i++) { 3320 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3321 } 3322 } 3323 3324 OS_REG_WRITE(ah, 0xa458, 0); 3325 3326 /* Write the OFDM power per rate set */ 3327 /* 6 (LSB), 9, 12, 18 (MSB) */ 3328 OS_REG_WRITE(ah, 0xa3c0, 3329 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3330 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3331 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3332 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3333 ); 3334 /* 24 (LSB), 36, 48, 54 (MSB) */ 3335 OS_REG_WRITE(ah, 0xa3c4, 3336 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3337 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3338 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3339 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3340 ); 3341 3342 /* Write the CCK power per rate set */ 3343 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3344 OS_REG_WRITE(ah, 0xa3c8, 3345 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3346 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3347 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3348 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3349 ); 3350 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3351 OS_REG_WRITE(ah, 0xa3cc, 3352 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3353 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3354 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3355 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3356 ); 3357 3358 /* Write the HT20 power per rate set */ 3359 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3360 OS_REG_WRITE(ah, 0xa3d0, 3361 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3362 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3363 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3364 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3365 ); 3366 3367 /* 6 (LSB), 7, 12, 13 (MSB) */ 3368 OS_REG_WRITE(ah, 0xa3d4, 3369 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3370 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3371 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3372 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3373 ); 3374 3375 /* 14 (LSB), 15, 20, 21 */ 3376 OS_REG_WRITE(ah, 0xa3e4, 3377 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3378 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3379 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3380 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3381 ); 3382 3383 /* Mixed HT20 and HT40 rates */ 3384 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3385 OS_REG_WRITE(ah, 0xa3e8, 3386 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3387 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3388 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3389 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3390 ); 3391 3392 /* Write the HT40 power per rate set */ 3393 /* correct PAR difference between HT40 and HT20/LEGACY */ 3394 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3395 OS_REG_WRITE(ah, 0xa3d8, 3396 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3397 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3398 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3399 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3400 ); 3401 3402 /* 6 (LSB), 7, 12, 13 (MSB) */ 3403 OS_REG_WRITE(ah, 0xa3dc, 3404 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3405 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3406 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3407 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3408 ); 3409 3410 /* 14 (LSB), 15, 20, 21 */ 3411 OS_REG_WRITE(ah, 0xa3ec, 3412 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3413 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3414 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3415 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3416 ); 3417#undef PWR_MAS 3418} 3419 3420void 3421ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3422{ 3423 if (tx_chainmask == 0x5) { 3424 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3425 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3426 } 3427 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3428 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3429 3430 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3431 if (tx_chainmask == 0x5) { 3432 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3433 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3434 } 3435} 3436 3437void 3438ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3439 int chtype) 3440{ 3441 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3442 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3443 OS_REG_WRITE(ah, 0xa350, 3444 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3445 3446 /* 11G mode */ 3447 if (!chtype) { 3448 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3449 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3450 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3451 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3452 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3453 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3454 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3455 | (0x1 << 26) | (0x7 << 24)) 3456 & ~(0x1 << 22)); 3457 } else { 3458 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3459 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3460 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3461 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3462 | (0x1 << 26) | (0x7 << 24)) 3463 & ~(0x1 << 22)); 3464 } 3465 3466 /* chain zero */ 3467 if ((tx_chain_mask & 0x01) == 0x01) { 3468 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3469 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3470 | (0x1 << 31) | (0x5 << 15) 3471 | (0x3 << 9)) & ~(0x1 << 27) 3472 & ~(0x1 << 12)); 3473 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3474 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3475 | (0x1 << 12) | (0x1 << 10) 3476 | (0x1 << 9) | (0x1 << 8) 3477 | (0x1 << 7)) & ~(0x1 << 11)); 3478 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3479 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3480 | (0x1 << 29) | (0x1 << 25) 3481 | (0x1 << 23) | (0x1 << 19) 3482 | (0x1 << 10) | (0x1 << 9) 3483 | (0x1 << 8) | (0x1 << 3)) 3484 & ~(0x1 << 28)& ~(0x1 << 24) 3485 & ~(0x1 << 22)& ~(0x1 << 7)); 3486 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3487 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3488 | (0x1 << 23))& ~(0x1 << 21)); 3489 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3490 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3491 | (0x1 << 12) | (0x1 << 10) 3492 | (0x1 << 9) | (0x1 << 8) 3493 | (0x1 << 6) | (0x1 << 5) 3494 | (0x1 << 4) | (0x1 << 3) 3495 | (0x1 << 2)); 3496 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3497 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3498 } 3499 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3500 /* chain one */ 3501 if ((tx_chain_mask & 0x02) == 0x02 ) { 3502 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3503 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3504 | (0x1 << 31) | (0x5 << 15) 3505 | (0x3 << 9)) & ~(0x1 << 27) 3506 & ~(0x1 << 12)); 3507 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3508 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3509 | (0x1 << 12) | (0x1 << 10) 3510 | (0x1 << 9) | (0x1 << 8) 3511 | (0x1 << 7)) & ~(0x1 << 11)); 3512 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3513 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3514 | (0x1 << 29) | (0x1 << 25) 3515 | (0x1 << 23) | (0x1 << 19) 3516 | (0x1 << 10) | (0x1 << 9) 3517 | (0x1 << 8) | (0x1 << 3)) 3518 & ~(0x1 << 28)& ~(0x1 << 24) 3519 & ~(0x1 << 22)& ~(0x1 << 7)); 3520 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3521 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3522 | (0x1 << 23))& ~(0x1 << 21)); 3523 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3524 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3525 | (0x1 << 12) | (0x1 << 10) 3526 | (0x1 << 9) | (0x1 << 8) 3527 | (0x1 << 6) | (0x1 << 5) 3528 | (0x1 << 4) | (0x1 << 3) 3529 | (0x1 << 2)); 3530 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3531 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3532 } 3533 } 3534 if (AR_SREV_OSPREY(ah)) { 3535 /* chain two */ 3536 if ((tx_chain_mask & 0x04) == 0x04 ) { 3537 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3538 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3539 | (0x1 << 31) | (0x5 << 15) 3540 | (0x3 << 9)) & ~(0x1 << 27) 3541 & ~(0x1 << 12)); 3542 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3543 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3544 | (0x1 << 12) | (0x1 << 10) 3545 | (0x1 << 9) | (0x1 << 8) 3546 | (0x1 << 7)) & ~(0x1 << 11)); 3547 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3548 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3549 | (0x1 << 29) | (0x1 << 25) 3550 | (0x1 << 23) | (0x1 << 19) 3551 | (0x1 << 10) | (0x1 << 9) 3552 | (0x1 << 8) | (0x1 << 3)) 3553 & ~(0x1 << 28)& ~(0x1 << 24) 3554 & ~(0x1 << 22)& ~(0x1 << 7)); 3555 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3556 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3557 | (0x1 << 23))& ~(0x1 << 21)); 3558 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3559 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3560 | (0x1 << 12) | (0x1 << 10) 3561 | (0x1 << 9) | (0x1 << 8) 3562 | (0x1 << 6) | (0x1 << 5) 3563 | (0x1 << 4) | (0x1 << 3) 3564 | (0x1 << 2)); 3565 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3566 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3567 } 3568 } 3569 3570 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3571 OS_REG_WRITE(ah, 0xa288, 0x111); 3572 } else { 3573 /* chain zero */ 3574 if ((tx_chain_mask & 0x01) == 0x01) { 3575 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3576 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3577 | (0x1 << 31) | (0x1 << 27) 3578 | (0x3 << 23) | (0x1 << 19) 3579 | (0x1 << 15) | (0x3 << 9)) 3580 & ~(0x1 << 12)); 3581 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3582 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3583 | (0x1 << 12) | (0x1 << 10) 3584 | (0x1 << 9) | (0x1 << 8) 3585 | (0x1 << 7) | (0x1 << 3) 3586 | (0x1 << 2) | (0x1 << 1)) 3587 & ~(0x1 << 11)& ~(0x1 << 0)); 3588 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3589 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3590 | (0x1 << 29) | (0x1 << 25) 3591 | (0x1 << 23) | (0x1 << 19) 3592 | (0x1 << 10) | (0x1 << 9) 3593 | (0x1 << 8) | (0x1 << 3)) 3594 & ~(0x1 << 28)& ~(0x1 << 24) 3595 & ~(0x1 << 22)& ~(0x1 << 7)); 3596 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3597 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3598 | (0x1 << 23))& ~(0x1 << 21)); 3599 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3600 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3601 | (0x3 << 3) | (0x3 << 0)); 3602 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3603 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3604 | (0x3 << 29) | (0x3 << 26) 3605 | (0x2 << 23) | (0x2 << 20) 3606 | (0x2 << 17))& ~(0x1 << 14)); 3607 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3608 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3609 | (0x1 << 12) | (0x1 << 10) 3610 | (0x1 << 9) | (0x1 << 8) 3611 | (0x1 << 6) | (0x1 << 5) 3612 | (0x1 << 4) | (0x1 << 3) 3613 | (0x1 << 2)); 3614 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3615 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3616 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3617 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3618 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3619 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3620 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3621 | (0x1 << 26) | (0x7 << 24) 3622 | (0x3 << 22)); 3623 } else { 3624 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3625 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3626 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3627 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3628 | (0x1 << 26) | (0x7 << 24) 3629 | (0x3 << 22)); 3630 } 3631 3632 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3633 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3634 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3635 | (0x1 << 3) | (0x1 << 2) 3636 | (0x1 << 1)) & ~(0x1 << 0)); 3637 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3638 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3639 | (0x1 << 19) | (0x1 << 3)); 3640 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3641 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3642 } 3643 if (AR_SREV_OSPREY(ah)) { 3644 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3645 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3646 | (0x1 << 3) | (0x1 << 2) 3647 | (0x1 << 1)) & ~(0x1 << 0)); 3648 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3649 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3650 | (0x1 << 19) | (0x1 << 3)); 3651 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3652 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3653 } 3654 } 3655 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3656 /* chain one */ 3657 if ((tx_chain_mask & 0x02) == 0x02 ) { 3658 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3659 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3660 | (0x1 << 3) | (0x1 << 2) 3661 | (0x1 << 1)) & ~(0x1 << 0)); 3662 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3663 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3664 | (0x1 << 19) | (0x1 << 3)); 3665 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3666 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3667 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3668 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3669 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3670 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3671 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3672 | (0x1 << 26) | (0x7 << 24) 3673 | (0x3 << 22)); 3674 } else { 3675 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3676 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3677 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3678 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3679 | (0x1 << 26) | (0x7 << 24) 3680 | (0x3 << 22)); 3681 } 3682 3683 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3684 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3685 | (0x1 << 31) | (0x1 << 27) 3686 | (0x3 << 23) | (0x1 << 19) 3687 | (0x1 << 15) | (0x3 << 9)) 3688 & ~(0x1 << 12)); 3689 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3690 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3691 | (0x1 << 12) | (0x1 << 10) 3692 | (0x1 << 9) | (0x1 << 8) 3693 | (0x1 << 7) | (0x1 << 3) 3694 | (0x1 << 2) | (0x1 << 1)) 3695 & ~(0x1 << 11)& ~(0x1 << 0)); 3696 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3697 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3698 | (0x1 << 29) | (0x1 << 25) 3699 | (0x1 << 23) | (0x1 << 19) 3700 | (0x1 << 10) | (0x1 << 9) 3701 | (0x1 << 8) | (0x1 << 3)) 3702 & ~(0x1 << 28)& ~(0x1 << 24) 3703 & ~(0x1 << 22)& ~(0x1 << 7)); 3704 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3705 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3706 | (0x1 << 23))& ~(0x1 << 21)); 3707 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3708 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3709 | (0x3 << 3) | (0x3 << 0)); 3710 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3711 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3712 | (0x3 << 29) | (0x3 << 26) 3713 | (0x2 << 23) | (0x2 << 20) 3714 | (0x2 << 17))& ~(0x1 << 14)); 3715 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3716 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3717 | (0x1 << 12) | (0x1 << 10) 3718 | (0x1 << 9) | (0x1 << 8) 3719 | (0x1 << 6) | (0x1 << 5) 3720 | (0x1 << 4) | (0x1 << 3) 3721 | (0x1 << 2)); 3722 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3723 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3724 3725 if (AR_SREV_OSPREY(ah)) { 3726 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3727 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3728 | (0x1 << 3) | (0x1 << 2) 3729 | (0x1 << 1)) & ~(0x1 << 0)); 3730 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3731 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3732 | (0x1 << 19) | (0x1 << 3)); 3733 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3734 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3735 } 3736 } 3737 } 3738 if (AR_SREV_OSPREY(ah)) { 3739 /* chain two */ 3740 if ((tx_chain_mask & 0x04) == 0x04 ) { 3741 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3742 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3743 | (0x1 << 3) | (0x1 << 2) 3744 | (0x1 << 1)) & ~(0x1 << 0)); 3745 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3746 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3747 | (0x1 << 19) | (0x1 << 3)); 3748 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3749 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3750 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3751 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3752 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3753 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3754 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3755 | (0x1 << 26) | (0x7 << 24) 3756 | (0x3 << 22)); 3757 } else { 3758 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3759 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3760 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3761 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3762 | (0x1 << 26) | (0x7 << 24) 3763 | (0x3 << 22)); 3764 } 3765 3766 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3767 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3768 | (0x1 << 3) | (0x1 << 2) 3769 | (0x1 << 1)) & ~(0x1 << 0)); 3770 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3771 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3772 | (0x1 << 19) | (0x1 << 3)); 3773 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3774 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3775 3776 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3777 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3778 | (0x1 << 31) | (0x1 << 27) 3779 | (0x3 << 23) | (0x1 << 19) 3780 | (0x1 << 15) | (0x3 << 9)) 3781 & ~(0x1 << 12)); 3782 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3783 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3784 | (0x1 << 12) | (0x1 << 10) 3785 | (0x1 << 9) | (0x1 << 8) 3786 | (0x1 << 7) | (0x1 << 3) 3787 | (0x1 << 2) | (0x1 << 1)) 3788 & ~(0x1 << 11)& ~(0x1 << 0)); 3789 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3790 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3791 | (0x1 << 29) | (0x1 << 25) 3792 | (0x1 << 23) | (0x1 << 19) 3793 | (0x1 << 10) | (0x1 << 9) 3794 | (0x1 << 8) | (0x1 << 3)) 3795 & ~(0x1 << 28)& ~(0x1 << 24) 3796 & ~(0x1 << 22)& ~(0x1 << 7)); 3797 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3798 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3799 | (0x1 << 23))& ~(0x1 << 21)); 3800 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3801 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3802 | (0x3 << 3) | (0x3 << 0)); 3803 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3804 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3805 | (0x3 << 29) | (0x3 << 26) 3806 | (0x2 << 23) | (0x2 << 20) 3807 | (0x2 << 17))& ~(0x1 << 14)); 3808 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3809 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3810 | (0x1 << 12) | (0x1 << 10) 3811 | (0x1 << 9) | (0x1 << 8) 3812 | (0x1 << 6) | (0x1 << 5) 3813 | (0x1 << 4) | (0x1 << 3) 3814 | (0x1 << 2)); 3815 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3816 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3817 } 3818 } 3819 3820 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3821 OS_REG_WRITE(ah, 0xa288, 0x222); 3822 } 3823} 3824 3825void 3826ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3827{ 3828 u_int32_t val; 3829 u_int32_t qnum = (u_int32_t)data; 3830 3831 /* Disable AGC to A2 */ 3832 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3833 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3834 3835 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3836 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3837 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3838 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3839 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3840 /* 200 ok for HT20, 400 ok for HT40 */ 3841 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3842 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3843 3844 /* set QCU modes to early termination */ 3845 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3846 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3847} 3848 3849void 3850ar9300_tx99_stop(struct ath_hal *ah) 3851{ 3852 /* this should follow the setting of start */ 3853 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3854 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3855} 3856#endif /* ATH_TX99_DIAG */ 3857#endif /* ATH_SUPPORT_HTC */ 3858 3859HAL_BOOL 3860ar9300Get3StreamSignature(struct ath_hal *ah) 3861{ 3862 return AH_FALSE; 3863} 3864 3865HAL_BOOL 3866ar9300ForceVCS(struct ath_hal *ah) 3867{ 3868 return AH_FALSE; 3869} 3870 3871HAL_BOOL 3872ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3873{ 3874 return AH_FALSE; 3875} 3876 3877static u_int32_t 3878ar9300_read_loc_timer(struct ath_hal *ah) 3879{ 3880 3881 return OS_REG_READ(ah, AR_LOC_TIMER_REG); 3882} 3883 3884HAL_BOOL 3885ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3886{ 3887 struct ath_hal_9300 *ahp = AH9300(ah); 3888 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3889 u_int8_t *ctl_index; 3890 u_int32_t offset = 0; 3891 3892 if (!ctl_array) 3893 return AH_FALSE; 3894 3895 /* copy 2G ctl freqbin and power data */ 3896 ctl_index = p_eep_data->ctl_index_2g; 3897 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3898 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3899 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3900 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3901 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3902 3903 3904 /* copy 2G ctl freqbin and power data */ 3905 ctl_index = p_eep_data->ctl_index_5g; 3906 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3907 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3908 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3909 3910 return AH_FALSE; 3911} 3912 3913void 3914ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3915{ 3916 struct ath_hal_9300 *ahp = AH9300(ah); 3917 3918 /* optional txchainmask should be subset of primary txchainmask */ 3919 if ((mask & ahp->ah_tx_chainmask) != mask) { 3920 ahp->ah_tx_chainmaskopt = 0; 3921 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3922 return; 3923 } 3924 3925 ahp->ah_tx_chainmaskopt = mask; 3926} 3927