Searched refs:mmio_base (Results 1 - 25 of 161) sorted by last modified time

1234567

/linux-master/drivers/iommu/amd/
H A Diommu.c810 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
811 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
818 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
828 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
829 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
864 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
869 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
870 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
892 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
893 tail = readl(iommu->mmio_base
[all...]
H A Dinit.c249 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
375 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
379 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
395 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
402 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
413 BUG_ON(iommu->mmio_base == NULL);
417 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
426 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
428 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
435 ctrl = readq(iommu->mmio_base
[all...]
/linux-master/drivers/gpu/drm/xe/
H A Dxe_guc_ads.c440 { .reg = RING_MODE(hwe->mmio_base), },
441 { .reg = RING_HWS_PGA(hwe->mmio_base), },
442 { .reg = RING_IMR(hwe->mmio_base), },
H A Dxe_lrc.c101 const u32 base = hwe->mmio_base;
H A Dxe_ring_ops.c194 RING_NOPID(hwe->mmio_base).addr, 0);
H A Dxe_query.c154 RING_TIMESTAMP(hwe->mmio_base),
155 RING_TIMESTAMP_UDW(hwe->mmio_base),
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c863 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
879 BLIT_CCTL(engine->mmio_base),
1481 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),
1688 wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),
2068 RING_CTX_TIMESTAMP(engine->mmio_base),
2112 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
2115 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
2118 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
2267 const u32 base = engine->mmio_base;
2324 RING_CMD_CCTL(engine->mmio_base),
[all...]
H A Dintel_engine_cs.c491 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
1658 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1668 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1803 u32 mmio_base = engine->mmio_base; local
1812 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1846 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1859 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1873 if (I915_SELFTEST_ONLY(!engine->mmio_base))
2446 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
[all...]
H A Dintel_execlists_submission.c1778 _MMIO(engine->mmio_base + status));
2756 u32 base = engine->mmio_base;
3545 u32 base = engine->mmio_base;
3568 RING_EXECLIST_CONTROL(engine->mmio_base),
/linux-master/drivers/ufs/host/
H A Dufs-qcom.c1090 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1603 res->base = hba->mmio_base;
H A Dufs-mediatek.c1598 opr->base = hba->mmio_base + opr->offset;
1614 hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities);
/linux-master/drivers/pci/
H A Dquirks.c3928 void __iomem *mmio_base; local
3935 mmio_base = pci_iomap(dev, 0, 0);
3936 if (!mmio_base)
3939 iowrite32(0x00000002, mmio_base + MSG_CTL);
3947 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3949 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3950 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3954 val = ioread32(mmio_base + PCH_PP_STATUS);
3962 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3964 pci_iounmap(dev, mmio_base);
[all...]
/linux-master/sound/soc/sof/amd/
H A Dacp.c624 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR];
/linux-master/drivers/ufs/core/
H A Dufshcd.c10505 * @mmio_base: base register address
10510 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) argument
10524 if (!mmio_base) {
10526 "Invalid memory reference for mmio_base is NULL\n");
10531 hba->mmio_base = mmio_base;
/linux-master/drivers/scsi/
H A Dmyrs.c2269 if (cs->mmio_base) {
2272 iounmap(cs->mmio_base);
2273 cs->mmio_base = NULL;
2310 cs->mmio_base = ioremap(cs->pci_addr & PAGE_MASK, mmio_size);
2311 if (cs->mmio_base == NULL) {
2317 cs->io_base = cs->mmio_base + (cs->pci_addr & ~PAGE_MASK);
H A Dmyrb.c1241 if (cb->mmio_base) {
1244 iounmap(cb->mmio_base);
3436 cb->mmio_base = ioremap(cb->pci_addr & PAGE_MASK, mmio_size);
3437 if (cb->mmio_base == NULL) {
3443 cb->io_base = cb->mmio_base + (cb->pci_addr & ~PAGE_MASK);
H A Dmegaraid.c79 #define RDINDOOR(adapter) readl((adapter)->mmio_base + 0x20)
80 #define RDOUTDOOR(adapter) readl((adapter)->mmio_base + 0x2C)
81 #define WRINDOOR(adapter,value) writel(value, (adapter)->mmio_base + 0x20)
82 #define WROUTDOOR(adapter,value) writel(value, (adapter)->mmio_base + 0x2C)
4218 adapter->mmio_base = (void __iomem *) mega_baseport;
/linux-master/drivers/ata/
H A Dsata_sx4.c747 void __iomem *mmio_base; local
752 mmio_base = host->iomap[PDC_MMIO_BAR];
755 mmio_base += PDC_CHIP0_OFS;
756 mask = readl(mmio_base + PDC_20621_SEQMASK);
784 mmio_base);
H A Dsata_mv.c1254 static void mv_dump_all_regs(void __iomem *mmio_base, argument
1272 mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c);
1273 mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34);
1274 mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4);
1275 mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c);
1277 hc_base = mv_hc_base(mmio_base, hc);
1282 port_base = mv_port_base(mmio_base, p);
/linux-master/include/ufs/
H A Dufshcd.h799 * @mmio_base: UFSHCI base register address
922 void __iomem *mmio_base; member in struct:ufs_hba
1227 writel((val), (hba)->mmio_base + (reg))
1229 readl((hba)->mmio_base + (reg))
/linux-master/drivers/video/fbdev/
H A Dvt8623fb.c31 char __iomem *mmio_base; member in struct:vt8623fb_info
727 par->mmio_base = pci_iomap(dev, 1, 0);
728 if (! par->mmio_base) {
802 pci_iounmap(dev, par->mmio_base);
828 pci_iounmap(dev, par->mmio_base);
/linux-master/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c624 par->host = par->mmio_base;
625 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
626 par->disp = par->mmio_base + MB862XX_DISP_BASE;
627 par->cap = par->mmio_base + MB862XX_CAP_BASE;
628 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
629 par->geo = par->mmio_base + MB862XX_GEO_BASE;
630 par->pio = par->mmio_base + MB862XX_PIO_BASE;
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
726 if (par->mmio_base == NULL) {
772 iounmap(par->mmio_base);
[all...]
/linux-master/drivers/usb/host/
H A Dohci-pxa27x.c120 void __iomem *mmio_base; member in struct:pxa27x_ohci
139 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
140 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
164 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
165 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
220 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
221 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
253 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
254 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
259 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base
[all...]
/linux-master/drivers/thermal/st/
H A Dst_thermal_memmap.c123 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
124 if (IS_ERR(sensor->mmio_base))
125 return PTR_ERR(sensor->mmio_base);
127 sensor->regmap = devm_regmap_init_mmio(dev, sensor->mmio_base,
H A Dst_thermal.h92 void __iomem *mmio_base; member in struct:st_thermal_sensor

Completed in 402 milliseconds

1234567