1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2// 3// This file is provided under a dual BSD/GPLv2 license. When using or 4// redistributing this file, you may do so under either license. 5// 6// Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7// 8// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9// Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11/* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15#include <linux/io.h> 16#include <linux/module.h> 17#include <linux/pci.h> 18 19#include "../ops.h" 20#include "acp.h" 21#include "acp-dsp-offset.h" 22 23static bool enable_fw_debug; 24module_param(enable_fw_debug, bool, 0444); 25MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 26 27static struct acp_quirk_entry quirk_valve_galileo = { 28 .signed_fw_image = true, 29 .skip_iram_dram_size_mod = true, 30}; 31 32const struct dmi_system_id acp_sof_quirk_table[] = { 33 { 34 /* Steam Deck OLED device */ 35 .matches = { 36 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 37 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 38 }, 39 .driver_data = &quirk_valve_galileo, 40 }, 41 {} 42}; 43EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 44 45static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data) 46{ 47 pci_write_config_dword(dev, 0x60, smn_addr); 48 pci_write_config_dword(dev, 0x64, data); 49 50 return 0; 51} 52 53static int smn_read(struct pci_dev *dev, u32 smn_addr) 54{ 55 u32 data = 0; 56 57 pci_write_config_dword(dev, 0x60, smn_addr); 58 pci_read_config_dword(dev, 0x64, &data); 59 60 return data; 61} 62 63static void init_dma_descriptor(struct acp_dev_data *adata) 64{ 65 struct snd_sof_dev *sdev = adata->dev; 66 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 67 unsigned int addr; 68 69 addr = desc->sram_pte_offset + sdev->debug_box.offset + 70 offsetof(struct scratch_reg_conf, dma_desc); 71 72 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr); 73 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT); 74} 75 76static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 77 struct dma_descriptor *dscr_info) 78{ 79 struct snd_sof_dev *sdev = adata->dev; 80 unsigned int offset; 81 82 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 83 offsetof(struct scratch_reg_conf, dma_desc) + 84 idx * sizeof(struct dma_descriptor); 85 86 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 87 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 89} 90 91static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 92 unsigned int idx, unsigned int dscr_count) 93{ 94 struct snd_sof_dev *sdev = adata->dev; 95 unsigned int val, status; 96 int ret; 97 98 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), 99 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 100 101 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val, 102 val & (1 << ch), ACP_REG_POLL_INTERVAL, 103 ACP_REG_POLL_TIMEOUT_US); 104 if (ret < 0) { 105 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS); 106 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32)); 107 108 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 109 return ret; 110 } 111 112 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0); 113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count); 114 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx); 115 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0); 116 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 117 118 return ret; 119} 120 121static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 122 unsigned int dscr_count, struct dma_descriptor *dscr_info) 123{ 124 struct snd_sof_dev *sdev = adata->dev; 125 int ret; 126 u16 dscr; 127 128 if (!dscr_info || !dscr_count) 129 return -EINVAL; 130 131 for (dscr = 0; dscr < dscr_count; dscr++) 132 configure_dma_descriptor(adata, dscr, dscr_info++); 133 134 ret = config_dma_channel(adata, ch, 0, dscr_count); 135 if (ret < 0) 136 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 137 138 return ret; 139} 140 141int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 142 unsigned int dest_addr, int dsp_data_size) 143{ 144 struct snd_sof_dev *sdev = adata->dev; 145 unsigned int desc_count, index; 146 int ret; 147 148 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 149 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 150 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 151 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 152 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 153 if (dsp_data_size < ACP_PAGE_SIZE) 154 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 155 } 156 157 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 158 if (ret) 159 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 160 161 /* Clear descriptor array */ 162 for (index = 0; index < desc_count; index++) 163 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 164 165 return ret; 166} 167 168/* 169 * psp_mbox_ready- function to poll ready bit of psp mbox 170 * @adata: acp device data 171 * @ack: bool variable to check ready bit status or psp ack 172 */ 173 174static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 175{ 176 struct snd_sof_dev *sdev = adata->dev; 177 int ret; 178 u32 data; 179 180 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US, 181 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG); 182 if (!ret) 183 return 0; 184 185 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 186 187 if (ack) 188 return -ETIMEDOUT; 189 190 return -EBUSY; 191} 192 193/* 194 * psp_send_cmd - function to send psp command over mbox 195 * @adata: acp device data 196 * @cmd: non zero integer value for command type 197 */ 198 199static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 200{ 201 struct snd_sof_dev *sdev = adata->dev; 202 int ret; 203 u32 data; 204 205 if (!cmd) 206 return -EINVAL; 207 208 /* Get a non-zero Doorbell value from PSP */ 209 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, 210 adata->smn_dev, MP0_C2PMSG_73_REG); 211 212 if (ret) { 213 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 214 return ret; 215 } 216 217 /* Check if PSP is ready for new command */ 218 ret = psp_mbox_ready(adata, 0); 219 if (ret) 220 return ret; 221 222 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd); 223 224 /* Ring the Doorbell for PSP */ 225 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data); 226 227 /* Check MBOX ready as PSP ack */ 228 ret = psp_mbox_ready(adata, 1); 229 230 return ret; 231} 232 233int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 234 unsigned int start_addr, unsigned int dest_addr, 235 unsigned int image_length) 236{ 237 struct snd_sof_dev *sdev = adata->dev; 238 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 239 unsigned int tx_count, fw_qualifier, val; 240 int ret; 241 242 if (!image_addr) { 243 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 244 return -EINVAL; 245 } 246 247 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 248 if (val & ACP_SHA_RUN) { 249 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 250 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 251 val, val & ACP_SHA_RESET, 252 ACP_REG_POLL_INTERVAL, 253 ACP_REG_POLL_TIMEOUT_US); 254 if (ret < 0) { 255 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 256 return ret; 257 } 258 } 259 260 if (adata->quirks && adata->quirks->signed_fw_image) 261 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 262 263 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 264 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 265 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 266 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 267 268 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 269 tx_count, tx_count == image_length, 270 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 271 if (ret < 0) { 272 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 273 return ret; 274 } 275 276 /* psp_send_cmd only required for renoir platform (rev - 3) */ 277 if (desc->rev == 3) { 278 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 279 if (ret) 280 return ret; 281 } 282 283 /* psp_send_cmd only required for vangogh platform (rev - 5) */ 284 if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 285 /* Modify IRAM and DRAM size */ 286 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 287 if (ret) 288 return ret; 289 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 290 if (ret) 291 return ret; 292 } 293 294 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 295 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 296 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 297 if (ret < 0) { 298 dev_err(sdev->dev, "PSP validation failed\n"); 299 return ret; 300 } 301 302 return 0; 303} 304 305int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 306{ 307 struct snd_sof_dev *sdev = adata->dev; 308 unsigned int val; 309 int ret = 0; 310 311 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 312 if (val & ACP_DMA_CH_RUN) { 313 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val, 314 ACP_REG_POLL_INTERVAL, 315 ACP_DMA_COMPLETE_TIMEOUT_US); 316 if (ret < 0) 317 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 318 } 319 320 return ret; 321} 322 323void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 324{ 325 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 326 int i, j; 327 328 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 329 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 330} 331 332void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 333{ 334 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 335 int i, j; 336 337 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 338 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 339} 340 341static int acp_memory_init(struct snd_sof_dev *sdev) 342{ 343 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 344 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 345 346 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 347 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 348 init_dma_descriptor(adata); 349 350 return 0; 351} 352 353static irqreturn_t acp_irq_thread(int irq, void *context) 354{ 355 struct snd_sof_dev *sdev = context; 356 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 357 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 358 359 spin_lock_irq(&sdev->ipc_lock); 360 /* Wait until acquired HW Semaphore lock or timeout */ 361 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 362 ; 363 spin_unlock_irq(&sdev->ipc_lock); 364 365 if (!count) { 366 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 367 return IRQ_NONE; 368 } 369 370 sof_ops(sdev)->irq_thread(irq, sdev); 371 /* Unlock or Release HW Semaphore */ 372 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 373 374 return IRQ_HANDLED; 375}; 376 377static irqreturn_t acp_irq_handler(int irq, void *dev_id) 378{ 379 struct amd_sdw_manager *amd_manager; 380 struct snd_sof_dev *sdev = dev_id; 381 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 382 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 383 unsigned int base = desc->dsp_intr_base; 384 unsigned int val; 385 int irq_flag = 0; 386 387 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 388 if (val & ACP_DSP_TO_HOST_IRQ) { 389 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 390 ACP_DSP_TO_HOST_IRQ); 391 return IRQ_WAKE_THREAD; 392 } 393 394 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 395 if (val & ACP_SDW0_IRQ_MASK) { 396 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 397 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 398 if (amd_manager) 399 schedule_work(&amd_manager->amd_sdw_irq_thread); 400 irq_flag = 1; 401 } 402 403 if (val & ACP_ERROR_IRQ_MASK) { 404 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 405 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0); 406 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0); 407 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0); 408 irq_flag = 1; 409 } 410 411 if (desc->ext_intr_stat1) { 412 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 413 if (val & ACP_SDW1_IRQ_MASK) { 414 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 415 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 416 ACP_SDW1_IRQ_MASK); 417 if (amd_manager) 418 schedule_work(&amd_manager->amd_sdw_irq_thread); 419 irq_flag = 1; 420 } 421 } 422 if (irq_flag) 423 return IRQ_HANDLED; 424 else 425 return IRQ_NONE; 426} 427 428static int acp_power_on(struct snd_sof_dev *sdev) 429{ 430 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 431 unsigned int base = desc->pgfsm_base; 432 unsigned int val; 433 int ret; 434 435 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 436 437 if (val == ACP_POWERED_ON) 438 return 0; 439 440 if (val & ACP_PGFSM_STATUS_MASK) 441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 442 ACP_PGFSM_CNTL_POWER_ON_MASK); 443 444 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 445 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 446 if (ret < 0) 447 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 448 449 return ret; 450} 451 452static int acp_reset(struct snd_sof_dev *sdev) 453{ 454 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 455 unsigned int val; 456 int ret; 457 458 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 459 460 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 461 val & ACP_SOFT_RESET_DONE_MASK, 462 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 463 if (ret < 0) { 464 dev_err(sdev->dev, "timeout asserting reset\n"); 465 return ret; 466 } 467 468 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 469 470 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 471 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 472 if (ret < 0) 473 dev_err(sdev->dev, "timeout in releasing reset\n"); 474 475 if (desc->acp_clkmux_sel) 476 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 477 478 if (desc->ext_intr_enb) 479 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 480 481 if (desc->ext_intr_cntl) 482 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 483 return ret; 484} 485 486static int acp_dsp_reset(struct snd_sof_dev *sdev) 487{ 488 unsigned int val; 489 int ret; 490 491 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 492 493 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 494 val & ACP_DSP_SOFT_RESET_DONE_MASK, 495 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 496 if (ret < 0) { 497 dev_err(sdev->dev, "timeout asserting reset\n"); 498 return ret; 499 } 500 501 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 502 503 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 504 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 505 if (ret < 0) 506 dev_err(sdev->dev, "timeout in releasing reset\n"); 507 508 return ret; 509} 510 511static int acp_init(struct snd_sof_dev *sdev) 512{ 513 int ret; 514 515 /* power on */ 516 ret = acp_power_on(sdev); 517 if (ret) { 518 dev_err(sdev->dev, "ACP power on failed\n"); 519 return ret; 520 } 521 522 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 523 /* Reset */ 524 return acp_reset(sdev); 525} 526 527static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 528{ 529 struct acp_dev_data *acp_data; 530 u32 sdw0_en, sdw1_en; 531 532 acp_data = sdev->pdata->hw_pdata; 533 if (!acp_data->sdw) 534 return false; 535 536 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 537 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 538 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 539 return acp_data->sdw_en_stat; 540} 541 542int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 543{ 544 int ret; 545 546 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 547 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 548 * be reset to default values which will break the ClockStop Mode functionality. 549 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 550 * is selected. For the rest of the scenarios, apply acp reset sequence. 551 */ 552 if (check_acp_sdw_enable_status(sdev)) 553 return acp_dsp_reset(sdev); 554 555 ret = acp_reset(sdev); 556 if (ret) { 557 dev_err(sdev->dev, "ACP Reset failed\n"); 558 return ret; 559 } 560 561 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00); 562 563 return 0; 564} 565EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON); 566 567int amd_sof_acp_resume(struct snd_sof_dev *sdev) 568{ 569 int ret; 570 struct acp_dev_data *acp_data; 571 572 acp_data = sdev->pdata->hw_pdata; 573 if (!acp_data->sdw_en_stat) { 574 ret = acp_init(sdev); 575 if (ret) { 576 dev_err(sdev->dev, "ACP Init failed\n"); 577 return ret; 578 } 579 return acp_memory_init(sdev); 580 } else { 581 return acp_dsp_reset(sdev); 582 } 583} 584EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON); 585 586#if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 587static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 588{ 589 struct acpi_device *sdw_dev; 590 struct acp_dev_data *acp_data; 591 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 592 593 if (!addr) 594 return -ENODEV; 595 596 acp_data = sdev->pdata->hw_pdata; 597 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 598 if (!sdw_dev) 599 return -ENODEV; 600 601 acp_data->info.handle = sdw_dev->handle; 602 acp_data->info.count = desc->sdw_max_link_count; 603 604 return amd_sdw_scan_controller(&acp_data->info); 605} 606 607static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 608{ 609 struct acp_dev_data *acp_data; 610 struct sdw_amd_res sdw_res; 611 int ret; 612 613 acp_data = sdev->pdata->hw_pdata; 614 615 memset(&sdw_res, 0, sizeof(sdw_res)); 616 sdw_res.addr = acp_data->addr; 617 sdw_res.reg_range = acp_data->reg_range; 618 sdw_res.handle = acp_data->info.handle; 619 sdw_res.parent = sdev->dev; 620 sdw_res.dev = sdev->dev; 621 sdw_res.acp_lock = &acp_data->acp_lock; 622 sdw_res.count = acp_data->info.count; 623 sdw_res.link_mask = acp_data->info.link_mask; 624 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 625 626 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 627 if (ret) 628 dev_err(sdev->dev, "SoundWire probe failed\n"); 629 return ret; 630} 631 632static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 633{ 634 struct acp_dev_data *acp_data; 635 636 acp_data = sdev->pdata->hw_pdata; 637 if (acp_data->sdw) 638 sdw_amd_exit(acp_data->sdw); 639 acp_data->sdw = NULL; 640 641 return 0; 642} 643 644#else 645static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 646{ 647 return 0; 648} 649 650static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 651{ 652 return 0; 653} 654 655static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 656{ 657 return 0; 658} 659#endif 660 661int amd_sof_acp_probe(struct snd_sof_dev *sdev) 662{ 663 struct pci_dev *pci = to_pci_dev(sdev->dev); 664 struct acp_dev_data *adata; 665 const struct sof_amd_acp_desc *chip; 666 const struct dmi_system_id *dmi_id; 667 unsigned int addr; 668 int ret; 669 670 chip = get_chip_info(sdev->pdata); 671 if (!chip) { 672 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 673 return -EIO; 674 } 675 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 676 GFP_KERNEL); 677 if (!adata) 678 return -ENOMEM; 679 680 adata->dev = sdev; 681 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 682 PLATFORM_DEVID_NONE, NULL, 0); 683 if (IS_ERR(adata->dmic_dev)) { 684 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 685 return PTR_ERR(adata->dmic_dev); 686 } 687 addr = pci_resource_start(pci, ACP_DSP_BAR); 688 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 689 if (!sdev->bar[ACP_DSP_BAR]) { 690 dev_err(sdev->dev, "ioremap error\n"); 691 ret = -ENXIO; 692 goto unregister_dev; 693 } 694 695 pci_set_master(pci); 696 adata->addr = addr; 697 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 698 mutex_init(&adata->acp_lock); 699 sdev->pdata->hw_pdata = adata; 700 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL); 701 if (!adata->smn_dev) { 702 dev_err(sdev->dev, "Failed to get host bridge device\n"); 703 ret = -ENODEV; 704 goto unregister_dev; 705 } 706 707 ret = acp_init(sdev); 708 if (ret < 0) 709 goto free_smn_dev; 710 711 sdev->ipc_irq = pci->irq; 712 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 713 IRQF_SHARED, "AudioDSP", sdev); 714 if (ret < 0) { 715 dev_err(sdev->dev, "failed to register IRQ %d\n", 716 sdev->ipc_irq); 717 goto free_smn_dev; 718 } 719 720 /* scan SoundWire capabilities exposed by DSDT */ 721 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 722 if (ret < 0) { 723 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 724 goto skip_soundwire; 725 } 726 ret = amd_sof_sdw_probe(sdev); 727 if (ret < 0) { 728 dev_err(sdev->dev, "error: SoundWire probe error\n"); 729 free_irq(sdev->ipc_irq, sdev); 730 pci_dev_put(adata->smn_dev); 731 return ret; 732 } 733 734skip_soundwire: 735 sdev->dsp_box.offset = 0; 736 sdev->dsp_box.size = BOX_SIZE_512; 737 738 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 739 sdev->host_box.size = BOX_SIZE_512; 740 741 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 742 sdev->debug_box.size = BOX_SIZE_1024; 743 744 dmi_id = dmi_first_match(acp_sof_quirk_table); 745 if (dmi_id) { 746 adata->quirks = dmi_id->driver_data; 747 748 if (adata->quirks->signed_fw_image) { 749 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 750 "sof-%s-code.bin", 751 chip->name); 752 if (!adata->fw_code_bin) { 753 ret = -ENOMEM; 754 goto free_ipc_irq; 755 } 756 757 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 758 "sof-%s-data.bin", 759 chip->name); 760 if (!adata->fw_data_bin) { 761 ret = -ENOMEM; 762 goto free_ipc_irq; 763 } 764 } 765 } 766 767 adata->enable_fw_debug = enable_fw_debug; 768 acp_memory_init(sdev); 769 770 acp_dsp_stream_init(sdev); 771 772 return 0; 773 774free_ipc_irq: 775 free_irq(sdev->ipc_irq, sdev); 776free_smn_dev: 777 pci_dev_put(adata->smn_dev); 778unregister_dev: 779 platform_device_unregister(adata->dmic_dev); 780 return ret; 781} 782EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON); 783 784void amd_sof_acp_remove(struct snd_sof_dev *sdev) 785{ 786 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 787 788 if (adata->smn_dev) 789 pci_dev_put(adata->smn_dev); 790 791 if (adata->sdw) 792 amd_sof_sdw_exit(sdev); 793 794 if (sdev->ipc_irq) 795 free_irq(sdev->ipc_irq, sdev); 796 797 if (adata->dmic_dev) 798 platform_device_unregister(adata->dmic_dev); 799 800 acp_reset(sdev); 801} 802EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON); 803 804MODULE_DESCRIPTION("AMD ACP sof driver"); 805MODULE_IMPORT_NS(SOUNDWIRE_AMD_INIT); 806MODULE_IMPORT_NS(SND_AMD_SOUNDWIRE_ACPI); 807MODULE_LICENSE("Dual BSD/GPL"); 808