/linux-master/lib/ |
H A D | test_hmm.c | 284 .invalidate = dmirror_interval_invalidate, 1104 .invalidate = dmirror_snapshot_invalidate,
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/linux-master/fs/ext4/ |
H A D | inode.c | 1498 * function is called from invalidate page, it's 1545 bool invalidate) 1560 if (invalidate) { 1588 if (invalidate) { 5195 * In data=journal mode ext4_journalled_invalidate_folio() may fail to invalidate 1544 mpage_release_unused_pages(struct mpage_da_data *mpd, bool invalidate) argument
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/linux-master/mm/ |
H A D | mmu_notifier.c | 210 * op->invalidate(): 279 ret = interval_sub->ops->invalidate(interval_sub, &range, 439 ret = interval_sub->ops->invalidate(interval_sub, range,
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/linux-master/kernel/cgroup/ |
H A D | cpuset.c | 1675 goto invalidate; 1688 goto invalidate; 1705 invalidate: 2421 bool invalidate = false; local 2467 invalidate = true; 2470 invalidate = true; 2473 invalidate = true; 2498 invalidate = true; 2518 (is_partition_invalid(cs) && !invalidate)) { 2529 else if (invalidate) 2575 bool invalidate = false; local [all...] |
/linux-master/include/linux/ |
H A D | mmu_notifier.h | 39 * @MMU_NOTIFY_RELEASE: used during mmu_interval_notifier invalidate to signal 42 * @MMU_NOTIFY_MIGRATE: used during migrate_vma_collect() invalidate to signal 238 * @invalidate: Upon return the caller must stop using any SPTEs within this 243 bool (*invalidate)(struct mmu_interval_notifier *interval_sub, member in struct:mmu_interval_notifier_ops 312 * @interval_sub - The subscription passed to invalidate 313 * @cur_seq - The cur_seq passed to the invalidate() callback 315 * This must be called unconditionally from the invalidate callback of a 336 * unconditionally by op->invalidate() when it calls mmu_interval_set_seq().
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/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_vm.c | 642 .invalidate = vma_userptr_invalidate, 3138 * xe_vm_invalidate_vma - invalidate GPU mappings for VMA without a lock 3139 * @vma: VMA to invalidate 3182 * FIXME: We potentially need to invalidate multiple
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H A D | xe_ggtt.h | 27 bool invalidate);
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H A D | xe_ggtt.c | 434 bool invalidate) 444 if (invalidate) 433 xe_ggtt_remove_node(struct xe_ggtt *ggtt, struct drm_mm_node *node, bool invalidate) argument
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_ggtt.c | 183 ggtt->invalidate(ggtt); 220 * WCB of the writes into the GGTT before it triggers the invalidate. 448 ggtt->invalidate(ggtt); 461 return ggtt->invalidate(ggtt); 502 ggtt->invalidate(ggtt); 544 return ggtt->invalidate(ggtt); 586 return ggtt->invalidate(ggtt); 603 ggtt->invalidate(ggtt); 642 ggtt->invalidate(ggtt); 1280 ggtt->invalidate [all...] |
/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_userptr.c | 68 .invalidate = i915_gem_userptr_invalidate,
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/linux-master/arch/arm/mm/ |
H A D | tlb-v7.S | 32 * - the "Invalidate single entry" instruction will invalidate 50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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H A D | tlb-v6.S | 33 * - the "Invalidate single entry" instruction will invalidate 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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H A D | tlb-v4wbi.S | 41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | tlb-fa.S | 44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
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H A D | tlb-v4wb.S | 39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB 42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | tlb-v4.S | 39 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
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H A D | proc-xscale.S | 151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 159 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 191 * Unconditionally clean and invalidate the entire icache. 195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 210 * Clean and invalidate the entire cache. 313 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 340 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 367 * Clean and invalidate the specified virtual address range. 375 mcr p15, 0, r0, c7, c6, 1 @ invalidate [all...] |
H A D | proc-v7.S | 159 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 166 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 527 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 529 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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H A D | proc-xsc3.S | 69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 149 * Unconditionally clean and invalidate the entire icache. 153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 168 * Clean and invalidate the entire cache. 176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 206 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BT [all...] |
H A D | proc-v6.S | 162 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 163 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 164 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 214 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 216 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 218 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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H A D | proc-mohawk.S | 65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 92 * Unconditionally clean and invalidate the entire icache. 96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 * Clean and invalidate all cache entries in a particular 111 * Clean and invalidate the entire cache. 117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 127 * Clean and invalidate a range of cache entries in the 142 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate [all...] |
H A D | proc-sa1100.S | 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 154 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 194 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 211 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-sa110.S | 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-feroceon.S | 22 * using the single invalidate entry instructions. Anything larger 98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 127 * Unconditionally clean and invalidate the entire icache. 131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 138 * Clean and invalidate all cache entries in a particular 147 * Clean and invalidate the entire cache. 156 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 164 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 172 * Clean and invalidate [all...] |
H A D | proc-fa526.S | 61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB 143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpa [all...] |