#
a2faac39 |
|
24-Oct-2022 |
Nick Desaulniers <ndesaulniers@google.com> |
ARM: 9263/1: use .arch directives instead of assembler command line flags Similar to commit a6c30873ee4a ("ARM: 8989/1: use .fpu assembler directives instead of assembler arguments"). GCC and GNU binutils support setting the "sub arch" via -march=, -Wa,-march, target function attribute, and .arch assembler directive. Clang was missing support for -Wa,-march=, but this was implemented in clang-13. The behavior of both GCC and Clang is to prefer -Wa,-march= over -march= for assembler and assembler-with-cpp sources, but Clang will warn about the -march= being unused. clang: warning: argument unused during compilation: '-march=armv6k' [-Wunused-command-line-argument] Since most assembler is non-conditionally assembled with one sub arch (modulo arch/arm/delay-loop.S which conditionally is assembled as armv4 based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the .arch assembler directive. Add a few more instances found in compile testing as found by Arnd and Nathan. Link: https://github.com/llvm/llvm-project/commit/1d51c699b9e2ebc5bcfdbe85c74cc871426333d4 Link: https://bugs.llvm.org/show_bug.cgi?id=48894 Link: https://github.com/ClangBuiltLinux/linux/issues/1195 Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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#
65fddcfc |
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08-Jun-2020 |
Mike Rapoport <rppt@kernel.org> |
mm: reorder includes after introduction of linux/pgtable.h The replacement of <asm/pgrable.h> with <linux/pgtable.h> made the include of the latter in the middle of asm includes. Fix this up with the aid of the below script and manual adjustments here and there. import sys import re if len(sys.argv) is not 3: print "USAGE: %s <file> <header>" % (sys.argv[0]) sys.exit(1) hdr_to_move="#include <linux/%s>" % sys.argv[2] moved = False in_hdrs = False with open(sys.argv[1], "r") as f: lines = f.readlines() for _line in lines: line = _line.rstrip(' ') if line == hdr_to_move: continue if line.startswith("#include <linux/"): in_hdrs = True elif not moved and in_hdrs: moved = True print hdr_to_move print line Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-4-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
ca5999fd |
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08-Jun-2020 |
Mike Rapoport <rppt@kernel.org> |
mm: introduce include/linux/pgtable.h The include/linux/pgtable.h is going to be the home of generic page table manipulation functions. Start with moving asm-generic/pgtable.h to include/linux/pgtable.h and make the latter include asm/pgtable.h. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Cain <bcain@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: "David S. Miller" <davem@davemloft.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Ungerer <gerg@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Mark Salter <msalter@redhat.com> Cc: Matthew Wilcox <willy@infradead.org> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Nick Hu <nickhu@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vincent Chen <deanbo422@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will@kernel.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Link: http://lkml.kernel.org/r/20200514170327.31389-3-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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#
790756c7 |
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04-Nov-2019 |
Nick Desaulniers <ndesaulniers@google.com> |
ARM: 8933/1: replace Sun/Solaris style flag on section directive It looks like a section directive was using "Solaris style" to declare the section flags. Replace this with the GNU style so that Clang's integrated assembler can assemble this directive. The modified instances were identified via: $ ag \.section | grep # Link: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119 Link: https://github.com/ClangBuiltLinux/linux/issues/744 Link: https://bugs.llvm.org/show_bug.cgi?id=43759 Link: https://reviews.llvm.org/D69296 Acked-by: Nicolas Pitre <nico@fluxnic.net> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Suggested-by: Fangrui Song <maskray@google.com> Suggested-by: Jian Cai <jiancai@google.com> Suggested-by: Peter Smith <peter.smith@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
d2912cb1 |
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04-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
bf35706f |
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18-Mar-2015 |
Ard Biesheuvel <ardb@kernel.org> |
ARM: 8314/1: replace PROCINFO embedded branch with relative offset This patch replaces the 'branch to setup()' instructions embedded in the PROCINFO structs with the offset to that setup function relative to the base of the struct. This preserves the position independent nature of that field, but uses a data item rather than an instruction. This is mainly done to prevent linker failures on large kernels, where the setup function is out of reach for the branch. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
6ebbf2ce |
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30-Jun-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
bae0ca2b |
|
07-Feb-2014 |
Will Deacon <will@kernel.org> |
ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMU During __v{6,7}_setup, we invalidate the TLBs since we are about to enable the MMU on return to head.S. Unfortunately, without a subsequent dsb instruction, the invalidation is not guaranteed to have completed by the time we write to the sctlr, potentially exposing us to junk/stale translations cached in the TLB. This patch reworks the init functions so that the dsb used to ensure completion of cache/predictor maintenance is also used to ensure completion of the TLB invalidation. Cc: <stable@vger.kernel.org> Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
457c2403 |
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12-Feb-2013 |
Ben Dooks <ben.dooks@codethink.co.uk> |
ARM: asm: Add ARM_BE8() assembly helper Add ARM_BE8() helper to wrap any code conditional on being compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert existing places where this is to use it. Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
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#
8bd26e3a |
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17-Jun-2013 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
arm: delete __cpuinit/__CPUINIT usage from all ARM users The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. This removes all the ARM uses of the __cpuinit macros from C code, and all __CPUINIT from assembly code. It also had two ".previous" section statements that were paired off against __CPUINIT (aka .section ".cpuinit.text") that also get removed here. [1] https://lkml.org/lkml/2013/5/20/589 Cc: Russell King <linux@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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#
aa1aadc3 |
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23-Feb-2012 |
Will Deacon <will@kernel.org> |
ARM: suspend: fix CPU suspend code for !CONFIG_MMU configurations The ARM CPU suspend code can be selected even for a !CONFIG_MMU configuration. The resulting kernel will not compile and, even if it did, would access undefined co-processor registers when executing. This patch fixes the v6 and v7 CPU suspend code for the nommu case. Signed-off-by: Will Deacon <will.deacon@arm.com> Tested-by: Jonathan Austin <jonathan.austin@arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> (commit_signer:1/3=33%) CC: Santosh Shilimkar <santosh.shilimkar@ti.com> (commit_signer:1/3=33%) CC: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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#
b6c7aabd |
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08-Apr-2013 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly Let's do the changes properly and fix the same problem everywhere, not just for one case. Cc: <stable@vger.kernel.org> # kernels containing 15e0d9e37c or equivalent Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
ae8a8b95 |
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03-Apr-2013 |
Will Deacon <will@kernel.org> |
ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead Many ARMv7 cores have hardware page table walkers that can read the L1 cache. This is discoverable from the ID_MMFR3 register, although this can be expensive to access from the low-level set_pte functions and is a pain to cache, particularly with multi-cluster systems. A useful observation is that the multi-processing extensions for ARMv7 require coherent table walks, meaning that we can make use of ALT_SMP patching in proc-v7-* to patch away the cache flush safely for these cores. Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
251019fb |
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10-Feb-2013 |
Ben Dooks <ben-linux@fluff.org> |
ARM: 7650/1: mm: replace direct access to mm->context.id with new macro The mmid macro is meant to be used to get the mm->context.id data from the mm structure, but it seems to have been missed in a cuple of files. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
2b6e204f |
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07-Nov-2012 |
Nicolas Pitre <nico@fluxnic.net> |
ARM: 7572/1: proc-v6.S: fix comment Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
575320d6 |
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06-Jul-2012 |
Will Deacon <will@kernel.org> |
ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process This patch introduces a new Kconfig option which, when enabled, causes the kernel to write the PID of the current task into the PROCID field of the CONTEXTIDR on context switch. This is useful when analysing hardware trace, since writes to this register can be configured to emit an event into the trace stream. The thread notifier for writing the PID is deliberately kept separate from the ASID-writing code so that we can support newer processors using LPAE, where the ASID is stored in TTBR0. As such, the switch_mm code is updated to perform a read-modify-write sequence to ensure that we don't clobber the PID on CPUs using the classic 2-level page tables. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
1a4baafa |
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15-Nov-2011 |
Will Deacon <will@kernel.org> |
ARM: proc-*.S: place cpu_reset functions into .idmap.text section The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
1aede681 |
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28-Aug-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: no need to save/restore context ID register There is no need to save and restore the context ID register on ARMv6 and ARMv7 with a temporary page table as we write the context ID register when we switch back to the real page tables for the thread. Moreover, the temporary page tables do not contain any non-global mappings, so the context ID value should not be used. To be safe, initialize the register to a reserved context ID value. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
de8e71ca |
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27-Aug-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: only use preallocated page table during resume Only use the preallocated page table during the resume, not while suspending. This avoids the overhead of having to switch unnecessarily to the resume page table in the suspend path. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
e8ce0eb5 |
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26-Aug-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: preallocate a page table for suspend/resume Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
145e10e1 |
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15-Aug-2011 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible cache data corruption with hit-under-miss enabled). It sets the undocumented bit 31 in the auxiliary control register and the FI bit in the control register, thus disabling hit-under-miss without putting the processor into full low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
6645cb61 |
|
21-Jul-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Fix build errors caused by adding generic macros Commit 66a625a (ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macros) introduced build errors when PM_SLEEP is not enabled. The per-CPU do_suspend/do_resume functions are defined via the preprocessor to constant 0. However, the macros which use these were converted to assembly, resulting in undefined references to these functions. Fix that by moving the ! ifdef section into proc-macros.S and deleting it from all effected proc-*.S files. Acked-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f4daf06f |
|
05-Jun-2011 |
Will Deacon <will@kernel.org> |
ARM: proc: add definition of cpu_reset for ARMv6 and ARMv7 cores This patch adds simple definitions of cpu_reset for ARMv6 and ARMv7 cores, which disable the MMU via the SCTLR. Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
7b7dc6e8 |
|
23-Jun-2011 |
Dave Martin <dave.martin@linaro.org> |
ARM: mm: proc-v6: Use the new processor struct macros Signed-off-by: Dave Martin <dave.martin@linaro.org>
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#
d427958a |
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26-May-2011 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6942/1: mm: make TTBR1 always point to swapper_pg_dir on ARMv6/7 This patch makes TTBR1 point to swapper_pg_dir so that global, kernel mappings can be used exclusively on v6 and v7 cores where they are needed. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f5178ddd |
|
03-May-2011 |
Nicolas Pitre <nico@fluxnic.net> |
ARM: PJ4: remove the ARMv6 compatible cache method entries The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Saeed Bishara <saeed.bishara@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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#
29ea23ff |
|
02-Apr-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Make consolidated PM sleep code depend on PM_SLEEP CONFIG_PM is now set whenever we support either runtime PM in addition to suspend and hibernate. This causes build errors when runtime PM is enabled on a platform, but the CPU does not have the appropriate support for suspend. So, switch this code to use CONFIG_PM_SLEEP rather than CONFIG_PM to allow runtime PM to be enabled without causing build errors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
25985edc |
|
30-Mar-2011 |
Lucas De Marchi <lucas.demarchi@profusion.mobi> |
Fix common misspellings Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
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#
f6b0fa02 |
|
06-Feb-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: add generic CPU suspend/resume support This adds core support for saving and restoring CPU coprocessor registers for suspend/resume support. This contains support for suspend with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs. Tested on Assabet and Tegra 2. Tested-by: Colin Cross <ccross@android.com> Tested-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
5085f3ff |
|
01-Oct-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: hotplug cpu: Keep processor information, startup code & __lookup_processor_type When hotplug CPU is enabled, we need to keep the list of supported CPUs, their setup functions, and __lookup_processor_type in place so that we can find and initialize secondary CPUs. Move these into the __CPUINIT section. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
f00ec48f |
|
04-Sep-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Allow SMP kernels to boot on UP systems UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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9ca03a21 |
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25-Jul-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Factor out common code from cpu_proc_fin() All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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f159f4ed |
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05-Jul-2010 |
Tony Lindgren <tony@atomide.com> |
ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6 The TLS register is only available on ARM1136 r1p0 and later. Set HWCAP_TLS flags if hardware TLS is available and test for it if CONFIG_CPU_32v6K is not set for V6. Note that we set the TLS instruction in __kuser_get_tls dynamically as suggested by Jamie Lokier <jamie@shareable.org>. Also the __switch_to code is optimized out in most cases as suggested by Nicolas Pitre <nico@fluxnic.net>. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2045124f |
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19-Jan-2010 |
Tony Lindgren <tony@atomide.com> |
ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 and V7 comments The comments in cacheflush.h should follow what's in struct cpu_cache_fns. The comments for V6 and V7 are unnecessary. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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f0e5d2c9 |
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06-Dec-2009 |
Saeed Bishara <saeed@marvell.com> |
ARM: dove: fix the mm mmu flags of the pj4 procinfo ... to be the same as proc-v6 Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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edabd38e |
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06-Aug-2009 |
Saeed Bishara <saeed@marvell.com> |
ARM: add base support for Marvell Dove SoC The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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4b46d641 |
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01-Nov-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: ensure initial page tables are setup for SMP systems Mapping the same memory using two different attributes (memory type, shareability, cacheability) is unpredictable. During boot, we encounter a situation when we're updating the kernel's page tables which can lead to dirty cache lines existing in the cache which are subsequently missed. This causes stack corruption, and therefore a crash. Therefore, ensure that the shared and cacheability settings matches the configuration that will be used later; this together with the restriction in early_cachepolicy() ensures that we won't create a mismatch during boot. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4fb28474 |
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25-Sep-2009 |
Kirill A. Shutemov <kirill@shutemov.name> |
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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26584853 |
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30-May-2009 |
Catalin Marinas <catalin.marinas@arm.com> |
Add core support for ARMv6/v7 big-endian Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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991da17e |
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27-Apr-2009 |
Tim Abbott <tabbott@MIT.EDU> |
arm: Use __INIT macro instead of .text.init. arm is placing some code in the .text.init section, but it does not reference that section in its linker scripts. This change moves this code from the .text.init section to the .init.text section, which is presumably where it belongs. Signed-off-by: Tim Abbott <tabbott@mit.edu> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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8553cb67 |
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10-Nov-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
Modern processors may need to drain the WB before WFI Since WFI may cause the processor to enter a low-power mode, data may still be in the write buffer. This patch adds a DSB (or DWB) to the cpu_(v6|v7)_do_idle functions before the WFI. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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5ec9407d |
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07-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Don't include asm/elf.h in asm code asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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639b0ae7 |
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06-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Convert ARMv6 and ARMv7 to use new memory types Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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da091653 |
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06-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Convert set_pte_ext implementions to macros There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4a1fd556 |
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21-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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b7b0ba94 |
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18-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
RealView: Move the SCU initialisation out of __v6_setup This patch moves the SCU initialisation from __v6_setup to the smp_prepare_cpus() function as it relies on platform-specific settings. Changes to get_core_count() are mainly for allowing cleaner code with the upcoming PB11MPCore patches. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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48d7927b |
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18-Apr-2008 |
Paul Brook <paul@codesourcery.com> |
Add a prefetch abort handler This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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4b17244c |
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14-Feb-2007 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 4109/2: Add support for the RealView/EB MPCore revC platform The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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f2131d34 |
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08-Feb-2007 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Always mark ARMv6 PTWs outer cacheable Other platforms other than SMP may have an outer cache. For these, we also need to mark the page table walks outer cacheable. Since marking the walks always outer cacheable apparantly has no side effects, we might as well always mark them so. However, we continue to only mark PTWs shared if we have SMP enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ad1ae2fe |
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13-Dec-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Unuse another Linux PTE bit L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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94b1e96d |
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08-Dec-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Formalise the ARMv6 processor name string Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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efe90d27 |
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08-Dec-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Handle HWCAP_VFP in VFP support code Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ee90dabc |
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09-Nov-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Include asm/elf.h instead of asm/procinfo.h These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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8799ee9f |
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29-Jun-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Set bit 4 on section mappings correctly depending on CPU On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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22b19086 |
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29-Jun-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] nommu: provide a way for correct control register value selection Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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d090ddda |
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28-Jun-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: Initial uCLinux support for MMU-based CPUs In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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800d8b5c |
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25-Jun-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Remove partial non-v6 binutils compatibility proc-v6 contains some compatibility to be able to use the V6 "cps" instruction. However, the kernel makes use of this instruction elsewhere extensively, so there's no point keeping this compatibility anymore. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3747b36e |
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27-Mar-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX. Mark page table walks with outer-cacheable attribute, and enable no-execute in page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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74945c86 |
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16-Mar-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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862184fe |
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07-Nov-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM SMP] Add Realview MPcore SMP support Add SMP support for the MPcore tile fitted to the Realview ARM platform. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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cd03adb0 |
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07-Nov-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM SMP] Add support for shared memory attribute We need to set the shared memory attribute in the page tables on SMP systems to allow the cache coherency to operate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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67c5587a |
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19-Oct-2005 |
Tony Lindgren <tony@atomide.com> |
[ARM] 3024/1: Add cpu_v6_proc_fin Patch from Tony Lindgren Machine restart calls cpu_proc_fin() to clean and disable cache, and turn off interrupts. This patch adds proper cpu_v6_proc_fin. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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02b7dd12 |
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20-Sep-2005 |
Ben Dooks <ben-linux@fluff.org> |
[ARM] 2926/1: .proc.info - postfix section with .init for `make buildcheck` Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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e6ae744d |
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09-Sep-2005 |
Sam Ravnborg <sam@mars.(none)> |
kbuild: arm - use generic asm-offsets.h support Delete obsoleted stuff from arch Makefile and rename constants.h to asm-offsets.h Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
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d93742f5 |
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15-Aug-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Remove extraneous whitespace introduced in previous ARMv6 patch Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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6626a707 |
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10-Aug-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Control v6 'global' bit via Linux PTE entries Unfortunately, we can't use the "user" bit in the page tables to control whether a page table entry is "global" or "asid" specific, since the vector page is mapped as "user" accessible but is not process specific. Therefore, give direct control of the ARMv6 "nG" (not global) bit to the mm layers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1b9749e7 |
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10-Aug-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Use #defined constants for manipulating v6 hardware PTE bits Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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d1d890ed |
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06-Jul-2005 |
Catalin Marinas <catalin.marinas@arm.com> |
[PATCH] ARM: 2789/1: Enable access to both CP10 and CP11 on ARMv6 Patch from Catalin Marinas The VFP instructions trigger undefined exceptions because the access to CP11 is disabled (only CP10 is currently enabled by the kernel). The patch fixes this problem. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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79042f08 |
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24-Jun-2005 |
Catalin Marinas <catalin.marinas@arm.com> |
[PATCH] ARM: 2698/1: Enable kernel r/w access to user pages on ARMv6 Patch from Catalin Marinas cpu_v6_set_pte() sets the kernel access rights to r/o for user pages (L_PTE_USER) when neither L_PTE_WRITE nor L_PTE_DIRTY are set. This causes a kernel data abort when writing the TLS value in the 0xffff0000 page. This patch enables the kernel r/w access. Signed-off-by: Catalin Marinas Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1da177e4 |
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16-Apr-2005 |
Linus Torvalds <torvalds@ppc970.osdl.org> |
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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