Searched refs:hwpwm (Results 1 - 25 of 49) sorted by path

12

/linux-master/drivers/gpio/
H A Dgpio-mvebu.c634 pwm->hwpwm, "mvebu-pwm",
745 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
747 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
/linux-master/drivers/hwmon/
H A Daspeed-g6-pwm-tach.c154 u32 hwpwm = pwm->hwpwm; local
159 val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm));
165 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
192 u32 hwpwm = pwm->hwpwm, duty_pt, val; local
234 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
238 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
247 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
251 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
[all...]
/linux-master/drivers/leds/rgb/
H A Dleds-qcom-lpg.c1208 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1224 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
1255 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];
/linux-master/drivers/pwm/
H A Dcore.c588 pwm->hwpwm = i;
H A Dpwm-atmel-tcb.c72 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
91 if (pwm->hwpwm == 0)
126 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
144 if (pwm->hwpwm == 0) {
183 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
203 if (pwm->hwpwm == 0) {
226 if (pwm->hwpwm == 0) {
243 if (pwm->hwpwm == 0)
267 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
313 if (pwm->hwpwm
[all...]
H A Dpwm-atmel.c246 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
248 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
253 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
262 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
264 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
274 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
276 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
284 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
306 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CM
[all...]
H A Dpwm-bcm-iproc.c79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))
84 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)))
97 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
102 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
106 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
154 iproc_pwmc_disable(ip, pwm->hwpwm);
158 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm);
159 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
163 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
164 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
[all...]
H A Dpwm-bcm-kona.c106 unsigned int value, chan = pwm->hwpwm;
160 unsigned int chan = pwm->hwpwm;
205 unsigned int chan = pwm->hwpwm;
H A Dpwm-bcm2835.c43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
56 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
100 writel(val, pc->base + DUTY(pwm->hwpwm));
106 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
108 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
112 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
114 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
H A Dpwm-berlin.c100 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL);
105 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL);
107 berlin_pwm_writel(bpc, pwm->hwpwm, duty, BERLIN_PWM_DUTY);
108 berlin_pwm_writel(bpc, pwm->hwpwm, period, BERLIN_PWM_TCNT);
120 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL);
127 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL);
137 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN);
139 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_EN);
150 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN);
152 berlin_pwm_writel(bpc, pwm->hwpwm, valu
[all...]
H A Dpwm-brcmstb.c100 unsigned int channel = pwm->hwpwm;
205 brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
215 brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
H A Dpwm-clps711x.c44 u32 shift = (pwm->hwpwm + 1) * 4;
H A Dpwm-cros-ec.c138 struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
155 ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle);
168 struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
171 ret = cros_ec_pwm_get_duty(ec_pwm->ec, ec_pwm->use_pwm_type, pwm->hwpwm);
H A Dpwm-dwc-core.c70 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
78 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
79 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
88 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));
93 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled);
112 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
129 ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
130 ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
131 ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
H A Dpwm-fsl-ftm.c94 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
107 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
217 if (~(val | BIT(pwm->hwpwm)) & 0xFF)
251 pwm->hwpwm);
281 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
283 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
287 reg_polarity = BIT(pwm->hwpwm);
289 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
317 BIT(pwm->hwpwm));
341 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
[all...]
H A Dpwm-hibvt.c86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
109 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
112 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
123 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
126 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
140 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
143 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
146 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
H A Dpwm-img.c133 val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
135 PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
140 img_pwm_writel(imgchip, PWM_CH_CFG(pwm->hwpwm), val);
159 val |= BIT(pwm->hwpwm);
164 PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm));
175 val &= ~BIT(pwm->hwpwm);
H A Dpwm-imx-tpm.c149 tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
154 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
232 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
241 || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
255 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
271 writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
H A Dpwm-jz4740.c56 if (!jz4740_pwm_can_use_chn(chip, pwm->hwpwm))
59 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
74 jz->clk[pwm->hwpwm] = clk;
82 struct clk *clk = jz->clk[pwm->hwpwm];
93 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
96 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
109 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
110 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
117 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
120 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
[all...]
H A Dpwm-keembay.c102 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
109 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
137 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));
143 keembay_pwm_disable(priv, pwm->hwpwm);
171 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
174 keembay_pwm_enable(priv, pwm->hwpwm);
H A Dpwm-lp3943.c34 lp3943_pwm_request_map(struct lp3943_pwm *lp3943_pwm, int hwpwm) argument
38 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[hwpwm];
41 pwm_map->output = pdata->pwms[hwpwm]->output;
42 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs;
60 pwm_map = lp3943_pwm_request_map(lp3943_pwm, pwm->hwpwm);
82 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm];
105 if (pwm->hwpwm == 0) {
154 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm];
157 if (pwm->hwpwm == 0)
173 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[pwm->hwpwm];
[all...]
H A Dpwm-lpc18xx-sct.c140 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm);
141 val |= LPC18XX_PWM_RES(pwm->hwpwm, action);
173 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
216 pwm->hwpwm);
237 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
260 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
262 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
272 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
276 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
277 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
[all...]
H A Dpwm-lpss.c78 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
85 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
91 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
H A Dpwm-mediatek.c87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]);
106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]);
138 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
154 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
164 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
165 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
166 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
184 value |= BIT(pwm->hwpwm);
196 value &= ~BIT(pwm->hwpwm);
H A Dpwm-meson.c122 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
139 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
148 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
208 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
214 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
242 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
252 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
296 channel = &meson->channels[pwm->hwpwm];
316 channel = &meson->channels[pwm->hwpwm];
317 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
[all...]

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