/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_connectors.c | 1478 amdgpu_dig_connector->dpcd,
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H A D | amdgpu_mode.h | 553 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:amdgpu_connector_atom_dig
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H A D | atombios_dp.c | 253 const u8 dpcd[DP_DPCD_SIZE], 260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); 261 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); 322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { 359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 362 dig_connector->dpcd); 369 dig_connector->dpcd[0] = 0; 421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, 252 amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector, const u8 dpcd[DP_DPCD_SIZE], unsigned pix_clock, unsigned *dp_lanes, unsigned *dp_rate) argument 495 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:amdgpu_atombios_dp_link_train_info [all...] |
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 1448 * changed, need get latest link status from dpcd 2403 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2404 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2420 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
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H A D | amdgpu_dm_helpers.c | 523 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 524 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 763 "Configure DSC to non-virtual dpcd synaptics\n"); 779 /* Synaptics hub not support virtual dpcd, 830 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 839 "virtual dpcd", 847 "virtual dpcd", 855 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
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/linux-master/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix-anx6345.c | 63 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:anx6345 99 u8 dp_bw, dpcd[2]; local 134 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); 150 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { 151 err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]); 158 dpcd[0] &= ~DP_SET_POWER_MASK; 159 dpcd[0] |= DP_SET_POWER_D0; 161 err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]); 182 if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { 201 if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) [all...] |
H A D | analogix-anx78xx.c | 83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:anx78xx 606 u8 dp_bw, dpcd[2]; local 647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); 663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { 664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]); 671 dpcd[0] &= ~DP_SET_POWER_MASK; 672 dpcd[0] |= DP_SET_POWER_D0; 674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]); 695 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { 714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) [all...] |
/linux-master/drivers/gpu/drm/bridge/cadence/ |
H A D | cdns-mhdp8546-core.c | 338 dev_err(mhdp->dev, "dpcd write failed: %d\n", ret); 1401 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1409 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & 1414 if (drm_dp_tps3_supported(dpcd)) 1416 if (drm_dp_tps4_supported(dpcd)) 1420 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & 1426 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; local 1442 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); 1448 mhdp->link.revision = dpcd[0]; 1449 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[ 1400 cdns_mhdp_fill_sink_caps(struct cdns_mhdp_device *mhdp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument [all...] |
/linux-master/drivers/gpu/drm/bridge/ |
H A D | ite-it6505.c | 427 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:it6505 626 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num) argument 631 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num); 637 num, dpcd); 1442 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01; 1453 if (it6505->dpcd[0] == 0) { 1460 link->revision = it6505->dpcd[0]; 1461 link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]); 1462 link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK; 1464 if (it6505->dpcd[ [all...] |
H A D | tc358767.c | 345 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:tc_edp_link 811 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, 816 revision = tc->link.dpcd[DP_DPCD_REV]; 817 rate = drm_dp_max_link_rate(tc->link.dpcd); 818 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); 854 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? 1159 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) 1206 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? 1476 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
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/linux-master/drivers/gpu/drm/display/ |
H A D | drm_dp_helper.c | 284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], argument 300 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 326 rd_interval = dpcd[offset]; 339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], argument 342 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], argument 349 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 374 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 376 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 380 if (dpcd[DP_DPCD_RE 373 drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 397 drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 804 drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], u8 type) argument 821 drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument 908 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 918 drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 972 drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 1006 drm_dp_read_downstream_info(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) argument 1050 drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument 1079 drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument 1144 drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument 1187 drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid) argument 1243 drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument 1274 drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument 1305 drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], u8 color_spc) argument 1338 drm_dp_downstream_mode(struct drm_device *dev, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument 1404 drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4], const struct drm_edid *drm_edid, struct drm_dp_aux *aux) argument 1492 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument 1547 drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 port_cap[4]) argument 1574 drm_dp_read_sink_count_cap(struct drm_connector *connector, const u8 dpcd[DP_RECEIVER_CAP_SIZE], const struct drm_dp_desc *desc) argument 2533 drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, u8 *buf, int buf_size) argument 2569 drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) argument 2590 drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy, u8 caps[DP_LTTPR_PHY_CAP_SIZE]) argument 2958 drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 3056 drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], const u8 port_cap[4]) argument [all...] |
H A D | drm_dp_mst_topology.c | 2745 drm_dbg_kms(mgr->dev, "failed to dpcd write %d %d\n", tosend, ret); 3613 * @dpcd: A cached copy of the DPCD capabilities for this sink 3618 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 3622 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_12) 3654 /* get dpcd info */ 3655 ret = drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd); 3776 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 3777 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 3793 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 4923 seq_printf(m, "dpcd rea 3617 drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument [all...] |
/linux-master/drivers/gpu/drm/gma500/ |
H A D | cdv_intel_dp.c | 263 uint8_t dpcd[4]; member in struct:cdv_intel_dp 326 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 327 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 342 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 1075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1670 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, 1671 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) [all...] |
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | g4x_dp.c | 135 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
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H A D | intel_cx0_phy.c | 1822 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
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H A D | intel_display_debugfs.c | 227 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 231 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
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H A D | intel_display_types.h | 1769 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member in struct:intel_dp
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H A D | intel_dp.c | 163 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 171 return drm_dp_max_lane_count(intel_dp->dpcd); 180 /* update sink rates from dpcd */ 217 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { 964 if (!drm_dp_is_branch(intel_dp->dpcd)) 981 if (!drm_dp_is_branch(intel_dp->dpcd)) 1019 (!drm_dp_is_branch(intel_dp->dpcd) || 2928 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3038 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3039 drm_dp_is_branch(intel_dp->dpcd) 5361 u8 *dpcd = intel_dp->dpcd; local 6124 u8 dpcd[DP_RECEIVER_CAP_SIZE]; local [all...] |
H A D | intel_dp_link_training.c | 68 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 73 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 84 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 88 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 117 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 122 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 160 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 165 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument 181 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 216 u8 dpcd[DP_RECEIVER_CAP_SIZ local 67 intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE], enum drm_dp_phy dp_phy) argument 83 intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) argument [all...] |
H A D | intel_dp_link_training.h | 14 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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H A D | intel_dp_mst.c | 1513 u8 dpcd[DP_RECEIVER_CAP_SIZE]; local 1526 if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0) 1529 if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
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H A D | intel_dp_tunnel.c | 301 u8 dpcd[DP_RECEIVER_CAP_SIZE]; local 323 err = intel_dp_read_dprx_caps(intel_dp, dpcd);
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H A D | intel_lspcon.c | 87 if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) { 674 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {
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H A D | intel_psr.c | 702 drm_dp_tps3_supported(intel_dp->dpcd))
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H A D | intel_vrr.c | 33 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
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