i915/display/intel_dp.c

163 	return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
171 	return drm_dp_max_lane_count(intel_dp->dpcd);
180 /* update sink rates from dpcd */
217 	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
964 	if (!drm_dp_is_branch(intel_dp->dpcd))
981 	if (!drm_dp_is_branch(intel_dp->dpcd))
1019 		    (!drm_dp_is_branch(intel_dp->dpcd) ||
2928 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3038 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3039 		drm_dp_is_branch(intel_dp->dpcd) &&
3262 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3321 	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3521 	if (drm_dp_is_branch(intel_dp->dpcd) &&
3684 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3687 	if (!drm_dp_is_branch(intel_dp->dpcd))
3873 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3880 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3899 	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3901 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3905 			 drm_dp_is_branch(intel_dp->dpcd));
3991 					  intel_dp->dpcd,
4016 				 drm_dp_is_branch(intel_dp->dpcd));
4044 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4055 		drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4064 	bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4706 				    intel_dp->dpcd[DP_DPCD_REV]);
5234 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5259 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5311 	 * the value that was stored earlier or dpcd read failed
5361 	u8 *dpcd = intel_dp->dpcd;
5373 	if (!drm_dp_is_branch(dpcd))
5391 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5397 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5504 		drm_dp_downstream_max_bpc(intel_dp->dpcd,
5508 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5512 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5516 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5521 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5540 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5561 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5566 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5569 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5646 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5770 						 intel_dp->dpcd,
5817 					      intel_dp->dpcd,
6124 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
6156 		intel_dp_read_dprx_caps(intel_dp, dpcd);
6385 		if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6386 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==