1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include <linux/string.h> 27#include <linux/acpi.h> 28#include <linux/i2c.h> 29 30#include <drm/drm_atomic.h> 31#include <drm/drm_probe_helper.h> 32#include <drm/amdgpu_drm.h> 33#include <drm/drm_edid.h> 34#include <drm/drm_fixed.h> 35 36#include "dm_services.h" 37#include "amdgpu.h" 38#include "dc.h" 39#include "amdgpu_dm.h" 40#include "amdgpu_dm_irq.h" 41#include "amdgpu_dm_mst_types.h" 42#include "dpcd_defs.h" 43#include "dc/inc/core_types.h" 44 45#include "dm_helpers.h" 46#include "ddc_service_types.h" 47 48static u32 edid_extract_panel_id(struct edid *edid) 49{ 50 return (u32)edid->mfg_id[0] << 24 | 51 (u32)edid->mfg_id[1] << 16 | 52 (u32)EDID_PRODUCT_ID(edid); 53} 54 55static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 56{ 57 uint32_t panel_id = edid_extract_panel_id(edid); 58 59 switch (panel_id) { 60 /* Workaround for some monitors which does not work well with FAMS */ 61 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E): 62 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053): 63 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC): 64 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id); 65 edid_caps->panel_patch.disable_fams = true; 66 break; 67 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */ 68 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB): 69 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B): 70 case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A): 71 case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1): 72 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); 73 edid_caps->panel_patch.remove_sink_ext_caps = true; 74 break; 75 default: 76 return; 77 } 78} 79 80/** 81 * dm_helpers_parse_edid_caps() - Parse edid caps 82 * 83 * @link: current detected link 84 * @edid: [in] pointer to edid 85 * @edid_caps: [in] pointer to edid caps 86 * 87 * Return: void 88 */ 89enum dc_edid_status dm_helpers_parse_edid_caps( 90 struct dc_link *link, 91 const struct dc_edid *edid, 92 struct dc_edid_caps *edid_caps) 93{ 94 struct amdgpu_dm_connector *aconnector = link->priv; 95 struct drm_connector *connector = &aconnector->base; 96 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 97 struct cea_sad *sads; 98 int sad_count = -1; 99 int sadb_count = -1; 100 int i = 0; 101 uint8_t *sadb = NULL; 102 103 enum dc_edid_status result = EDID_OK; 104 105 if (!edid_caps || !edid) 106 return EDID_BAD_INPUT; 107 108 if (!drm_edid_is_valid(edid_buf)) 109 result = EDID_BAD_CHECKSUM; 110 111 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 112 ((uint16_t) edid_buf->mfg_id[1])<<8; 113 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 114 ((uint16_t) edid_buf->prod_code[1])<<8; 115 edid_caps->serial_number = edid_buf->serial; 116 edid_caps->manufacture_week = edid_buf->mfg_week; 117 edid_caps->manufacture_year = edid_buf->mfg_year; 118 119 drm_edid_get_monitor_name(edid_buf, 120 edid_caps->display_name, 121 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 122 123 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 124 125 apply_edid_quirks(edid_buf, edid_caps); 126 127 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 128 if (sad_count <= 0) 129 return result; 130 131 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT); 132 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 133 struct cea_sad *sad = &sads[i]; 134 135 edid_caps->audio_modes[i].format_code = sad->format; 136 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 137 edid_caps->audio_modes[i].sample_rate = sad->freq; 138 edid_caps->audio_modes[i].sample_size = sad->byte2; 139 } 140 141 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 142 143 if (sadb_count < 0) { 144 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 145 sadb_count = 0; 146 } 147 148 if (sadb_count) 149 edid_caps->speaker_flags = sadb[0]; 150 else 151 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 152 153 kfree(sads); 154 kfree(sadb); 155 156 return result; 157} 158 159static void 160fill_dc_mst_payload_table_from_drm(struct dc_link *link, 161 bool enable, 162 struct drm_dp_mst_atomic_payload *target_payload, 163 struct dc_dp_mst_stream_allocation_table *table) 164{ 165 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 166 struct dc_dp_mst_stream_allocation *sa; 167 struct link_mst_stream_allocation_table copy_of_link_table = 168 link->mst_stream_alloc_table; 169 170 int i; 171 int current_hw_table_stream_cnt = copy_of_link_table.stream_count; 172 struct link_mst_stream_allocation *dc_alloc; 173 174 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ 175 if (enable) { 176 dc_alloc = 177 ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; 178 dc_alloc->vcp_id = target_payload->vcpi; 179 dc_alloc->slot_count = target_payload->time_slots; 180 } else { 181 for (i = 0; i < copy_of_link_table.stream_count; i++) { 182 dc_alloc = 183 ©_of_link_table.stream_allocations[i]; 184 185 if (dc_alloc->vcp_id == target_payload->vcpi) { 186 dc_alloc->vcp_id = 0; 187 dc_alloc->slot_count = 0; 188 break; 189 } 190 } 191 ASSERT(i != copy_of_link_table.stream_count); 192 } 193 194 /* Fill payload info*/ 195 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 196 dc_alloc = 197 ©_of_link_table.stream_allocations[i]; 198 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { 199 sa = &new_table.stream_allocations[new_table.stream_count]; 200 sa->slot_count = dc_alloc->slot_count; 201 sa->vcp_id = dc_alloc->vcp_id; 202 new_table.stream_count++; 203 } 204 } 205 206 /* Overwrite the old table */ 207 *table = new_table; 208} 209 210void dm_helpers_dp_update_branch_info( 211 struct dc_context *ctx, 212 const struct dc_link *link) 213{} 214 215static void dm_helpers_construct_old_payload( 216 struct drm_dp_mst_topology_mgr *mgr, 217 struct drm_dp_mst_topology_state *mst_state, 218 struct drm_dp_mst_atomic_payload *new_payload, 219 struct drm_dp_mst_atomic_payload *old_payload) 220{ 221 struct drm_dp_mst_atomic_payload *pos; 222 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); 223 u8 next_payload_vc_start = mgr->next_start_slot; 224 u8 payload_vc_start = new_payload->vc_start_slot; 225 u8 allocated_time_slots; 226 227 *old_payload = *new_payload; 228 229 /* Set correct time_slots/PBN of old payload. 230 * other fields (delete & dsc_enabled) in 231 * struct drm_dp_mst_atomic_payload are don't care fields 232 * while calling drm_dp_remove_payload_part2() 233 */ 234 list_for_each_entry(pos, &mst_state->payloads, next) { 235 if (pos != new_payload && 236 pos->vc_start_slot > payload_vc_start && 237 pos->vc_start_slot < next_payload_vc_start) 238 next_payload_vc_start = pos->vc_start_slot; 239 } 240 241 allocated_time_slots = next_payload_vc_start - payload_vc_start; 242 243 old_payload->time_slots = allocated_time_slots; 244 old_payload->pbn = allocated_time_slots * pbn_per_slot; 245} 246 247/* 248 * Writes payload allocation table in immediate downstream device. 249 */ 250bool dm_helpers_dp_mst_write_payload_allocation_table( 251 struct dc_context *ctx, 252 const struct dc_stream_state *stream, 253 struct dc_dp_mst_stream_allocation_table *proposed_table, 254 bool enable) 255{ 256 struct amdgpu_dm_connector *aconnector; 257 struct drm_dp_mst_topology_state *mst_state; 258 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; 259 struct drm_dp_mst_topology_mgr *mst_mgr; 260 261 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 262 /* Accessing the connector state is required for vcpi_slots allocation 263 * and directly relies on behaviour in commit check 264 * that blocks before commit guaranteeing that the state 265 * is not gonna be swapped while still in use in commit tail 266 */ 267 268 if (!aconnector || !aconnector->mst_root) 269 return false; 270 271 mst_mgr = &aconnector->mst_root->mst_mgr; 272 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 273 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 274 275 if (enable) { 276 target_payload = new_payload; 277 278 /* It's OK for this to fail */ 279 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload); 280 } else { 281 /* construct old payload by VCPI*/ 282 dm_helpers_construct_old_payload(mst_mgr, mst_state, 283 new_payload, &old_payload); 284 target_payload = &old_payload; 285 286 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); 287 } 288 289 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 290 * AUX message. The sequence is slot 1-63 allocated sequence for each 291 * stream. AMD ASIC stream slot allocation should follow the same 292 * sequence. copy DRM MST allocation to dc 293 */ 294 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); 295 296 return true; 297} 298 299/* 300 * poll pending down reply 301 */ 302void dm_helpers_dp_mst_poll_pending_down_reply( 303 struct dc_context *ctx, 304 const struct dc_link *link) 305{} 306 307/* 308 * Clear payload allocation table before enable MST DP link. 309 */ 310void dm_helpers_dp_mst_clear_payload_allocation_table( 311 struct dc_context *ctx, 312 const struct dc_link *link) 313{} 314 315/* 316 * Polls for ACT (allocation change trigger) handled and sends 317 * ALLOCATE_PAYLOAD message. 318 */ 319enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 320 struct dc_context *ctx, 321 const struct dc_stream_state *stream) 322{ 323 struct amdgpu_dm_connector *aconnector; 324 struct drm_dp_mst_topology_mgr *mst_mgr; 325 int ret; 326 327 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 328 329 if (!aconnector || !aconnector->mst_root) 330 return ACT_FAILED; 331 332 mst_mgr = &aconnector->mst_root->mst_mgr; 333 334 if (!mst_mgr->mst_state) 335 return ACT_FAILED; 336 337 ret = drm_dp_check_act_status(mst_mgr); 338 339 if (ret) 340 return ACT_FAILED; 341 342 return ACT_SUCCESS; 343} 344 345void dm_helpers_dp_mst_send_payload_allocation( 346 struct dc_context *ctx, 347 const struct dc_stream_state *stream) 348{ 349 struct amdgpu_dm_connector *aconnector; 350 struct drm_dp_mst_topology_state *mst_state; 351 struct drm_dp_mst_topology_mgr *mst_mgr; 352 struct drm_dp_mst_atomic_payload *new_payload; 353 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 354 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 355 int ret = 0; 356 357 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 358 359 if (!aconnector || !aconnector->mst_root) 360 return; 361 362 mst_mgr = &aconnector->mst_root->mst_mgr; 363 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 364 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 365 366 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, new_payload); 367 368 if (ret) { 369 amdgpu_dm_set_mst_status(&aconnector->mst_status, 370 set_flag, false); 371 } else { 372 amdgpu_dm_set_mst_status(&aconnector->mst_status, 373 set_flag, true); 374 amdgpu_dm_set_mst_status(&aconnector->mst_status, 375 clr_flag, false); 376 } 377} 378 379void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 380 struct dc_context *ctx, 381 const struct dc_stream_state *stream) 382{ 383 struct amdgpu_dm_connector *aconnector; 384 struct drm_dp_mst_topology_state *mst_state; 385 struct drm_dp_mst_topology_mgr *mst_mgr; 386 struct drm_dp_mst_atomic_payload *new_payload, old_payload; 387 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 388 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 389 390 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 391 392 if (!aconnector || !aconnector->mst_root) 393 return; 394 395 mst_mgr = &aconnector->mst_root->mst_mgr; 396 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 397 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); 398 dm_helpers_construct_old_payload(mst_mgr, mst_state, 399 new_payload, &old_payload); 400 401 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); 402 403 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); 404 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); 405 } 406 407void dm_dtn_log_begin(struct dc_context *ctx, 408 struct dc_log_buffer_ctx *log_ctx) 409{ 410 static const char msg[] = "[dtn begin]\n"; 411 412 if (!log_ctx) { 413 pr_info("%s", msg); 414 return; 415 } 416 417 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 418} 419 420__printf(3, 4) 421void dm_dtn_log_append_v(struct dc_context *ctx, 422 struct dc_log_buffer_ctx *log_ctx, 423 const char *msg, ...) 424{ 425 va_list args; 426 size_t total; 427 int n; 428 429 if (!log_ctx) { 430 /* No context, redirect to dmesg. */ 431 struct va_format vaf; 432 433 vaf.fmt = msg; 434 vaf.va = &args; 435 436 va_start(args, msg); 437 pr_info("%pV", &vaf); 438 va_end(args); 439 440 return; 441 } 442 443 /* Measure the output. */ 444 va_start(args, msg); 445 n = vsnprintf(NULL, 0, msg, args); 446 va_end(args); 447 448 if (n <= 0) 449 return; 450 451 /* Reallocate the string buffer as needed. */ 452 total = log_ctx->pos + n + 1; 453 454 if (total > log_ctx->size) { 455 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL); 456 457 if (buf) { 458 memcpy(buf, log_ctx->buf, log_ctx->pos); 459 kfree(log_ctx->buf); 460 461 log_ctx->buf = buf; 462 log_ctx->size = total; 463 } 464 } 465 466 if (!log_ctx->buf) 467 return; 468 469 /* Write the formatted string to the log buffer. */ 470 va_start(args, msg); 471 n = vscnprintf( 472 log_ctx->buf + log_ctx->pos, 473 log_ctx->size - log_ctx->pos, 474 msg, 475 args); 476 va_end(args); 477 478 if (n > 0) 479 log_ctx->pos += n; 480} 481 482void dm_dtn_log_end(struct dc_context *ctx, 483 struct dc_log_buffer_ctx *log_ctx) 484{ 485 static const char msg[] = "[dtn end]\n"; 486 487 if (!log_ctx) { 488 pr_info("%s", msg); 489 return; 490 } 491 492 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 493} 494 495bool dm_helpers_dp_mst_start_top_mgr( 496 struct dc_context *ctx, 497 const struct dc_link *link, 498 bool boot) 499{ 500 struct amdgpu_dm_connector *aconnector = link->priv; 501 int ret; 502 503 if (!aconnector) { 504 DRM_ERROR("Failed to find connector for link!"); 505 return false; 506 } 507 508 if (boot) { 509 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 510 aconnector, aconnector->base.base.id); 511 return true; 512 } 513 514 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 515 aconnector, aconnector->base.base.id); 516 517 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 518 if (ret < 0) { 519 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 520 return false; 521 } 522 523 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0], 524 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK); 525 526 return true; 527} 528 529bool dm_helpers_dp_mst_stop_top_mgr( 530 struct dc_context *ctx, 531 struct dc_link *link) 532{ 533 struct amdgpu_dm_connector *aconnector = link->priv; 534 535 if (!aconnector) { 536 DRM_ERROR("Failed to find connector for link!"); 537 return false; 538 } 539 540 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 541 aconnector, aconnector->base.base.id); 542 543 if (aconnector->mst_mgr.mst_state == true) { 544 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 545 link->cur_link_settings.lane_count = 0; 546 } 547 548 return false; 549} 550 551bool dm_helpers_dp_read_dpcd( 552 struct dc_context *ctx, 553 const struct dc_link *link, 554 uint32_t address, 555 uint8_t *data, 556 uint32_t size) 557{ 558 559 struct amdgpu_dm_connector *aconnector = link->priv; 560 561 if (!aconnector) 562 return false; 563 564 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data, 565 size) == size; 566} 567 568bool dm_helpers_dp_write_dpcd( 569 struct dc_context *ctx, 570 const struct dc_link *link, 571 uint32_t address, 572 const uint8_t *data, 573 uint32_t size) 574{ 575 struct amdgpu_dm_connector *aconnector = link->priv; 576 577 if (!aconnector) { 578 DRM_ERROR("Failed to find connector for link!"); 579 return false; 580 } 581 582 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 583 address, (uint8_t *)data, size) > 0; 584} 585 586bool dm_helpers_submit_i2c( 587 struct dc_context *ctx, 588 const struct dc_link *link, 589 struct i2c_command *cmd) 590{ 591 struct amdgpu_dm_connector *aconnector = link->priv; 592 struct i2c_msg *msgs; 593 int i = 0; 594 int num = cmd->number_of_payloads; 595 bool result; 596 597 if (!aconnector) { 598 DRM_ERROR("Failed to find connector for link!"); 599 return false; 600 } 601 602 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 603 604 if (!msgs) 605 return false; 606 607 for (i = 0; i < num; i++) { 608 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 609 msgs[i].addr = cmd->payloads[i].address; 610 msgs[i].len = cmd->payloads[i].length; 611 msgs[i].buf = cmd->payloads[i].data; 612 } 613 614 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 615 616 kfree(msgs); 617 618 return result; 619} 620 621static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 622 bool is_write_cmd, 623 unsigned char cmd, 624 unsigned int length, 625 unsigned int offset, 626 unsigned char *data) 627{ 628 bool success = false; 629 unsigned char rc_data[16] = {0}; 630 unsigned char rc_offset[4] = {0}; 631 unsigned char rc_length[2] = {0}; 632 unsigned char rc_cmd = 0; 633 unsigned char rc_result = 0xFF; 634 unsigned char i = 0; 635 int ret; 636 637 if (is_write_cmd) { 638 // write rc data 639 memmove(rc_data, data, length); 640 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 641 } 642 643 // write rc offset 644 rc_offset[0] = (unsigned char) offset & 0xFF; 645 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 646 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 647 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 648 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 649 650 // write rc length 651 rc_length[0] = (unsigned char) length & 0xFF; 652 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 653 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 654 655 // write rc cmd 656 rc_cmd = cmd | 0x80; 657 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 658 659 if (ret < 0) { 660 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret); 661 return false; 662 } 663 664 // poll until active is 0 665 for (i = 0; i < 10; i++) { 666 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 667 if (rc_cmd == cmd) 668 // active is 0 669 break; 670 msleep(10); 671 } 672 673 // read rc result 674 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 675 success = (rc_result == 0); 676 677 if (success && !is_write_cmd) { 678 // read rc data 679 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 680 } 681 682 drm_dbg_dp(aux->drm_dev, "success = %d\n", success); 683 684 return success; 685} 686 687static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 688{ 689 unsigned char data[16] = {0}; 690 691 drm_dbg_dp(aux->drm_dev, "Start\n"); 692 693 // Step 2 694 data[0] = 'P'; 695 data[1] = 'R'; 696 data[2] = 'I'; 697 data[3] = 'U'; 698 data[4] = 'S'; 699 700 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 701 return; 702 703 // Step 3 and 4 704 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 705 return; 706 707 data[0] &= (~(1 << 1)); // set bit 1 to 0 708 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 709 return; 710 711 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 712 return; 713 714 data[0] &= (~(1 << 1)); // set bit 1 to 0 715 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 716 return; 717 718 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 719 return; 720 721 data[0] &= (~(1 << 1)); // set bit 1 to 0 722 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 723 return; 724 725 // Step 3 and 5 726 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 727 return; 728 729 data[0] |= (1 << 1); // set bit 1 to 1 730 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 731 return; 732 733 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 734 return; 735 736 data[0] |= (1 << 1); // set bit 1 to 1 737 738 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 739 return; 740 741 data[0] |= (1 << 1); // set bit 1 to 1 742 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 743 return; 744 745 // Step 6 746 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 747 return; 748 749 drm_dbg_dp(aux->drm_dev, "Done\n"); 750} 751 752/* MST Dock */ 753static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA"; 754 755static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 756 struct drm_dp_aux *aux, 757 const struct dc_stream_state *stream, 758 bool enable) 759{ 760 uint8_t ret = 0; 761 762 drm_dbg_dp(aux->drm_dev, 763 "Configure DSC to non-virtual dpcd synaptics\n"); 764 765 if (enable) { 766 /* When DSC is enabled on previous boot and reboot with the hub, 767 * there is a chance that Synaptics hub gets stuck during reboot sequence. 768 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 769 */ 770 if (!stream->link->link_status.link_active && 771 memcmp(stream->link->dpcd_caps.branch_dev_name, 772 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 773 apply_synaptics_fifo_reset_wa(aux); 774 775 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 776 DRM_INFO("Send DSC enable to synaptics\n"); 777 778 } else { 779 /* Synaptics hub not support virtual dpcd, 780 * external monitor occur garbage while disable DSC, 781 * Disable DSC only when entire link status turn to false, 782 */ 783 if (!stream->link->link_status.link_active) { 784 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 785 DRM_INFO("Send DSC disable to synaptics\n"); 786 } 787 } 788 789 return ret; 790} 791 792bool dm_helpers_dp_write_dsc_enable( 793 struct dc_context *ctx, 794 const struct dc_stream_state *stream, 795 bool enable) 796{ 797 static const uint8_t DSC_DISABLE; 798 static const uint8_t DSC_DECODING = 0x01; 799 static const uint8_t DSC_PASSTHROUGH = 0x02; 800 801 struct amdgpu_dm_connector *aconnector = 802 (struct amdgpu_dm_connector *)stream->dm_stream_context; 803 struct drm_device *dev = aconnector->base.dev; 804 struct drm_dp_mst_port *port; 805 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 806 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 807 uint8_t ret = 0; 808 809 if (!stream) 810 return false; 811 812 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 813 if (!aconnector->dsc_aux) 814 return false; 815 816 // apply w/a to synaptics 817 if (needs_dsc_aux_workaround(aconnector->dc_link) && 818 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 819 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 820 aconnector->dsc_aux, stream, enable_dsc); 821 822 port = aconnector->mst_output_port; 823 824 if (enable) { 825 if (port->passthrough_aux) { 826 ret = drm_dp_dpcd_write(port->passthrough_aux, 827 DP_DSC_ENABLE, 828 &enable_passthrough, 1); 829 drm_dbg_dp(dev, 830 "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 831 ret); 832 } 833 834 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 835 DP_DSC_ENABLE, &enable_dsc, 1); 836 drm_dbg_dp(dev, 837 "Sent DSC decoding enable to %s port, ret = %u\n", 838 (port->passthrough_aux) ? "remote RX" : 839 "virtual dpcd", 840 ret); 841 } else { 842 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 843 DP_DSC_ENABLE, &enable_dsc, 1); 844 drm_dbg_dp(dev, 845 "Sent DSC decoding disable to %s port, ret = %u\n", 846 (port->passthrough_aux) ? "remote RX" : 847 "virtual dpcd", 848 ret); 849 850 if (port->passthrough_aux) { 851 ret = drm_dp_dpcd_write(port->passthrough_aux, 852 DP_DSC_ENABLE, 853 &enable_passthrough, 1); 854 drm_dbg_dp(dev, 855 "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 856 ret); 857 } 858 } 859 } 860 861 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 862 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 863 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 864 drm_dbg_dp(dev, 865 "Send DSC %s to SST RX\n", 866 enable_dsc ? "enable" : "disable"); 867 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 868 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 869 drm_dbg_dp(dev, 870 "Send DSC %s to DP-HDMI PCON\n", 871 enable_dsc ? "enable" : "disable"); 872 } 873 } 874 875 return ret; 876} 877 878bool dm_helpers_is_dp_sink_present(struct dc_link *link) 879{ 880 bool dp_sink_present; 881 struct amdgpu_dm_connector *aconnector = link->priv; 882 883 if (!aconnector) { 884 BUG_ON("Failed to find connector for link!"); 885 return true; 886 } 887 888 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 889 dp_sink_present = dc_link_is_dp_sink_present(link); 890 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 891 return dp_sink_present; 892} 893 894enum dc_edid_status dm_helpers_read_local_edid( 895 struct dc_context *ctx, 896 struct dc_link *link, 897 struct dc_sink *sink) 898{ 899 struct amdgpu_dm_connector *aconnector = link->priv; 900 struct drm_connector *connector = &aconnector->base; 901 struct i2c_adapter *ddc; 902 int retry = 3; 903 enum dc_edid_status edid_status; 904 struct edid *edid; 905 906 if (link->aux_mode) 907 ddc = &aconnector->dm_dp_aux.aux.ddc; 908 else 909 ddc = &aconnector->i2c->base; 910 911 /* some dongles read edid incorrectly the first time, 912 * do check sum and retry to make sure read correct edid. 913 */ 914 do { 915 916 edid = drm_get_edid(&aconnector->base, ddc); 917 918 /* DP Compliance Test 4.2.2.6 */ 919 if (link->aux_mode && connector->edid_corrupt) 920 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 921 922 if (!edid && connector->edid_corrupt) { 923 connector->edid_corrupt = false; 924 return EDID_BAD_CHECKSUM; 925 } 926 927 if (!edid) 928 return EDID_NO_RESPONSE; 929 930 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 931 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 932 933 /* We don't need the original edid anymore */ 934 kfree(edid); 935 936 edid_status = dm_helpers_parse_edid_caps( 937 link, 938 &sink->dc_edid, 939 &sink->edid_caps); 940 941 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 942 943 if (edid_status != EDID_OK) 944 DRM_ERROR("EDID err: %d, on connector: %s", 945 edid_status, 946 aconnector->base.name); 947 if (link->aux_mode) { 948 union test_request test_request = {0}; 949 union test_response test_response = {0}; 950 951 dm_helpers_dp_read_dpcd(ctx, 952 link, 953 DP_TEST_REQUEST, 954 &test_request.raw, 955 sizeof(union test_request)); 956 957 if (!test_request.bits.EDID_READ) 958 return edid_status; 959 960 test_response.bits.EDID_CHECKSUM_WRITE = 1; 961 962 dm_helpers_dp_write_dpcd(ctx, 963 link, 964 DP_TEST_EDID_CHECKSUM, 965 &sink->dc_edid.raw_edid[sink->dc_edid.length-1], 966 1); 967 968 dm_helpers_dp_write_dpcd(ctx, 969 link, 970 DP_TEST_RESPONSE, 971 &test_response.raw, 972 sizeof(test_response)); 973 974 } 975 976 return edid_status; 977} 978int dm_helper_dmub_aux_transfer_sync( 979 struct dc_context *ctx, 980 const struct dc_link *link, 981 struct aux_payload *payload, 982 enum aux_return_code_type *operation_result) 983{ 984 if (!link->hpd_status) { 985 *operation_result = AUX_RET_ERROR_HPD_DISCON; 986 return -1; 987 } 988 989 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 990 operation_result); 991} 992 993int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 994 const struct dc_link *link, 995 struct set_config_cmd_payload *payload, 996 enum set_config_status *operation_result) 997{ 998 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 999 operation_result); 1000} 1001 1002void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 1003{ 1004 /* TODO: something */ 1005} 1006 1007void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 1008{ 1009 // TODO: 1010 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 1011} 1012 1013void dm_helpers_init_panel_settings( 1014 struct dc_context *ctx, 1015 struct dc_panel_config *panel_config, 1016 struct dc_sink *sink) 1017{ 1018 // Extra Panel Power Sequence 1019 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 1020 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 1021 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 1022 panel_config->pps.extra_post_t7_ms = 0; 1023 panel_config->pps.extra_pre_t11_ms = 0; 1024 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 1025 panel_config->pps.extra_post_OUI_ms = 0; 1026 // Feature DSC 1027 panel_config->dsc.disable_dsc_edp = false; 1028 panel_config->dsc.force_dsc_edp_policy = 0; 1029} 1030 1031void dm_helpers_override_panel_settings( 1032 struct dc_context *ctx, 1033 struct dc_panel_config *panel_config) 1034{ 1035 // Feature DSC 1036 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1037 panel_config->dsc.disable_dsc_edp = true; 1038} 1039 1040void *dm_helpers_allocate_gpu_mem( 1041 struct dc_context *ctx, 1042 enum dc_gpu_mem_alloc_type type, 1043 size_t size, 1044 long long *addr) 1045{ 1046 struct amdgpu_device *adev = ctx->driver_context; 1047 struct dal_allocation *da; 1048 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1049 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1050 int ret; 1051 1052 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1053 if (!da) 1054 return NULL; 1055 1056 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1057 domain, &da->bo, 1058 &da->gpu_addr, &da->cpu_ptr); 1059 1060 *addr = da->gpu_addr; 1061 1062 if (ret) { 1063 kfree(da); 1064 return NULL; 1065 } 1066 1067 /* add da to list in dm */ 1068 list_add(&da->list, &adev->dm.da_list); 1069 1070 return da->cpu_ptr; 1071} 1072 1073void dm_helpers_free_gpu_mem( 1074 struct dc_context *ctx, 1075 enum dc_gpu_mem_alloc_type type, 1076 void *pvMem) 1077{ 1078 struct amdgpu_device *adev = ctx->driver_context; 1079 struct dal_allocation *da; 1080 1081 /* walk the da list in DM */ 1082 list_for_each_entry(da, &adev->dm.da_list, list) { 1083 if (pvMem == da->cpu_ptr) { 1084 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1085 list_del(&da->list); 1086 kfree(da); 1087 break; 1088 } 1089 } 1090} 1091 1092bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 1093{ 1094 enum dc_irq_source irq_source; 1095 bool ret; 1096 1097 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 1098 1099 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 1100 1101 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 1102 enable ? "en" : "dis", ret); 1103 return ret; 1104} 1105 1106void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 1107{ 1108 /* TODO: virtual DPCD */ 1109 struct dc_link *link = stream->link; 1110 union down_spread_ctrl old_downspread; 1111 union down_spread_ctrl new_downspread; 1112 1113 if (link->aux_access_disabled) 1114 return; 1115 1116 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1117 &old_downspread.raw, 1118 sizeof(old_downspread))) 1119 return; 1120 1121 new_downspread.raw = old_downspread.raw; 1122 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1123 (stream->ignore_msa_timing_param) ? 1 : 0; 1124 1125 if (new_downspread.raw != old_downspread.raw) 1126 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 1127 &new_downspread.raw, 1128 sizeof(new_downspread)); 1129} 1130 1131bool dm_helpers_dp_handle_test_pattern_request( 1132 struct dc_context *ctx, 1133 const struct dc_link *link, 1134 union link_test_pattern dpcd_test_pattern, 1135 union test_misc dpcd_test_params) 1136{ 1137 enum dp_test_pattern test_pattern; 1138 enum dp_test_pattern_color_space test_pattern_color_space = 1139 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED; 1140 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED; 1141 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED; 1142 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 1143 struct pipe_ctx *pipe_ctx = NULL; 1144 struct amdgpu_dm_connector *aconnector = link->priv; 1145 struct drm_device *dev = aconnector->base.dev; 1146 int i; 1147 1148 for (i = 0; i < MAX_PIPES; i++) { 1149 if (pipes[i].stream == NULL) 1150 continue; 1151 1152 if (pipes[i].stream->link == link && !pipes[i].top_pipe && 1153 !pipes[i].prev_odm_pipe) { 1154 pipe_ctx = &pipes[i]; 1155 break; 1156 } 1157 } 1158 1159 if (pipe_ctx == NULL) 1160 return false; 1161 1162 switch (dpcd_test_pattern.bits.PATTERN) { 1163 case LINK_TEST_PATTERN_COLOR_RAMP: 1164 test_pattern = DP_TEST_PATTERN_COLOR_RAMP; 1165 break; 1166 case LINK_TEST_PATTERN_VERTICAL_BARS: 1167 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS; 1168 break; /* black and white */ 1169 case LINK_TEST_PATTERN_COLOR_SQUARES: 1170 test_pattern = (dpcd_test_params.bits.DYN_RANGE == 1171 TEST_DYN_RANGE_VESA ? 1172 DP_TEST_PATTERN_COLOR_SQUARES : 1173 DP_TEST_PATTERN_COLOR_SQUARES_CEA); 1174 break; 1175 default: 1176 test_pattern = DP_TEST_PATTERN_VIDEO_MODE; 1177 break; 1178 } 1179 1180 if (dpcd_test_params.bits.CLR_FORMAT == 0) 1181 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB; 1182 else 1183 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ? 1184 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 : 1185 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601; 1186 1187 switch (dpcd_test_params.bits.BPC) { 1188 case 0: // 6 bits 1189 requestColorDepth = COLOR_DEPTH_666; 1190 break; 1191 case 1: // 8 bits 1192 requestColorDepth = COLOR_DEPTH_888; 1193 break; 1194 case 2: // 10 bits 1195 requestColorDepth = COLOR_DEPTH_101010; 1196 break; 1197 case 3: // 12 bits 1198 requestColorDepth = COLOR_DEPTH_121212; 1199 break; 1200 default: 1201 break; 1202 } 1203 1204 switch (dpcd_test_params.bits.CLR_FORMAT) { 1205 case 0: 1206 requestPixelEncoding = PIXEL_ENCODING_RGB; 1207 break; 1208 case 1: 1209 requestPixelEncoding = PIXEL_ENCODING_YCBCR422; 1210 break; 1211 case 2: 1212 requestPixelEncoding = PIXEL_ENCODING_YCBCR444; 1213 break; 1214 default: 1215 requestPixelEncoding = PIXEL_ENCODING_RGB; 1216 break; 1217 } 1218 1219 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED 1220 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) 1221 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED 1222 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) { 1223 drm_dbg(dev, 1224 "original bpc %d pix encoding %d, changing to %d %d\n", 1225 pipe_ctx->stream->timing.display_color_depth, 1226 pipe_ctx->stream->timing.pixel_encoding, 1227 requestColorDepth, 1228 requestPixelEncoding); 1229 pipe_ctx->stream->timing.display_color_depth = requestColorDepth; 1230 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding; 1231 1232 dc_link_update_dsc_config(pipe_ctx); 1233 1234 aconnector->timing_changed = true; 1235 /* store current timing */ 1236 if (aconnector->timing_requested) 1237 *aconnector->timing_requested = pipe_ctx->stream->timing; 1238 else 1239 drm_err(dev, "timing storage failed\n"); 1240 1241 } 1242 1243 pipe_ctx->stream->test_pattern.type = test_pattern; 1244 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1245 1246 dc_link_dp_set_test_pattern( 1247 (struct dc_link *) link, 1248 test_pattern, 1249 test_pattern_color_space, 1250 NULL, 1251 NULL, 1252 0); 1253 1254 return false; 1255} 1256 1257void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 1258{ 1259 // TODO 1260} 1261 1262void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 1263{ 1264 /* TODO: add periodic detection implementation */ 1265} 1266 1267void dm_helpers_dp_mst_update_branch_bandwidth( 1268 struct dc_context *ctx, 1269 struct dc_link *link) 1270{ 1271 // TODO 1272} 1273 1274static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id) 1275{ 1276 bool ret_val = false; 1277 1278 switch (branch_dev_id) { 1279 case DP_BRANCH_DEVICE_ID_0060AD: 1280 case DP_BRANCH_DEVICE_ID_00E04C: 1281 case DP_BRANCH_DEVICE_ID_90CC24: 1282 ret_val = true; 1283 break; 1284 default: 1285 break; 1286 } 1287 1288 return ret_val; 1289} 1290 1291enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link) 1292{ 1293 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 1294 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 1295 1296 switch (dpcd_caps->dongle_type) { 1297 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 1298 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true && 1299 dpcd_caps->allow_invalid_MSA_timing_param == true && 1300 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id)) 1301 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST; 1302 break; 1303 default: 1304 break; 1305 } 1306 1307 return as_type; 1308} 1309