Lines Matching refs:dpcd
428 u8 dpcd[DP_RECEIVER_CAP_SIZE];
627 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
632 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
638 num, dpcd);
1443 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1454 if (it6505->dpcd[0] == 0) {
1461 link->revision = it6505->dpcd[0];
1462 link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);
1463 link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1465 if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1486 it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1494 it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1704 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1776 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
2292 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2348 if (it6505->dpcd[0] == 0) {
2349 it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2350 ARRAY_SIZE(it6505->dpcd));
2380 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2676 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2736 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3434 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));