1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright(c) 2016, Analogix Semiconductor. 4 * 5 * Based on anx7808 driver obtained from chromeos with copyright: 6 * Copyright(c) 2013, Google Inc. 7 */ 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/gpio/consumer.h> 11#include <linux/i2c.h> 12#include <linux/interrupt.h> 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/of_irq.h> 16#include <linux/of_platform.h> 17#include <linux/regmap.h> 18#include <linux/regulator/consumer.h> 19#include <linux/types.h> 20 21#include <drm/display/drm_dp_helper.h> 22#include <drm/drm_atomic_helper.h> 23#include <drm/drm_bridge.h> 24#include <drm/drm_crtc.h> 25#include <drm/drm_edid.h> 26#include <drm/drm_print.h> 27#include <drm/drm_probe_helper.h> 28 29#include "analogix-anx78xx.h" 30 31#define I2C_NUM_ADDRESSES 5 32#define I2C_IDX_TX_P0 0 33#define I2C_IDX_TX_P1 1 34#define I2C_IDX_TX_P2 2 35#define I2C_IDX_RX_P0 3 36#define I2C_IDX_RX_P1 4 37 38#define XTAL_CLK 270 /* 27M */ 39 40static const u8 anx7808_i2c_addresses[] = { 41 [I2C_IDX_TX_P0] = 0x78, 42 [I2C_IDX_TX_P1] = 0x7a, 43 [I2C_IDX_TX_P2] = 0x72, 44 [I2C_IDX_RX_P0] = 0x7e, 45 [I2C_IDX_RX_P1] = 0x80, 46}; 47 48static const u8 anx781x_i2c_addresses[] = { 49 [I2C_IDX_TX_P0] = 0x70, 50 [I2C_IDX_TX_P1] = 0x7a, 51 [I2C_IDX_TX_P2] = 0x72, 52 [I2C_IDX_RX_P0] = 0x7e, 53 [I2C_IDX_RX_P1] = 0x80, 54}; 55 56struct anx78xx_platform_data { 57 struct regulator *dvdd10; 58 struct gpio_desc *gpiod_hpd; 59 struct gpio_desc *gpiod_pd; 60 struct gpio_desc *gpiod_reset; 61 62 int hpd_irq; 63 int intp_irq; 64}; 65 66struct anx78xx { 67 struct drm_dp_aux aux; 68 struct drm_bridge bridge; 69 struct i2c_client *client; 70 struct edid *edid; 71 struct drm_connector connector; 72 struct anx78xx_platform_data pdata; 73 struct mutex lock; 74 75 /* 76 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2, 77 * RX_P0 and RX_P1. 78 */ 79 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES]; 80 struct regmap *map[I2C_NUM_ADDRESSES]; 81 82 u16 chipid; 83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 84 85 bool powered; 86}; 87 88static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c) 89{ 90 return container_of(c, struct anx78xx, connector); 91} 92 93static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge) 94{ 95 return container_of(bridge, struct anx78xx, bridge); 96} 97 98static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask) 99{ 100 return regmap_update_bits(map, reg, mask, mask); 101} 102 103static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask) 104{ 105 return regmap_update_bits(map, reg, mask, 0); 106} 107 108static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux, 109 struct drm_dp_aux_msg *msg) 110{ 111 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux); 112 return anx_dp_aux_transfer(anx78xx->map[I2C_IDX_TX_P0], msg); 113} 114 115static int anx78xx_set_hpd(struct anx78xx *anx78xx) 116{ 117 int err; 118 119 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], 120 SP_TMDS_CTRL_BASE + 7, SP_PD_RT); 121 if (err) 122 return err; 123 124 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, 125 SP_HPD_OUT); 126 if (err) 127 return err; 128 129 return 0; 130} 131 132static int anx78xx_clear_hpd(struct anx78xx *anx78xx) 133{ 134 int err; 135 136 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, 137 SP_HPD_OUT); 138 if (err) 139 return err; 140 141 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 142 SP_TMDS_CTRL_BASE + 7, SP_PD_RT); 143 if (err) 144 return err; 145 146 return 0; 147} 148 149static const struct reg_sequence tmds_phy_initialization[] = { 150 { SP_TMDS_CTRL_BASE + 1, 0x90 }, 151 { SP_TMDS_CTRL_BASE + 2, 0xa9 }, 152 { SP_TMDS_CTRL_BASE + 6, 0x92 }, 153 { SP_TMDS_CTRL_BASE + 7, 0x80 }, 154 { SP_TMDS_CTRL_BASE + 20, 0xf2 }, 155 { SP_TMDS_CTRL_BASE + 22, 0xc4 }, 156 { SP_TMDS_CTRL_BASE + 23, 0x18 }, 157}; 158 159static int anx78xx_rx_initialization(struct anx78xx *anx78xx) 160{ 161 int err; 162 163 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, 164 SP_AUD_MUTE | SP_VID_MUTE); 165 if (err) 166 return err; 167 168 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG, 169 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN | 170 SP_DIGITAL_CKDT_EN); 171 if (err) 172 return err; 173 174 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 175 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST | 176 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST); 177 if (err) 178 return err; 179 180 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], 181 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST | 182 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST); 183 if (err) 184 return err; 185 186 /* Sync detect change, GP set mute */ 187 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 188 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) | 189 BIT(6)); 190 if (err) 191 return err; 192 193 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 194 SP_AUD_EXCEPTION_ENABLE_BASE + 3, 195 SP_AEC_EN21); 196 if (err) 197 return err; 198 199 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG, 200 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN); 201 if (err) 202 return err; 203 204 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], 205 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL); 206 if (err) 207 return err; 208 209 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 210 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT); 211 if (err) 212 return err; 213 214 /* Enable DDC stretch */ 215 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 216 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR); 217 if (err) 218 return err; 219 220 /* TMDS phy initialization */ 221 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0], 222 tmds_phy_initialization, 223 ARRAY_SIZE(tmds_phy_initialization)); 224 if (err) 225 return err; 226 227 err = anx78xx_clear_hpd(anx78xx); 228 if (err) 229 return err; 230 231 return 0; 232} 233 234static const u8 dp_tx_output_precise_tune_bits[20] = { 235 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f, 236 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, 237 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e, 238}; 239 240static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx) 241{ 242 int err; 243 244 /* 245 * REVISIT : It is writing to a RESERVED bits in Analog Control 0 246 * register. 247 */ 248 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG, 249 0x02); 250 if (err) 251 return err; 252 253 /* 254 * Write DP TX output emphasis precise tune bits. 255 */ 256 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1], 257 SP_DP_TX_LT_CTRL0_REG, 258 dp_tx_output_precise_tune_bits, 259 ARRAY_SIZE(dp_tx_output_precise_tune_bits)); 260 261 if (err) 262 return err; 263 264 return 0; 265} 266 267static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx) 268{ 269 unsigned int value; 270 int err; 271 272 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2], 273 SP_ANALOG_DEBUG2_REG, 274 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS, 275 SP_XTAL_FRQ_27M); 276 if (err) 277 return err; 278 279 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG, 280 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK); 281 if (err) 282 return err; 283 284 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG, 285 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10)); 286 if (err) 287 return err; 288 289 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 290 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff); 291 if (err) 292 return err; 293 294 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 295 SP_I2C_GEN_10US_TIMER1_REG, 296 (XTAL_CLK & 0xff00) >> 8); 297 if (err) 298 return err; 299 300 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG, 301 XTAL_CLK / 10 - 1); 302 if (err) 303 return err; 304 305 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], 306 SP_HDMI_US_TIMER_CTRL_REG, 307 &value); 308 if (err) 309 return err; 310 311 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], 312 SP_HDMI_US_TIMER_CTRL_REG, 313 (value & SP_MS_TIMER_MARGIN_10_8_MASK) | 314 ((((XTAL_CLK / 10) >> 1) - 2) << 3)); 315 if (err) 316 return err; 317 318 return 0; 319} 320 321static const struct reg_sequence otp_key_protect[] = { 322 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 }, 323 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 }, 324 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 }, 325}; 326 327static int anx78xx_tx_initialization(struct anx78xx *anx78xx) 328{ 329 int err; 330 331 /* Set terminal resistor to 50 ohm */ 332 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG, 333 0x30); 334 if (err) 335 return err; 336 337 /* Enable aux double diff output */ 338 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 339 SP_DP_AUX_CH_CTRL2_REG, 0x08); 340 if (err) 341 return err; 342 343 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 344 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN | 345 SP_AUTO_START); 346 if (err) 347 return err; 348 349 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0], 350 otp_key_protect, 351 ARRAY_SIZE(otp_key_protect)); 352 if (err) 353 return err; 354 355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 356 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP); 357 if (err) 358 return err; 359 360 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG, 361 SP_VID_VRES_TH); 362 if (err) 363 return err; 364 365 /* 366 * DP HDCP auto authentication wait timer (when downstream starts to 367 * auth, DP side will wait for this period then do auth automatically) 368 */ 369 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG, 370 0x00); 371 if (err) 372 return err; 373 374 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 375 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING); 376 if (err) 377 return err; 378 379 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 380 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG); 381 if (err) 382 return err; 383 384 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], 385 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS); 386 if (err) 387 return err; 388 389 err = anx78xx_xtal_clk_sel(anx78xx); 390 if (err) 391 return err; 392 393 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG, 394 SP_DEFER_CTRL_EN | 0x0c); 395 if (err) 396 return err; 397 398 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 399 SP_DP_POLLING_CTRL_REG, 400 SP_AUTO_POLLING_DISABLE); 401 if (err) 402 return err; 403 404 /* 405 * Short the link integrity check timer to speed up bstatus 406 * polling for HDCP CTS item 1A-07 407 */ 408 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 409 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d); 410 if (err) 411 return err; 412 413 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 414 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP); 415 if (err) 416 return err; 417 418 /* Power down the main link by default */ 419 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 420 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); 421 if (err) 422 return err; 423 424 err = anx78xx_link_phy_initialization(anx78xx); 425 if (err) 426 return err; 427 428 /* Gen m_clk with downspreading */ 429 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 430 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL); 431 if (err) 432 return err; 433 434 return 0; 435} 436 437static int anx78xx_enable_interrupts(struct anx78xx *anx78xx) 438{ 439 int err; 440 441 /* 442 * BIT0: INT pin assertion polarity: 1 = assert high 443 * BIT1: INT pin output type: 0 = push/pull 444 */ 445 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01); 446 if (err) 447 return err; 448 449 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], 450 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG); 451 if (err) 452 return err; 453 454 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG, 455 SP_TRAINING_FINISH); 456 if (err) 457 return err; 458 459 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG, 460 SP_CKDT_CHG | SP_SCDT_CHG); 461 if (err) 462 return err; 463 464 return 0; 465} 466 467static void anx78xx_poweron(struct anx78xx *anx78xx) 468{ 469 struct anx78xx_platform_data *pdata = &anx78xx->pdata; 470 int err; 471 472 if (WARN_ON(anx78xx->powered)) 473 return; 474 475 if (pdata->dvdd10) { 476 err = regulator_enable(pdata->dvdd10); 477 if (err) { 478 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n", 479 err); 480 return; 481 } 482 483 usleep_range(1000, 2000); 484 } 485 486 gpiod_set_value_cansleep(pdata->gpiod_reset, 1); 487 usleep_range(1000, 2000); 488 489 gpiod_set_value_cansleep(pdata->gpiod_pd, 0); 490 usleep_range(1000, 2000); 491 492 gpiod_set_value_cansleep(pdata->gpiod_reset, 0); 493 494 /* Power on registers module */ 495 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, 496 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); 497 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, 498 SP_REGISTER_PD | SP_TOTAL_PD); 499 500 anx78xx->powered = true; 501} 502 503static void anx78xx_poweroff(struct anx78xx *anx78xx) 504{ 505 struct anx78xx_platform_data *pdata = &anx78xx->pdata; 506 int err; 507 508 if (WARN_ON(!anx78xx->powered)) 509 return; 510 511 gpiod_set_value_cansleep(pdata->gpiod_reset, 1); 512 usleep_range(1000, 2000); 513 514 gpiod_set_value_cansleep(pdata->gpiod_pd, 1); 515 usleep_range(1000, 2000); 516 517 if (pdata->dvdd10) { 518 err = regulator_disable(pdata->dvdd10); 519 if (err) { 520 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n", 521 err); 522 return; 523 } 524 525 usleep_range(1000, 2000); 526 } 527 528 anx78xx->powered = false; 529} 530 531static int anx78xx_start(struct anx78xx *anx78xx) 532{ 533 int err; 534 535 /* Power on all modules */ 536 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], 537 SP_POWERDOWN_CTRL_REG, 538 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | 539 SP_LINK_PD); 540 541 err = anx78xx_enable_interrupts(anx78xx); 542 if (err) { 543 DRM_ERROR("Failed to enable interrupts: %d\n", err); 544 goto err_poweroff; 545 } 546 547 err = anx78xx_rx_initialization(anx78xx); 548 if (err) { 549 DRM_ERROR("Failed receiver initialization: %d\n", err); 550 goto err_poweroff; 551 } 552 553 err = anx78xx_tx_initialization(anx78xx); 554 if (err) { 555 DRM_ERROR("Failed transmitter initialization: %d\n", err); 556 goto err_poweroff; 557 } 558 559 /* 560 * This delay seems to help keep the hardware in a good state. Without 561 * it, there are times where it fails silently. 562 */ 563 usleep_range(10000, 15000); 564 565 return 0; 566 567err_poweroff: 568 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err); 569 anx78xx_poweroff(anx78xx); 570 571 return err; 572} 573 574static int anx78xx_init_pdata(struct anx78xx *anx78xx) 575{ 576 struct anx78xx_platform_data *pdata = &anx78xx->pdata; 577 struct device *dev = &anx78xx->client->dev; 578 579 /* 1.0V digital core power regulator */ 580 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10"); 581 if (IS_ERR(pdata->dvdd10)) { 582 if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER) 583 DRM_ERROR("DVDD10 regulator not found\n"); 584 585 return PTR_ERR(pdata->dvdd10); 586 } 587 588 /* GPIO for HPD */ 589 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN); 590 if (IS_ERR(pdata->gpiod_hpd)) 591 return PTR_ERR(pdata->gpiod_hpd); 592 593 /* GPIO for chip power down */ 594 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH); 595 if (IS_ERR(pdata->gpiod_pd)) 596 return PTR_ERR(pdata->gpiod_pd); 597 598 /* GPIO for chip reset */ 599 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 600 601 return PTR_ERR_OR_ZERO(pdata->gpiod_reset); 602} 603 604static int anx78xx_dp_link_training(struct anx78xx *anx78xx) 605{ 606 u8 dp_bw, dpcd[2]; 607 int err; 608 609 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, 610 0x0); 611 if (err) 612 return err; 613 614 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], 615 SP_POWERDOWN_CTRL_REG, 616 SP_TOTAL_PD); 617 if (err) 618 return err; 619 620 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw); 621 if (err < 0) 622 return err; 623 624 switch (dp_bw) { 625 case DP_LINK_BW_1_62: 626 case DP_LINK_BW_2_7: 627 case DP_LINK_BW_5_4: 628 break; 629 630 default: 631 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw); 632 return -EINVAL; 633 } 634 635 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, 636 SP_VIDEO_MUTE); 637 if (err) 638 return err; 639 640 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], 641 SP_VID_CTRL1_REG, SP_VIDEO_EN); 642 if (err) 643 return err; 644 645 /* Get DPCD info */ 646 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV, 647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); 648 if (err < 0) { 649 DRM_ERROR("Failed to read DPCD: %d\n", err); 650 return err; 651 } 652 653 /* Clear channel x SERDES power down */ 654 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 655 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); 656 if (err) 657 return err; 658 659 /* 660 * Power up the sink (DP_SET_POWER register is only available on DPCD 661 * v1.1 and later). 662 */ 663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { 664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]); 665 if (err < 0) { 666 DRM_ERROR("Failed to read DP_SET_POWER register: %d\n", 667 err); 668 return err; 669 } 670 671 dpcd[0] &= ~DP_SET_POWER_MASK; 672 dpcd[0] |= DP_SET_POWER_D0; 673 674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]); 675 if (err < 0) { 676 DRM_ERROR("Failed to power up DisplayPort link: %d\n", 677 err); 678 return err; 679 } 680 681 /* 682 * According to the DP 1.1 specification, a "Sink Device must 683 * exit the power saving state within 1 ms" (Section 2.5.3.1, 684 * Table 5-52, "Sink Control Field" (register 0x600). 685 */ 686 usleep_range(1000, 2000); 687 } 688 689 /* Possibly enable downspread on the sink */ 690 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 691 SP_DP_DOWNSPREAD_CTRL1_REG, 0); 692 if (err) 693 return err; 694 695 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { 696 DRM_DEBUG("Enable downspread on the sink\n"); 697 /* 4000PPM */ 698 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 699 SP_DP_DOWNSPREAD_CTRL1_REG, 8); 700 if (err) 701 return err; 702 703 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 704 DP_SPREAD_AMP_0_5); 705 if (err < 0) 706 return err; 707 } else { 708 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0); 709 if (err < 0) 710 return err; 711 } 712 713 /* Set the lane count and the link rate on the sink */ 714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) 715 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 716 SP_DP_SYSTEM_CTRL_BASE + 4, 717 SP_ENHANCED_MODE); 718 else 719 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 720 SP_DP_SYSTEM_CTRL_BASE + 4, 721 SP_ENHANCED_MODE); 722 if (err) 723 return err; 724 725 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 726 SP_DP_MAIN_LINK_BW_SET_REG, 727 anx78xx->dpcd[DP_MAX_LINK_RATE]); 728 if (err) 729 return err; 730 731 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd); 732 733 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) 734 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 735 736 err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd, 737 sizeof(dpcd)); 738 if (err < 0) { 739 DRM_ERROR("Failed to configure link: %d\n", err); 740 return err; 741 } 742 743 /* Start training on the source */ 744 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG, 745 SP_LT_EN); 746 if (err) 747 return err; 748 749 return 0; 750} 751 752static int anx78xx_config_dp_output(struct anx78xx *anx78xx) 753{ 754 int err; 755 756 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, 757 SP_VIDEO_MUTE); 758 if (err) 759 return err; 760 761 /* Enable DP output */ 762 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, 763 SP_VIDEO_EN); 764 if (err) 765 return err; 766 767 return 0; 768} 769 770static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx, 771 struct hdmi_avi_infoframe *frame) 772{ 773 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 774 int err; 775 776 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer)); 777 if (err < 0) { 778 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err); 779 return err; 780 } 781 782 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 783 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN); 784 if (err) 785 return err; 786 787 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2], 788 SP_INFOFRAME_AVI_DB1_REG, buffer, 789 frame->length); 790 if (err) 791 return err; 792 793 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 794 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD); 795 if (err) 796 return err; 797 798 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 799 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN); 800 if (err) 801 return err; 802 803 return 0; 804} 805 806static int anx78xx_get_downstream_info(struct anx78xx *anx78xx) 807{ 808 u8 value; 809 int err; 810 811 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value); 812 if (err < 0) { 813 DRM_ERROR("Get sink count failed %d\n", err); 814 return err; 815 } 816 817 if (!DP_GET_SINK_COUNT(value)) { 818 DRM_ERROR("Downstream disconnected\n"); 819 return -EIO; 820 } 821 822 return 0; 823} 824 825static int anx78xx_get_modes(struct drm_connector *connector) 826{ 827 struct anx78xx *anx78xx = connector_to_anx78xx(connector); 828 int err, num_modes = 0; 829 830 if (WARN_ON(!anx78xx->powered)) 831 return 0; 832 833 if (anx78xx->edid) 834 return drm_add_edid_modes(connector, anx78xx->edid); 835 836 mutex_lock(&anx78xx->lock); 837 838 err = anx78xx_get_downstream_info(anx78xx); 839 if (err) { 840 DRM_ERROR("Failed to get downstream info: %d\n", err); 841 goto unlock; 842 } 843 844 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc); 845 if (!anx78xx->edid) { 846 DRM_ERROR("Failed to read EDID\n"); 847 goto unlock; 848 } 849 850 err = drm_connector_update_edid_property(connector, 851 anx78xx->edid); 852 if (err) { 853 DRM_ERROR("Failed to update EDID property: %d\n", err); 854 goto unlock; 855 } 856 857 num_modes = drm_add_edid_modes(connector, anx78xx->edid); 858 859unlock: 860 mutex_unlock(&anx78xx->lock); 861 862 return num_modes; 863} 864 865static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = { 866 .get_modes = anx78xx_get_modes, 867}; 868 869static enum drm_connector_status anx78xx_detect(struct drm_connector *connector, 870 bool force) 871{ 872 struct anx78xx *anx78xx = connector_to_anx78xx(connector); 873 874 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd)) 875 return connector_status_disconnected; 876 877 return connector_status_connected; 878} 879 880static const struct drm_connector_funcs anx78xx_connector_funcs = { 881 .fill_modes = drm_helper_probe_single_connector_modes, 882 .detect = anx78xx_detect, 883 .destroy = drm_connector_cleanup, 884 .reset = drm_atomic_helper_connector_reset, 885 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 886 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 887}; 888 889static int anx78xx_bridge_attach(struct drm_bridge *bridge, 890 enum drm_bridge_attach_flags flags) 891{ 892 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 893 int err; 894 895 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 896 DRM_ERROR("Fix bridge driver to make connector optional!"); 897 return -EINVAL; 898 } 899 900 if (!bridge->encoder) { 901 DRM_ERROR("Parent encoder object not found"); 902 return -ENODEV; 903 } 904 905 /* Register aux channel */ 906 anx78xx->aux.name = "DP-AUX"; 907 anx78xx->aux.dev = &anx78xx->client->dev; 908 anx78xx->aux.drm_dev = bridge->dev; 909 anx78xx->aux.transfer = anx78xx_aux_transfer; 910 911 err = drm_dp_aux_register(&anx78xx->aux); 912 if (err < 0) { 913 DRM_ERROR("Failed to register aux channel: %d\n", err); 914 return err; 915 } 916 917 err = drm_connector_init(bridge->dev, &anx78xx->connector, 918 &anx78xx_connector_funcs, 919 DRM_MODE_CONNECTOR_DisplayPort); 920 if (err) { 921 DRM_ERROR("Failed to initialize connector: %d\n", err); 922 goto aux_unregister; 923 } 924 925 drm_connector_helper_add(&anx78xx->connector, 926 &anx78xx_connector_helper_funcs); 927 928 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD; 929 930 err = drm_connector_attach_encoder(&anx78xx->connector, 931 bridge->encoder); 932 if (err) { 933 DRM_ERROR("Failed to link up connector to encoder: %d\n", err); 934 goto connector_cleanup; 935 } 936 937 err = drm_connector_register(&anx78xx->connector); 938 if (err) { 939 DRM_ERROR("Failed to register connector: %d\n", err); 940 goto connector_cleanup; 941 } 942 943 return 0; 944connector_cleanup: 945 drm_connector_cleanup(&anx78xx->connector); 946aux_unregister: 947 drm_dp_aux_unregister(&anx78xx->aux); 948 return err; 949} 950 951static void anx78xx_bridge_detach(struct drm_bridge *bridge) 952{ 953 drm_dp_aux_unregister(&bridge_to_anx78xx(bridge)->aux); 954} 955 956static enum drm_mode_status 957anx78xx_bridge_mode_valid(struct drm_bridge *bridge, 958 const struct drm_display_info *info, 959 const struct drm_display_mode *mode) 960{ 961 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 962 return MODE_NO_INTERLACE; 963 964 /* Max 1200p at 5.4 Ghz, one lane */ 965 if (mode->clock > 154000) 966 return MODE_CLOCK_HIGH; 967 968 return MODE_OK; 969} 970 971static void anx78xx_bridge_disable(struct drm_bridge *bridge) 972{ 973 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 974 975 /* Power off all modules except configuration registers access */ 976 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, 977 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); 978} 979 980static void anx78xx_bridge_mode_set(struct drm_bridge *bridge, 981 const struct drm_display_mode *mode, 982 const struct drm_display_mode *adjusted_mode) 983{ 984 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 985 struct hdmi_avi_infoframe frame; 986 int err; 987 988 if (WARN_ON(!anx78xx->powered)) 989 return; 990 991 mutex_lock(&anx78xx->lock); 992 993 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 994 &anx78xx->connector, 995 adjusted_mode); 996 if (err) { 997 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err); 998 goto unlock; 999 } 1000 1001 err = anx78xx_send_video_infoframe(anx78xx, &frame); 1002 if (err) 1003 DRM_ERROR("Failed to send AVI infoframe: %d\n", err); 1004 1005unlock: 1006 mutex_unlock(&anx78xx->lock); 1007} 1008 1009static void anx78xx_bridge_enable(struct drm_bridge *bridge) 1010{ 1011 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 1012 int err; 1013 1014 err = anx78xx_start(anx78xx); 1015 if (err) { 1016 DRM_ERROR("Failed to initialize: %d\n", err); 1017 return; 1018 } 1019 1020 err = anx78xx_set_hpd(anx78xx); 1021 if (err) 1022 DRM_ERROR("Failed to set HPD: %d\n", err); 1023} 1024 1025static const struct drm_bridge_funcs anx78xx_bridge_funcs = { 1026 .attach = anx78xx_bridge_attach, 1027 .detach = anx78xx_bridge_detach, 1028 .mode_valid = anx78xx_bridge_mode_valid, 1029 .disable = anx78xx_bridge_disable, 1030 .mode_set = anx78xx_bridge_mode_set, 1031 .enable = anx78xx_bridge_enable, 1032}; 1033 1034static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data) 1035{ 1036 struct anx78xx *anx78xx = data; 1037 int err; 1038 1039 if (anx78xx->powered) 1040 return IRQ_HANDLED; 1041 1042 mutex_lock(&anx78xx->lock); 1043 1044 /* Cable is pulled, power on the chip */ 1045 anx78xx_poweron(anx78xx); 1046 1047 err = anx78xx_enable_interrupts(anx78xx); 1048 if (err) 1049 DRM_ERROR("Failed to enable interrupts: %d\n", err); 1050 1051 mutex_unlock(&anx78xx->lock); 1052 1053 return IRQ_HANDLED; 1054} 1055 1056static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq) 1057{ 1058 int err; 1059 1060 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq); 1061 1062 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG, 1063 irq); 1064 if (err) 1065 return err; 1066 1067 if (irq & SP_TRAINING_FINISH) { 1068 DRM_DEBUG_KMS("IRQ: hardware link training finished\n"); 1069 err = anx78xx_config_dp_output(anx78xx); 1070 } 1071 1072 return err; 1073} 1074 1075static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq) 1076{ 1077 bool event = false; 1078 int err; 1079 1080 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq); 1081 1082 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], 1083 SP_COMMON_INT_STATUS4_REG, irq); 1084 if (err) { 1085 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err); 1086 return event; 1087 } 1088 1089 if (irq & SP_HPD_LOST) { 1090 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n"); 1091 event = true; 1092 anx78xx_poweroff(anx78xx); 1093 /* Free cached EDID */ 1094 kfree(anx78xx->edid); 1095 anx78xx->edid = NULL; 1096 } else if (irq & SP_HPD_PLUG) { 1097 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n"); 1098 event = true; 1099 } 1100 1101 return event; 1102} 1103 1104static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq) 1105{ 1106 unsigned int value; 1107 int err; 1108 1109 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq); 1110 1111 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, 1112 irq); 1113 if (err) { 1114 DRM_ERROR("Write HDMI int 1 failed: %d\n", err); 1115 return; 1116 } 1117 1118 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) { 1119 DRM_DEBUG_KMS("IRQ: HDMI input detected\n"); 1120 1121 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], 1122 SP_SYSTEM_STATUS_REG, &value); 1123 if (err) { 1124 DRM_ERROR("Read system status reg failed: %d\n", err); 1125 return; 1126 } 1127 1128 if (!(value & SP_TMDS_CLOCK_DET)) { 1129 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n"); 1130 return; 1131 } 1132 1133 if (!(value & SP_TMDS_DE_DET)) { 1134 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n"); 1135 return; 1136 } 1137 1138 err = anx78xx_dp_link_training(anx78xx); 1139 if (err) 1140 DRM_ERROR("Failed to start link training: %d\n", err); 1141 } 1142} 1143 1144static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data) 1145{ 1146 struct anx78xx *anx78xx = data; 1147 bool event = false; 1148 unsigned int irq; 1149 int err; 1150 1151 mutex_lock(&anx78xx->lock); 1152 1153 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG, 1154 &irq); 1155 if (err) { 1156 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err); 1157 goto unlock; 1158 } 1159 1160 if (irq) 1161 anx78xx_handle_dp_int_1(anx78xx, irq); 1162 1163 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], 1164 SP_COMMON_INT_STATUS4_REG, &irq); 1165 if (err) { 1166 DRM_ERROR("Failed to read common interrupt 4 status: %d\n", 1167 err); 1168 goto unlock; 1169 } 1170 1171 if (irq) 1172 event = anx78xx_handle_common_int_4(anx78xx, irq); 1173 1174 /* Make sure we are still powered after handle HPD events */ 1175 if (!anx78xx->powered) 1176 goto unlock; 1177 1178 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, 1179 &irq); 1180 if (err) { 1181 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err); 1182 goto unlock; 1183 } 1184 1185 if (irq) 1186 anx78xx_handle_hdmi_int_1(anx78xx, irq); 1187 1188unlock: 1189 mutex_unlock(&anx78xx->lock); 1190 1191 if (event) 1192 drm_helper_hpd_irq_event(anx78xx->connector.dev); 1193 1194 return IRQ_HANDLED; 1195} 1196 1197static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx) 1198{ 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++) 1202 i2c_unregister_device(anx78xx->i2c_dummy[i]); 1203} 1204 1205static const struct regmap_config anx78xx_regmap_config = { 1206 .reg_bits = 8, 1207 .val_bits = 8, 1208}; 1209 1210static const u16 anx78xx_chipid_list[] = { 1211 0x7808, 1212 0x7812, 1213 0x7814, 1214 0x7816, 1215 0x7818, 1216}; 1217 1218static int anx78xx_i2c_probe(struct i2c_client *client) 1219{ 1220 struct anx78xx *anx78xx; 1221 struct anx78xx_platform_data *pdata; 1222 unsigned int i, idl, idh, version; 1223 const u8 *i2c_addresses; 1224 bool found = false; 1225 int err; 1226 1227 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL); 1228 if (!anx78xx) 1229 return -ENOMEM; 1230 1231 pdata = &anx78xx->pdata; 1232 1233 mutex_init(&anx78xx->lock); 1234 1235 anx78xx->bridge.of_node = client->dev.of_node; 1236 1237 anx78xx->client = client; 1238 i2c_set_clientdata(client, anx78xx); 1239 1240 err = anx78xx_init_pdata(anx78xx); 1241 if (err) { 1242 if (err != -EPROBE_DEFER) 1243 DRM_ERROR("Failed to initialize pdata: %d\n", err); 1244 1245 return err; 1246 } 1247 1248 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd); 1249 if (pdata->hpd_irq < 0) { 1250 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq); 1251 return -ENODEV; 1252 } 1253 1254 pdata->intp_irq = client->irq; 1255 if (!pdata->intp_irq) { 1256 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n"); 1257 return -ENODEV; 1258 } 1259 1260 /* Map slave addresses of ANX7814 */ 1261 i2c_addresses = device_get_match_data(&client->dev); 1262 for (i = 0; i < I2C_NUM_ADDRESSES; i++) { 1263 struct i2c_client *i2c_dummy; 1264 1265 i2c_dummy = i2c_new_dummy_device(client->adapter, 1266 i2c_addresses[i] >> 1); 1267 if (IS_ERR(i2c_dummy)) { 1268 err = PTR_ERR(i2c_dummy); 1269 DRM_ERROR("Failed to reserve I2C bus %02x: %d\n", 1270 i2c_addresses[i], err); 1271 goto err_unregister_i2c; 1272 } 1273 1274 anx78xx->i2c_dummy[i] = i2c_dummy; 1275 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i], 1276 &anx78xx_regmap_config); 1277 if (IS_ERR(anx78xx->map[i])) { 1278 err = PTR_ERR(anx78xx->map[i]); 1279 DRM_ERROR("Failed regmap initialization %02x\n", 1280 i2c_addresses[i]); 1281 goto err_unregister_i2c; 1282 } 1283 } 1284 1285 /* Look for supported chip ID */ 1286 anx78xx_poweron(anx78xx); 1287 1288 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG, 1289 &idl); 1290 if (err) 1291 goto err_poweroff; 1292 1293 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG, 1294 &idh); 1295 if (err) 1296 goto err_poweroff; 1297 1298 anx78xx->chipid = (u8)idl | ((u8)idh << 8); 1299 1300 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG, 1301 &version); 1302 if (err) 1303 goto err_poweroff; 1304 1305 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) { 1306 if (anx78xx->chipid == anx78xx_chipid_list[i]) { 1307 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n", 1308 anx78xx->chipid, version); 1309 found = true; 1310 break; 1311 } 1312 } 1313 1314 if (!found) { 1315 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n", 1316 anx78xx->chipid, version); 1317 err = -ENODEV; 1318 goto err_poweroff; 1319 } 1320 1321 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL, 1322 anx78xx_hpd_threaded_handler, 1323 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1324 "anx78xx-hpd", anx78xx); 1325 if (err) { 1326 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n", 1327 err); 1328 goto err_poweroff; 1329 } 1330 1331 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL, 1332 anx78xx_intp_threaded_handler, 1333 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1334 "anx78xx-intp", anx78xx); 1335 if (err) { 1336 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err); 1337 goto err_poweroff; 1338 } 1339 1340 anx78xx->bridge.funcs = &anx78xx_bridge_funcs; 1341 1342 drm_bridge_add(&anx78xx->bridge); 1343 1344 /* If cable is pulled out, just poweroff and wait for HPD event */ 1345 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd)) 1346 anx78xx_poweroff(anx78xx); 1347 1348 return 0; 1349 1350err_poweroff: 1351 anx78xx_poweroff(anx78xx); 1352 1353err_unregister_i2c: 1354 unregister_i2c_dummy_clients(anx78xx); 1355 return err; 1356} 1357 1358static void anx78xx_i2c_remove(struct i2c_client *client) 1359{ 1360 struct anx78xx *anx78xx = i2c_get_clientdata(client); 1361 1362 drm_bridge_remove(&anx78xx->bridge); 1363 1364 unregister_i2c_dummy_clients(anx78xx); 1365 1366 kfree(anx78xx->edid); 1367} 1368 1369static const struct of_device_id anx78xx_match_table[] = { 1370 { .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses }, 1371 { .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses }, 1372 { .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses }, 1373 { .compatible = "analogix,anx7816", .data = anx781x_i2c_addresses }, 1374 { .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses }, 1375 { /* sentinel */ }, 1376}; 1377MODULE_DEVICE_TABLE(of, anx78xx_match_table); 1378 1379static struct i2c_driver anx78xx_driver = { 1380 .driver = { 1381 .name = "anx7814", 1382 .of_match_table = anx78xx_match_table, 1383 }, 1384 .probe = anx78xx_i2c_probe, 1385 .remove = anx78xx_i2c_remove, 1386}; 1387module_i2c_driver(anx78xx_driver); 1388 1389MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver"); 1390MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); 1391MODULE_LICENSE("GPL v2"); 1392