/linux-master/kernel/sched/ |
H A D | fair.c | 3821 u32 divider = get_pelt_divider(&se->avg); local 3823 se->avg.load_avg = div_u64(se_weight(se) * se->avg.load_sum, divider); 4033 * _avg must be null when _sum are null because _avg = _sum / divider 4280 u32 new_sum, divider; local 4290 divider = get_pelt_divider(&cfs_rq->avg); 4295 new_sum = se->avg.util_avg * divider; 4312 u32 new_sum, divider; local 4322 divider = get_pelt_divider(&cfs_rq->avg); 4326 new_sum = se->avg.runnable_avg * divider; 4345 u32 divider; local 4592 u32 divider = get_pelt_divider(&cfs_rq->avg); local 4661 u32 divider = get_pelt_divider(&cfs_rq->avg); local [all...] |
/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_cdclk.c | 70 * - CD2X divider update. Single pipe can be active as the divider update 523 * CCK divider into the Punit register. 637 u32 divider; local 639 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 642 /* adjust cdclk divider */ 645 val |= divider; 649 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 1428 /* 2 * cd2x divider */ 1605 u32 divider; local 3407 int divider, fraction; local [all...] |
H A D | intel_display.c | 149 int divider; local 152 divider = val & CCK_FREQUENCY_VALUES; 155 (divider << CCK_FREQUENCY_STATUS_SHIFT), 158 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); 3686 * The PLL needs to be enabled with a valid divider
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H A D | intel_dpll_mgr.c | 1461 unsigned int p; /* chosen divider */ 1471 unsigned int divider) 1485 ctx->p = divider; 1493 ctx->p = divider; 1664 * have found the definitive divider, we can't 1674 * If a solution is found with an even divider, prefer 1727 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); 2552 * Program half of the nominal DCO divider fraction value. 1468 skl_wrpll_try_divider(struct skl_wrpll_context *ctx, u64 central_freq, u64 dco_freq, unsigned int divider) argument
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/linux-master/include/linux/firmware/ |
H A D | xlnx-zynqmp.h | 542 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); 543 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); 643 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) argument 648 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) argument
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/linux-master/drivers/net/ethernet/mediatek/ |
H A D | mtk_eth_soc.c | 819 unsigned int max_clk = 2500000, divider; local 859 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 866 val = FIELD_PREP(PPSC_MDC_CFG, divider); 871 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | opp.h | 255 uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ member in struct:hw_adjustment_range
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/linux-master/drivers/firmware/xilinx/ |
H A D | zynqmp.c | 625 * zynqmp_pm_clock_setdivider() - Set the clock divider for given id 627 * @divider: divider value 629 * This function is used by master to set divider for any clock 634 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) argument 636 return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, NULL, 2, clock_id, divider); 641 * zynqmp_pm_clock_getdivider() - Get the clock divider for given id 643 * @divider: divider value 645 * This function is used by master to get divider value 650 zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) argument [all...] |
/linux-master/drivers/clk/ti/ |
H A D | divider.c | 32 static void _setup_mask(struct clk_omap_divider *divider) argument 38 if (divider->table) { 41 for (clkt = divider->table; clkt->div; clkt++) 45 max_val = divider->max; 47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && 48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) 52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 57 divider->mask = (1 << fls(mask)) - 1; 60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) argument 62 if (divider 82 _get_val(struct clk_omap_divider *divider, u8 div) argument 96 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local 130 _is_valid_div(struct clk_omap_divider *divider, unsigned int div) argument 171 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local 238 struct clk_omap_divider *divider; local 274 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local 291 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local 331 ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, u8 flags, struct clk_omap_divider *divider) argument 434 _populate_divider_min_max(struct device_node *node, struct clk_omap_divider *divider) argument [all...] |
/linux-master/drivers/i2c/busses/ |
H A D | i2c-mpc.c | 105 u16 divider; member in struct:mpc_i2c_divider 158 * 1. Set up the frequency divider and sampling rate. 244 u32 divider; local 253 /* Determine divider value */ 254 divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock; 265 if (div->divider >= divider) 269 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider; 431 u32 divider; local 440 divider [all...] |
/linux-master/drivers/clk/xilinx/ |
H A D | clk-xlnx-clock-wizard.c | 111 /* Extract divider instance from clock hardware instance */ 147 * struct clk_wzrd_divider - clock divider specific to clk_wzrd 150 * @base: base address of register containing the divider 151 * @offset: offset address of register containing the divider 152 * @shift: shift to the divider bit field 153 * @width: width of the divider bit field 154 * @flags: clk_wzrd divider flags 155 * @table: array of value/divider pairs, last entry should have div = 0 157 * @d: value of the common divider 158 * @o: value of the leaf divider 194 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 219 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 233 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 281 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 337 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 375 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 410 clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr) argument 434 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 499 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 535 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 551 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 567 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 585 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 651 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 704 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local 720 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local [all...] |
/linux-master/drivers/clk/qcom/ |
H A D | Makefile | 11 clk-qcom-y += clk-regmap-divider.o
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/linux-master/drivers/clk/imx/ |
H A D | clk-composite-8m.c | 31 struct clk_divider *divider = to_clk_divider(hw); local 36 prediv_value = readl(divider->reg) >> divider->shift; 37 prediv_value &= clk_div_mask(divider->width); 40 NULL, divider->flags, 41 divider->width); 43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; 47 divider->flags, PCG_DIV_WIDTH); 95 struct clk_divider *divider = to_clk_divider(hw); local 107 spin_lock_irqsave(divider 127 struct clk_divider *divider = to_clk_divider(hw); local [all...] |
/linux-master/drivers/clk/ |
H A D | clk-cdce925.c | 349 /* Disable clock by setting divider to "0" */ 366 unsigned long divider; local 373 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 374 if (divider > 0x7F) 375 divider = 0x7F; 377 return (u16)divider; 427 u16 divider = cdce925_calc_divider(rate, l_parent_rate); local 429 if (l_parent_rate / divider != rate) { 431 divider = cdce925_calc_divider(rate, l_parent_rate); 435 if (divider) 462 unsigned long divider; local 480 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); local [all...] |
/linux-master/drivers/mmc/host/ |
H A D | mxcmmc.c | 788 unsigned int divider; local 793 for (divider = 1; divider <= 0xF; divider++) { 796 x = (clk_in / (divider + 1)); 804 if (divider < 0x10) 813 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); 815 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 816 prescaler, divider, clk_in, clk_ios);
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/linux-master/drivers/hwmon/ |
H A D | ltc4282.c | 1350 const char *divider; local 1464 ÷r); 1467 ARRAY_SIZE(ltc4282_dividers), divider); 1470 "Invalid val(%s) for adi,overvoltage-divider\n", 1471 divider); 1479 ÷r); 1482 ARRAY_SIZE(ltc4282_dividers), divider); 1485 "Invalid val(%s) for adi,undervoltage-divider\n", 1486 divider);
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | trinity_dpm.c | 565 u32 index, u32 divider) 572 value |= DS_DIV(divider); 577 u32 index, u32 divider) 584 value |= DS_SH_DIV(divider); 1784 u32 divider; local 1787 divider = did * 25; 1789 divider = (did - 64) * 50 + 1600; 1791 divider = (did - 96) * 100 + 3200; 1793 divider = 128 * 100; 1797 return ((pi->sys_info.dentist_vco_freq * 100) + (divider 564 trinity_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument 576 trinity_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument [all...] |
H A D | sumo_dpm.c | 472 u32 index, u32 divider) 479 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK); 482 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK); 485 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK); 488 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK); 492 u32 index, u32 divider) 500 dpm_ctrl |= (divider << (index * 3)); 506 u32 index, u32 divider) 514 dpm_ctrl |= (divider << (index * 3)); 471 sumo_set_divider_value(struct radeon_device *rdev, u32 index, u32 divider) argument 491 sumo_set_ds_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument 505 sumo_set_ss_dividers(struct radeon_device *rdev, u32 index, u32 divider) argument
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H A D | r600_dpm.c | 477 u32 index, u32 divider) 480 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK); 484 u32 index, u32 divider) 487 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK); 491 u32 index, u32 divider) 494 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK); 476 r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev, u32 index, u32 divider) argument 483 r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev, u32 index, u32 divider) argument 490 r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev, u32 index, u32 divider) argument
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H A D | r600_dpm.h | 180 u32 index, u32 divider); 182 u32 index, u32 divider); 184 u32 index, u32 divider);
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/linux-master/drivers/soc/qcom/ |
H A D | qcom-geni-se.c | 626 unsigned int divider; local 637 divider = DIV_ROUND_UP(tbl[i], req_freq); 638 new_delta = req_freq - tbl[i] / divider;
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/linux-master/drivers/clocksource/ |
H A D | arm_arch_timer.c | 915 static void arch_timer_evtstrm_enable(unsigned int divider) argument 920 /* ECV is likely to require a large divider. Use the EVNTIS flag. */ 921 if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) { 923 divider -= 8; 927 divider = min(divider, 15U); 929 /* Set the divider and enable virtual event stream */ 930 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) 943 * of the counter, use half the frequency when computing the divider.
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/linux-master/drivers/iio/imu/inv_mpu6050/ |
H A D | inv_mpu_ring.c | 115 fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
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/linux-master/arch/sh/boards/mach-ecovec24/ |
H A D | setup.c | 514 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */ 519 .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
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/linux-master/drivers/mfd/ |
H A D | sm501.c | 392 int divider; member in struct:sm501_clock 411 int divider; local 416 try divider 5 for panel only.*/ 418 for (divider = 1; divider <= max_div; divider += 2) { 422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; 431 clock->divider = divider; 476 return clock->mclk / (clock->divider << cloc [all...] |