clk/xilinx/clk-xlnx-clock-wizard.c

111 /* Extract divider instance from clock hardware instance */
147  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150  * @base:	base address of register containing the divider
151  * @offset:	offset address of register containing the divider
152  * @shift:	shift to the divider bit field
153  * @width:	width of the divider bit field
154  * @flags:	clk_wzrd divider flags
155  * @table:	array of value/divider pairs, last entry should have div = 0
157  * @d:	value of the common divider
158  * @o:	value of the leaf divider
172 	spinlock_t *lock;  /* divider lock */
194 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
195 	void __iomem *div_addr = divider->base + divider->offset;
219 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
220 	void __iomem *div_addr = divider->base + divider->offset;
223 	val = readl(div_addr) >> divider->shift;
224 	val &= div_mask(divider->width);
226 	return divider_recalc_rate(hw, parent_rate, val, divider->table,
227 			divider->flags, divider->width);
233 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
234 	void __iomem *div_addr = divider->base + divider->offset;
239 	spin_lock_irqsave(divider->lock, flags);
259 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
267 	       divider->base + WZRD_DR_INIT_VERSAL_OFFSET);
270 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
274 	spin_unlock_irqrestore(divider->lock, flags);
281 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
282 	void __iomem *div_addr = divider->base + divider->offset;
287 	spin_lock_irqsave(divider->lock, flags);
299 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
307 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
309 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
312 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
316 	spin_unlock_irqrestore(divider->lock, flags);
337 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
360 						divider->m = m;
361 						divider->d = d;
362 						divider->o = o;
375 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
398 						divider->m = m;
399 						divider->d = d;
400 						divider->o = o;
410 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)
416 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
425 	return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
434 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
442 	writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));
444 	m = divider->m;
447 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
455 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
458 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
461 	value2 = divider->d;
465 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
468 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
470 	value = divider->o;
472 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
486 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
489 	writel(regval, divider->base + WZRD_CLK_CFG_REG(1,
491 	div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;
493 	return clk_wzrd_reconfig(divider, div_addr);
499 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
509 	vco_freq = DIV_ROUND_CLOSEST(parent_rate * divider->m, divider->d);
521 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));
523 	reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |
524 	      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);
525 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));
526 	writel(divider->o, divider->base + WZRD_CLK_CFG_REG(0, 2));
527 	writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));
528 	div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;
529 	return clk_wzrd_reconfig(divider, div_addr);
535 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
539 	spin_lock_irqsave(divider->lock, flags);
543 	spin_unlock_irqrestore(divider->lock, flags);
551 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
555 	spin_lock_irqsave(divider->lock, flags);
559 	spin_unlock_irqrestore(divider->lock, flags);
567 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
570 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));
573 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));
578 	return divider_recalc_rate(hw, parent_rate * m, div, divider->table,
579 		divider->flags, divider->width);
585 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
589 	edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &
592 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));
600 	regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &
603 		regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))
612 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));
617 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));
632 	edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &
634 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
644 	return divider_recalc_rate(hw, parent_rate, div, divider->table,
645 			divider->flags, divider->width);
651 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
660 	m = divider->m;
661 	d = divider->d;
662 	o = divider->o;
665 	int_freq =  divider_recalc_rate(hw, *prate * m, div, divider->table,
666 					divider->flags, divider->width);
704 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
705 	void __iomem *div_addr = divider->base + divider->offset;
708 	div = val & div_mask(divider->width);
720 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
721 	void __iomem *div_addr = divider->base + divider->offset;
738 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
746 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
748 	       divider->base + WZRD_DR_INIT_REG_OFFSET);
751 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
1137 		dev_err(&pdev->dev, "unable to register divider clock\n");
1186 				"unable to register divider clock\n");