Searched refs:control_reg (Results 1 - 25 of 31) sorted by last modified time

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/linux-master/drivers/tty/serial/
H A Dpmac_zilog.c1365 uap->control_reg = uap->port.membase;
1366 uap->data_reg = uap->control_reg + 0x10;
1451 iounmap(uap->control_reg);
1642 uap->control_reg = uap->port.membase;
1643 uap->data_reg = uap->control_reg + 4;
H A Dpmac_zilog.h54 volatile u8 __iomem *control_reg; member in struct:uart_pmac_port
78 writeb(reg, port->control_reg);
79 return readb(port->control_reg);
85 writeb(reg, port->control_reg);
86 writeb(value, port->control_reg);
101 (void)readb(port->control_reg);
/linux-master/drivers/staging/fieldbus/anybuss/
H A Darcx-anybus.c45 u8 control_reg; member in struct:controller_priv
55 * cd->control_reg
58 cd->control_reg &= ~rst_bit;
60 cd->control_reg |= rst_bit;
61 writeb(cd->control_reg, cd->cpld_base + CPLD_CONTROL);
/linux-master/include/linux/clk/
H A Dti.h35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
56 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
57 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
58 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
65 * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
67 * @control_reg
93 struct clk_omap_reg control_reg; member in struct:dpll_data
/linux-master/drivers/clk/ti/
H A Dapll.c55 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
58 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
94 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
97 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
108 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
212 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
241 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
267 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
270 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
297 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
[all...]
H A Ddpll3xxx.c54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
373 ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
399 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
402 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
456 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
472 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
860 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
884 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
[all...]
H A Ddpll.c318 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
/linux-master/sound/pci/echoaudio/
H A Dechoaudio_3g.c145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) argument
147 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
151 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
155 control_reg |= E3G_SPDIF_SAMPLE_RATE0;
158 control_reg |= E3G_SPDIF_SAMPLE_RATE1;
163 control_reg |= E3G_SPDIF_PRO_MODE;
166 control_reg |= E3G_SPDIF_NOT_AUDIO;
168 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
171 return control_reg;
179 u32 control_reg; local
260 u32 control_reg, clock, base_rate, frq_reg; local
330 u32 control_reg, clocks_from_dsp; local
378 u32 control_reg; local
[all...]
H A Dmona_dsp.c119 u32 control_reg; local
152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
153 err = write_control_reg(chip, control_reg, true);
200 u32 control_reg, clock; local
246 control_reg = le32_to_cpu(chip->comm_page->control_register);
247 control_reg &= GML_CLOCK_CLEAR_MASK;
248 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
263 if (control_reg & GML_SPDIF_PRO_MODE)
288 control_reg |= clock;
295 return write_control_reg(chip, control_reg, force_writ
302 u32 control_reg, clocks_from_dsp; local
363 u32 control_reg; local
[all...]
H A Dmia_dsp.c111 u32 control_reg; local
115 control_reg = MIA_96000;
118 control_reg = MIA_88200;
121 control_reg = MIA_48000;
124 control_reg = MIA_44100;
127 control_reg = MIA_32000;
137 control_reg |= MIA_SPDIF;
140 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
145 chip->comm_page->control_register = cpu_to_le32(control_reg);
H A Dlayla24_dsp.c162 u32 control_reg, clock, base_rate; local
179 control_reg = le32_to_cpu(chip->comm_page->control_register);
180 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
197 if (control_reg & GML_SPDIF_PRO_MODE)
222 control_reg |= GML_DOUBLE_SPEED_MODE;
240 control_reg |= clock;
245 "set_sample_rate: %d clock %d\n", rate, control_reg);
247 return write_control_reg(chip, control_reg, false);
254 u32 control_reg, clocks_from_dsp; local
257 control_reg
335 u32 control_reg; local
[all...]
H A Dgina24_dsp.c126 u32 control_reg; local
156 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
157 err = write_control_reg(chip, control_reg, true);
166 u32 control_reg, clock; local
184 control_reg = le32_to_cpu(chip->comm_page->control_register);
185 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
200 if (control_reg & GML_SPDIF_PRO_MODE)
225 control_reg |= clock;
231 return write_control_reg(chip, control_reg, false);
238 u32 control_reg, clocks_from_ds local
286 u32 control_reg; local
[all...]
H A Dindigodj_dsp.c94 u32 control_reg; local
98 control_reg = MIA_96000;
101 control_reg = MIA_88200;
104 control_reg = MIA_48000;
107 control_reg = MIA_44100;
110 control_reg = MIA_32000;
119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
124 chip->comm_page->control_register = cpu_to_le32(control_reg);
H A Dindigo_dsp.c94 u32 control_reg; local
98 control_reg = MIA_96000;
101 control_reg = MIA_88200;
104 control_reg = MIA_48000;
107 control_reg = MIA_44100;
110 control_reg = MIA_32000;
119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
124 chip->comm_page->control_register = cpu_to_le32(control_reg);
H A Dechoaudio_gml.c158 u32 control_reg; local
162 control_reg = le32_to_cpu(chip->comm_page->control_register);
163 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK;
166 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT |
170 control_reg |= GML_SPDIF_PRO_MODE;
174 control_reg |= GML_SPDIF_SAMPLE_RATE0 |
178 control_reg |= GML_SPDIF_SAMPLE_RATE0;
181 control_reg |= GML_SPDIF_SAMPLE_RATE1;
188 control_reg |= GML_SPDIF_SAMPLE_RATE0 |
192 control_reg |
[all...]
/linux-master/drivers/net/ethernet/ti/
H A Dcpsw_new.c551 u32 control_reg; local
560 control_reg = readl(&cpsw->regs->control);
561 control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
562 writel(control_reg, &cpsw->regs->control);
H A Dcpsw.c680 u32 control_reg; local
690 control_reg = readl(&cpsw->regs->control);
691 control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
692 writel(control_reg, &cpsw->regs->control);
/linux-master/drivers/regulator/
H A Dti-abb-regulator.c78 * @control_reg: control register of ABB block
96 void __iomem *control_reg; member in struct:ti_abb
261 ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, abb->control_reg);
272 ti_abb_rmw(regs->opp_change_mask, 1, abb->control_reg);
717 abb->control_reg = abb->base + abb->regs->control_off;
720 abb->control_reg = devm_platform_ioremap_resource_byname(pdev, "control-address");
721 if (IS_ERR(abb->control_reg))
722 return PTR_ERR(abb->control_reg);
H A Das3722-regulator.c55 u32 control_reg; member in struct:as3722_register_mapping
85 .control_reg = AS3722_SD0_CONTROL_REG,
97 .control_reg = AS3722_SD1_CONTROL_REG,
110 .control_reg = AS3722_SD23_CONTROL_REG,
124 .control_reg = AS3722_SD23_CONTROL_REG,
138 .control_reg = AS3722_SD4_CONTROL_REG,
152 .control_reg = AS3722_SD5_CONTROL_REG,
165 .control_reg = AS3722_SD6_CONTROL_REG,
427 if (!as3722_reg_lookup[id].control_reg)
430 ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg,
[all...]
H A Danatop-regulator.c166 u32 control_reg; local
203 ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg);
247 rdesc->vsel_reg = control_reg;
258 if (control_reg && sreg->delay_bit_width) {
300 rdesc->enable_reg = control_reg;
/linux-master/drivers/i2c/busses/
H A Di2c-mt65xx.c554 u16 control_reg; local
632 control_reg = I2C_CONTROL_ACKERR_DET_EN |
635 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
637 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
1002 u16 control_reg; local
1042 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
1045 control_reg |= I2C_CONTROL_RS;
1048 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
1050 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
/linux-master/drivers/clk/
H A Dclk-palmas.c26 unsigned int control_reg; member in struct:palmas_clk32k_desc
58 cinfo->clk_desc->control_reg,
63 cinfo->clk_desc->control_reg, ret);
83 cinfo->clk_desc->control_reg,
87 cinfo->clk_desc->control_reg, ret);
100 cinfo->clk_desc->control_reg, &val);
103 cinfo->clk_desc->control_reg, ret);
129 .control_reg = PALMAS_CLK32KG_CTRL,
145 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
202 cinfo->clk_desc->control_reg,
[all...]
/linux-master/drivers/watchdog/
H A Dts72xx_wdt.c29 /* priv->control_reg */
43 void __iomem *control_reg; member in struct:ts72xx_wdt_priv
54 writeb(priv->regval, priv->control_reg);
64 writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg);
132 priv->control_reg = devm_platform_ioremap_resource(pdev, 0);
133 if (IS_ERR(priv->control_reg))
134 return PTR_ERR(priv->control_reg);
/linux-master/drivers/power/supply/
H A Dds2781_battery.c359 u8 *control_reg)
361 return ds2781_read8(dev_info, control_reg, DS2781_CONTROL);
365 u8 control_reg)
369 ret = ds2781_write(dev_info, &control_reg,
450 u8 control_reg; local
455 ret = ds2781_get_control_register(dev_info, &control_reg);
460 !!(control_reg & DS2781_CONTROL_PMOD));
469 u8 control_reg, new_setting; local
474 ret = ds2781_get_control_register(dev_info, &control_reg);
488 control_reg |
358 ds2781_get_control_register(struct ds2781_device_info *dev_info, u8 *control_reg) argument
364 ds2781_set_control_register(struct ds2781_device_info *dev_info, u8 control_reg) argument
[all...]
H A Dds2780_battery.c357 u8 *control_reg)
359 return ds2780_read8(dev_info, control_reg, DS2780_CONTROL_REG);
363 u8 control_reg)
367 ret = ds2780_write(dev_info, &control_reg,
448 u8 control_reg; local
453 ret = ds2780_get_control_register(dev_info, &control_reg);
458 !!(control_reg & DS2780_CONTROL_REG_PMOD));
467 u8 control_reg, new_setting; local
472 ret = ds2780_get_control_register(dev_info, &control_reg);
486 control_reg |
356 ds2780_get_control_register(struct ds2780_device_info *dev_info, u8 *control_reg) argument
362 ds2780_set_control_register(struct ds2780_device_info *dev_info, u8 control_reg) argument
[all...]

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