pci/echoaudio/echoaudio_3g.c

145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
147 	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
151 		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
155 			control_reg |= E3G_SPDIF_SAMPLE_RATE0;
158 		control_reg |= E3G_SPDIF_SAMPLE_RATE1;
163 		control_reg |= E3G_SPDIF_PRO_MODE;
166 		control_reg |= E3G_SPDIF_NOT_AUDIO;
168 	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
171 	return control_reg;
179 	u32 control_reg;
181 	control_reg = le32_to_cpu(chip->comm_page->control_register);
183 	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
184 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
260 	u32 control_reg, clock, base_rate, frq_reg;
277 	control_reg = le32_to_cpu(chip->comm_page->control_register);
278 	control_reg &= E3G_CLOCK_CLEAR_MASK;
303 	control_reg |= clock;
304 	control_reg = set_spdif_bits(chip, control_reg, rate);
319 		"SetSampleRate: %d clock %x\n", rate, control_reg);
322 	return write_control_reg(chip, control_reg, frq_reg, 0);
330 	u32 control_reg, clocks_from_dsp;
334 	control_reg = le32_to_cpu(chip->comm_page->control_register) &
345 		control_reg |= E3G_SPDIF_CLOCK;
347 			control_reg |= E3G_DOUBLE_SPEED_MODE;
349 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
354 		control_reg |= E3G_ADAT_CLOCK;
355 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;
358 		control_reg |= E3G_WORD_CLOCK;
360 			control_reg |= E3G_DOUBLE_SPEED_MODE;
362 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;
371 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
378 	u32 control_reg;
407 	control_reg = le32_to_cpu(chip->comm_page->control_register);
408 	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
413 		control_reg |= E3G_SPDIF_OPTICAL_MODE;
419 		control_reg |= E3G_ADAT_MODE;
420 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */
424 	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);