1117395Skan// SPDX-License-Identifier: GPL-2.0-only 2117395Skan/* 3169689Skan * OMAP DPLL clock support 4117395Skan * 5117395Skan * Copyright (C) 2013 Texas Instruments, Inc. 6117395Skan * 7117395Skan * Tero Kristo <t-kristo@ti.com> 8117395Skan */ 9117395Skan 10117395Skan#include <linux/clk.h> 11117395Skan#include <linux/clk-provider.h> 12117395Skan#include <linux/slab.h> 13117395Skan#include <linux/err.h> 14117395Skan#include <linux/of.h> 15117395Skan#include <linux/of_address.h> 16117395Skan#include <linux/clk/ti.h> 17117395Skan#include "clock.h" 18117395Skan 19169689Skan#undef pr_fmt 20169689Skan#define pr_fmt(fmt) "%s: " fmt, __func__ 21117395Skan 22117395Skan#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 23132718Skan defined(CONFIG_SOC_DRA7XX) 24132718Skanstatic const struct clk_ops dpll_m4xen_ck_ops = { 25117395Skan .enable = &omap3_noncore_dpll_enable, 26117395Skan .disable = &omap3_noncore_dpll_disable, 27117395Skan .recalc_rate = &omap4_dpll_regm4xen_recalc, 28117395Skan .round_rate = &omap4_dpll_regm4xen_round_rate, 29117395Skan .set_rate = &omap3_noncore_dpll_set_rate, 30117395Skan .set_parent = &omap3_noncore_dpll_set_parent, 31117395Skan .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 32117395Skan .determine_rate = &omap4_dpll_regm4xen_determine_rate, 33169689Skan .get_parent = &omap2_init_dpll_parent, 34169689Skan .save_context = &omap3_core_dpll_save_context, 35169689Skan .restore_context = &omap3_core_dpll_restore_context, 36169689Skan}; 37169689Skan#endif 38169689Skan 39169689Skan#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \ 40132718Skan defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \ 41117395Skan defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 42117395Skanstatic const struct clk_ops dpll_core_ck_ops = { 43117395Skan .recalc_rate = &omap3_dpll_recalc, 44117395Skan .get_parent = &omap2_init_dpll_parent, 45117395Skan}; 46132718Skan 47117395Skanstatic const struct clk_ops dpll_ck_ops = { 48117395Skan .enable = &omap3_noncore_dpll_enable, 49117395Skan .disable = &omap3_noncore_dpll_disable, 50117395Skan .recalc_rate = &omap3_dpll_recalc, 51117395Skan .round_rate = &omap2_dpll_round_rate, 52117395Skan .set_rate = &omap3_noncore_dpll_set_rate, 53117395Skan .set_parent = &omap3_noncore_dpll_set_parent, 54117395Skan .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 55117395Skan .determine_rate = &omap3_noncore_dpll_determine_rate, 56117395Skan .get_parent = &omap2_init_dpll_parent, 57169689Skan .save_context = &omap3_noncore_dpll_save_context, 58117395Skan .restore_context = &omap3_noncore_dpll_restore_context, 59117395Skan}; 60117395Skan 61117395Skanstatic const struct clk_ops dpll_no_gate_ck_ops = { 62117395Skan .recalc_rate = &omap3_dpll_recalc, 63117395Skan .get_parent = &omap2_init_dpll_parent, 64117395Skan .round_rate = &omap2_dpll_round_rate, 65117395Skan .set_rate = &omap3_noncore_dpll_set_rate, 66117395Skan .set_parent = &omap3_noncore_dpll_set_parent, 67117395Skan .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 68117395Skan .determine_rate = &omap3_noncore_dpll_determine_rate, 69117395Skan .save_context = &omap3_noncore_dpll_save_context, 70117395Skan .restore_context = &omap3_noncore_dpll_restore_context 71117395Skan}; 72117395Skan#else 73117395Skanstatic const struct clk_ops dpll_core_ck_ops = {}; 74117395Skanstatic const struct clk_ops dpll_ck_ops = {}; 75117395Skanstatic const struct clk_ops dpll_no_gate_ck_ops = {}; 76117395Skanconst struct clk_hw_omap_ops clkhwops_omap3_dpll = {}; 77117395Skan#endif 78117395Skan 79117395Skan#ifdef CONFIG_ARCH_OMAP2 80117395Skanstatic const struct clk_ops omap2_dpll_core_ck_ops = { 81117395Skan .get_parent = &omap2_init_dpll_parent, 82117395Skan .recalc_rate = &omap2_dpllcore_recalc, 83117395Skan .round_rate = &omap2_dpll_round_rate, 84117395Skan .set_rate = &omap2_reprogram_dpllcore, 85117395Skan}; 86117395Skan#else 87117395Skanstatic const struct clk_ops omap2_dpll_core_ck_ops = {}; 88117395Skan#endif 89117395Skan 90169689Skan#ifdef CONFIG_ARCH_OMAP3 91169689Skanstatic const struct clk_ops omap3_dpll_core_ck_ops = { 92117395Skan .get_parent = &omap2_init_dpll_parent, 93117395Skan .recalc_rate = &omap3_dpll_recalc, 94169689Skan .round_rate = &omap2_dpll_round_rate, 95169689Skan}; 96169689Skan 97169689Skanstatic const struct clk_ops omap3_dpll_ck_ops = { 98169689Skan .enable = &omap3_noncore_dpll_enable, 99169689Skan .disable = &omap3_noncore_dpll_disable, 100169689Skan .get_parent = &omap2_init_dpll_parent, 101117395Skan .recalc_rate = &omap3_dpll_recalc, 102117395Skan .set_rate = &omap3_noncore_dpll_set_rate, 103117395Skan .set_parent = &omap3_noncore_dpll_set_parent, 104117395Skan .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 105117395Skan .determine_rate = &omap3_noncore_dpll_determine_rate, 106117395Skan .round_rate = &omap2_dpll_round_rate, 107117395Skan}; 108117395Skan 109117395Skanstatic const struct clk_ops omap3_dpll5_ck_ops = { 110117395Skan .enable = &omap3_noncore_dpll_enable, 111117395Skan .disable = &omap3_noncore_dpll_disable, 112117395Skan .get_parent = &omap2_init_dpll_parent, 113117395Skan .recalc_rate = &omap3_dpll_recalc, 114117395Skan .set_rate = &omap3_dpll5_set_rate, 115117395Skan .set_parent = &omap3_noncore_dpll_set_parent, 116117395Skan .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, 117117395Skan .determine_rate = &omap3_noncore_dpll_determine_rate, 118117395Skan .round_rate = &omap2_dpll_round_rate, 119117395Skan}; 120117395Skan 121169689Skanstatic const struct clk_ops omap3_dpll_per_ck_ops = { 122169689Skan .enable = &omap3_noncore_dpll_enable, 123117395Skan .disable = &omap3_noncore_dpll_disable, 124117395Skan .get_parent = &omap2_init_dpll_parent, 125117395Skan .recalc_rate = &omap3_dpll_recalc, 126117395Skan .set_rate = &omap3_dpll4_set_rate, 127169689Skan .set_parent = &omap3_noncore_dpll_set_parent, 128169689Skan .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, 129117395Skan .determine_rate = &omap3_noncore_dpll_determine_rate, 130117395Skan .round_rate = &omap2_dpll_round_rate, 131117395Skan}; 132117395Skan#endif 133117395Skan 134117395Skan#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 135117395Skan defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 136117395Skan defined(CONFIG_SOC_AM43XX) 137117395Skanstatic const struct clk_ops dpll_x2_ck_ops = { 138117395Skan .recalc_rate = &omap3_clkoutx2_recalc, 139117395Skan}; 140117395Skan#endif 141117395Skan 142117395Skan/** 143117395Skan * _register_dpll - low level registration of a DPLL clock 144169689Skan * @user: pointer to the hardware clock definition for the clock 145169689Skan * @node: device node for the clock 146117395Skan * 147117395Skan * Finalizes DPLL registration process. In case a failure (clk-ref or 148132718Skan * clk-bypass is missing), the clock is added to retry list and 149132718Skan * the initialization is retried on later stage. 150117395Skan */ 151117395Skanstatic void __init _register_dpll(void *user, 152117395Skan struct device_node *node) 153117395Skan{ 154132718Skan struct clk_hw *hw = user; 155132718Skan struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 156132718Skan struct dpll_data *dd = clk_hw->dpll_data; 157132718Skan const char *name; 158132718Skan struct clk *clk; 159132718Skan const struct clk_init_data *init = hw->init; 160132718Skan 161169689Skan clk = of_clk_get(node, 0); 162169689Skan if (IS_ERR(clk)) { 163132718Skan pr_debug("clk-ref missing for %pOFn, retry later\n", 164132718Skan node); 165132718Skan if (!ti_clk_retry_init(node, hw, _register_dpll)) 166132718Skan return; 167132718Skan 168132718Skan goto cleanup; 169132718Skan } 170132718Skan 171117395Skan dd->clk_ref = __clk_get_hw(clk); 172117395Skan 173117395Skan clk = of_clk_get(node, 1); 174117395Skan 175117395Skan if (IS_ERR(clk)) { 176117395Skan pr_debug("clk-bypass missing for %pOFn, retry later\n", 177117395Skan node); 178169689Skan if (!ti_clk_retry_init(node, hw, _register_dpll)) 179169689Skan return; 180117395Skan 181117395Skan goto cleanup; 182117395Skan } 183132718Skan 184132718Skan dd->clk_bypass = __clk_get_hw(clk); 185132718Skan 186132718Skan /* register the clock */ 187132718Skan name = ti_dt_clk_name(node); 188132718Skan clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); 189132718Skan 190132718Skan if (!IS_ERR(clk)) { 191132718Skan of_clk_add_provider(node, of_clk_src_simple_get, clk); 192132718Skan kfree(init->parent_names); 193132718Skan kfree(init); 194132718Skan return; 195169689Skan } 196169689Skan 197132718Skancleanup: 198132718Skan kfree(clk_hw->dpll_data); 199132718Skan kfree(init->parent_names); 200117395Skan kfree(init); 201117395Skan kfree(clk_hw); 202117395Skan} 203117395Skan 204117395Skan#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 205117395Skan defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 206117395Skan defined(CONFIG_SOC_AM43XX) 207117395Skan/** 208117395Skan * _register_dpll_x2 - Registers a DPLLx2 clock 209117395Skan * @node: device node for this clock 210117395Skan * @ops: clk_ops for this clock 211117395Skan * @hw_ops: clk_hw_ops for this clock 212117395Skan * 213117395Skan * Initializes a DPLL x 2 clock from device tree data. 214117395Skan */ 215117395Skanstatic void _register_dpll_x2(struct device_node *node, 216117395Skan const struct clk_ops *ops, 217117395Skan const struct clk_hw_omap_ops *hw_ops) 218117395Skan{ 219117395Skan struct clk *clk; 220117395Skan struct clk_init_data init = { NULL }; 221117395Skan struct clk_hw_omap *clk_hw; 222169689Skan const char *name = ti_dt_clk_name(node); 223169689Skan const char *parent_name; 224169689Skan 225117395Skan parent_name = of_clk_get_parent_name(node, 0); 226117395Skan if (!parent_name) { 227117395Skan pr_err("%pOFn must have parent\n", node); 228117395Skan return; 229117395Skan } 230117395Skan 231117395Skan clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 232117395Skan if (!clk_hw) 233117395Skan return; 234117395Skan 235117395Skan clk_hw->ops = hw_ops; 236117395Skan clk_hw->hw.init = &init; 237117395Skan 238117395Skan init.name = name; 239117395Skan init.ops = ops; 240117395Skan init.parent_names = &parent_name; 241117395Skan init.num_parents = 1; 242169689Skan 243169689Skan#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 244169689Skan defined(CONFIG_SOC_DRA7XX) 245169689Skan if (hw_ops == &clkhwops_omap4_dpllmx) { 246169689Skan int ret; 247169689Skan 248169689Skan /* Check if register defined, if not, drop hw-ops */ 249169689Skan ret = of_property_count_elems_of_size(node, "reg", 1); 250169689Skan if (ret <= 0) { 251169689Skan clk_hw->ops = NULL; 252169689Skan } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { 253169689Skan kfree(clk_hw); 254169689Skan return; 255169689Skan } 256169689Skan } 257169689Skan#endif 258169689Skan 259169689Skan /* register the clock */ 260169689Skan clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); 261169689Skan 262169689Skan if (IS_ERR(clk)) 263169689Skan kfree(clk_hw); 264169689Skan else 265169689Skan of_clk_add_provider(node, of_clk_src_simple_get, clk); 266169689Skan} 267169689Skan#endif 268169689Skan 269169689Skan/** 270169689Skan * of_ti_dpll_setup - Setup function for OMAP DPLL clocks 271169689Skan * @node: device node containing the DPLL info 272169689Skan * @ops: ops for the DPLL 273169689Skan * @ddt: DPLL data template to use 274169689Skan * 275169689Skan * Initializes a DPLL clock from device tree data. 276169689Skan */ 277169689Skanstatic void __init of_ti_dpll_setup(struct device_node *node, 278117395Skan const struct clk_ops *ops, 279117395Skan const struct dpll_data *ddt) 280117395Skan{ 281117395Skan struct clk_hw_omap *clk_hw = NULL; 282169689Skan struct clk_init_data *init = NULL; 283117395Skan const char **parent_names = NULL; 284117395Skan struct dpll_data *dd = NULL; 285117395Skan int ssc_clk_index; 286117395Skan u8 dpll_mode = 0; 287117395Skan u32 min_div; 288117395Skan 289117395Skan dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL); 290117395Skan clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 291117395Skan init = kzalloc(sizeof(*init), GFP_KERNEL); 292169689Skan if (!dd || !clk_hw || !init) 293117395Skan goto cleanup; 294169689Skan 295169689Skan clk_hw->dpll_data = dd; 296117395Skan clk_hw->ops = &clkhwops_omap3_dpll; 297117395Skan clk_hw->hw.init = init; 298117395Skan 299117395Skan init->name = ti_dt_clk_name(node); 300117395Skan init->ops = ops; 301117395Skan 302117395Skan init->num_parents = of_clk_get_parent_count(node); 303117395Skan if (!init->num_parents) { 304117395Skan pr_err("%pOFn must have parent(s)\n", node); 305117395Skan goto cleanup; 306117395Skan } 307117395Skan 308117395Skan parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); 309117395Skan if (!parent_names) 310117395Skan goto cleanup; 311169689Skan 312169689Skan of_clk_parent_fill(node, parent_names, init->num_parents); 313169689Skan 314169689Skan init->parent_names = parent_names; 315169689Skan 316169689Skan if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) 317169689Skan goto cleanup; 318169689Skan 319169689Skan /* 320169689Skan * Special case for OMAP2 DPLL, register order is different due to 321169689Skan * missing idlest_reg, also clkhwops is different. Detected from 322169689Skan * missing idlest_mask. 323169689Skan */ 324169689Skan if (!dd->idlest_mask) { 325169689Skan if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) 326169689Skan goto cleanup; 327169689Skan#ifdef CONFIG_ARCH_OMAP2 328169689Skan clk_hw->ops = &clkhwops_omap2xxx_dpll; 329169689Skan omap2xxx_clkt_dpllcore_init(&clk_hw->hw); 330169689Skan#endif 331169689Skan } else { 332117395Skan if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) 333169689Skan goto cleanup; 334117395Skan 335117395Skan if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) 336117395Skan goto cleanup; 337117395Skan } 338169689Skan 339117395Skan if (dd->autoidle_mask) { 340117395Skan if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) 341117395Skan goto cleanup; 342169689Skan 343117395Skan ssc_clk_index = 4; 344117395Skan } else { 345117395Skan ssc_clk_index = 3; 346169689Skan } 347117395Skan 348117395Skan if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask && 349117395Skan dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) { 350169689Skan if (ti_clk_get_reg_addr(node, ssc_clk_index++, 351117395Skan &dd->ssc_deltam_reg)) 352117395Skan goto cleanup; 353117395Skan 354117395Skan if (ti_clk_get_reg_addr(node, ssc_clk_index++, 355117395Skan &dd->ssc_modfreq_reg)) 356117395Skan goto cleanup; 357117395Skan 358117395Skan of_property_read_u32(node, "ti,ssc-modfreq-hz", 359117395Skan &dd->ssc_modfreq); 360117395Skan of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam); 361117395Skan dd->ssc_downspread = 362117395Skan of_property_read_bool(node, "ti,ssc-downspread"); 363117395Skan } 364117395Skan 365117395Skan if (of_property_read_bool(node, "ti,low-power-stop")) 366117395Skan dpll_mode |= 1 << DPLL_LOW_POWER_STOP; 367117395Skan 368117395Skan if (of_property_read_bool(node, "ti,low-power-bypass")) 369117395Skan dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; 370169689Skan 371169689Skan if (of_property_read_bool(node, "ti,lock")) 372117395Skan dpll_mode |= 1 << DPLL_LOCKED; 373117395Skan 374117395Skan if (!of_property_read_u32(node, "ti,min-div", &min_div) && 375117395Skan min_div > dd->min_divider) 376117395Skan dd->min_divider = min_div; 377117395Skan 378117395Skan if (dpll_mode) 379117395Skan dd->modes = dpll_mode; 380117395Skan 381117395Skan _register_dpll(&clk_hw->hw, node); 382117395Skan return; 383117395Skan 384117395Skancleanup: 385117395Skan kfree(dd); 386117395Skan kfree(parent_names); 387117395Skan kfree(init); 388117395Skan kfree(clk_hw); 389117395Skan} 390117395Skan 391117395Skan#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 392117395Skan defined(CONFIG_SOC_DRA7XX) 393117395Skanstatic void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 394117395Skan{ 395117395Skan _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 396117395Skan} 397117395SkanCLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 398117395Skan of_ti_omap4_dpll_x2_setup); 399117395Skan#endif 400117395Skan 401117395Skan#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 402117395Skanstatic void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 403117395Skan{ 404117395Skan _register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 405117395Skan} 406117395SkanCLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 407117395Skan of_ti_am3_dpll_x2_setup); 408117395Skan#endif 409117395Skan 410117395Skan#ifdef CONFIG_ARCH_OMAP3 411117395Skanstatic void __init of_ti_omap3_dpll_setup(struct device_node *node) 412117395Skan{ 413169689Skan const struct dpll_data dd = { 414169689Skan .idlest_mask = 0x1, 415169689Skan .enable_mask = 0x7, 416169689Skan .autoidle_mask = 0x7, 417169689Skan .mult_mask = 0x7ff << 8, 418117395Skan .div1_mask = 0x7f, 419117395Skan .max_multiplier = 2047, 420169689Skan .max_divider = 128, 421169689Skan .min_divider = 1, 422169689Skan .freqsel_mask = 0xf0, 423169689Skan .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 424169689Skan }; 425169689Skan 426169689Skan if ((of_machine_is_compatible("ti,omap3630") || 427169689Skan of_machine_is_compatible("ti,omap36xx")) && 428169689Skan of_node_name_eq(node, "dpll5_ck")) 429169689Skan of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd); 430169689Skan else 431169689Skan of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd); 432169689Skan} 433169689SkanCLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", 434169689Skan of_ti_omap3_dpll_setup); 435169689Skan 436169689Skanstatic void __init of_ti_omap3_core_dpll_setup(struct device_node *node) 437169689Skan{ 438169689Skan const struct dpll_data dd = { 439169689Skan .idlest_mask = 0x1, 440169689Skan .enable_mask = 0x7, 441169689Skan .autoidle_mask = 0x7, 442169689Skan .mult_mask = 0x7ff << 16, 443169689Skan .div1_mask = 0x7f << 8, 444169689Skan .max_multiplier = 2047, 445169689Skan .max_divider = 128, 446169689Skan .min_divider = 1, 447169689Skan .freqsel_mask = 0xf0, 448169689Skan }; 449169689Skan 450169689Skan of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd); 451169689Skan} 452169689SkanCLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", 453169689Skan of_ti_omap3_core_dpll_setup); 454169689Skan 455169689Skanstatic void __init of_ti_omap3_per_dpll_setup(struct device_node *node) 456169689Skan{ 457169689Skan const struct dpll_data dd = { 458169689Skan .idlest_mask = 0x1 << 1, 459169689Skan .enable_mask = 0x7 << 16, 460169689Skan .autoidle_mask = 0x7 << 3, 461169689Skan .mult_mask = 0x7ff << 8, 462169689Skan .div1_mask = 0x7f, 463169689Skan .max_multiplier = 2047, 464169689Skan .max_divider = 128, 465169689Skan .min_divider = 1, 466169689Skan .freqsel_mask = 0xf00000, 467169689Skan .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 468169689Skan }; 469169689Skan 470169689Skan of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 471169689Skan} 472169689SkanCLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", 473169689Skan of_ti_omap3_per_dpll_setup); 474169689Skan 475169689Skanstatic void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) 476169689Skan{ 477169689Skan const struct dpll_data dd = { 478169689Skan .idlest_mask = 0x1 << 1, 479169689Skan .enable_mask = 0x7 << 16, 480169689Skan .autoidle_mask = 0x7 << 3, 481169689Skan .mult_mask = 0xfff << 8, 482169689Skan .div1_mask = 0x7f, 483169689Skan .max_multiplier = 4095, 484169689Skan .max_divider = 128, 485169689Skan .min_divider = 1, 486169689Skan .sddiv_mask = 0xff << 24, 487169689Skan .dco_mask = 0xe << 20, 488169689Skan .flags = DPLL_J_TYPE, 489169689Skan .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 490169689Skan }; 491169689Skan 492169689Skan of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd); 493169689Skan} 494169689SkanCLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", 495169689Skan of_ti_omap3_per_jtype_dpll_setup); 496169689Skan#endif 497169689Skan 498169689Skanstatic void __init of_ti_omap4_dpll_setup(struct device_node *node) 499169689Skan{ 500169689Skan const struct dpll_data dd = { 501169689Skan .idlest_mask = 0x1, 502169689Skan .enable_mask = 0x7, 503169689Skan .autoidle_mask = 0x7, 504169689Skan .mult_mask = 0x7ff << 8, 505169689Skan .div1_mask = 0x7f, 506169689Skan .max_multiplier = 2047, 507169689Skan .max_divider = 128, 508169689Skan .min_divider = 1, 509169689Skan .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 510169689Skan }; 511169689Skan 512169689Skan of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 513169689Skan} 514169689SkanCLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", 515169689Skan of_ti_omap4_dpll_setup); 516169689Skan 517169689Skanstatic void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) 518169689Skan{ 519169689Skan const struct dpll_data dd = { 520169689Skan .idlest_mask = 0x1, 521169689Skan .enable_mask = 0x7, 522169689Skan .autoidle_mask = 0x7, 523169689Skan .mult_mask = 0x7ff << 8, 524169689Skan .div1_mask = 0x7f, 525169689Skan .max_multiplier = 2047, 526169689Skan .max_divider = 128, 527169689Skan .dcc_mask = BIT(22), 528169689Skan .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ 529169689Skan .min_divider = 1, 530169689Skan .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 531169689Skan }; 532169689Skan 533169689Skan of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 534169689Skan} 535169689SkanCLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", 536169689Skan of_ti_omap5_mpu_dpll_setup); 537169689Skan 538169689Skanstatic void __init of_ti_omap4_core_dpll_setup(struct device_node *node) 539169689Skan{ 540169689Skan const struct dpll_data dd = { 541169689Skan .idlest_mask = 0x1, 542169689Skan .enable_mask = 0x7, 543169689Skan .autoidle_mask = 0x7, 544169689Skan .mult_mask = 0x7ff << 8, 545169689Skan .div1_mask = 0x7f, 546169689Skan .max_multiplier = 2047, 547169689Skan .max_divider = 128, 548169689Skan .min_divider = 1, 549169689Skan .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 550169689Skan }; 551169689Skan 552169689Skan of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 553169689Skan} 554169689SkanCLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", 555169689Skan of_ti_omap4_core_dpll_setup); 556169689Skan 557169689Skan#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 558169689Skan defined(CONFIG_SOC_DRA7XX) 559169689Skanstatic void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) 560169689Skan{ 561169689Skan const struct dpll_data dd = { 562169689Skan .idlest_mask = 0x1, 563169689Skan .enable_mask = 0x7, 564169689Skan .autoidle_mask = 0x7, 565169689Skan .mult_mask = 0x7ff << 8, 566169689Skan .div1_mask = 0x7f, 567169689Skan .max_multiplier = 2047, 568169689Skan .max_divider = 128, 569169689Skan .min_divider = 1, 570169689Skan .m4xen_mask = 0x800, 571169689Skan .lpmode_mask = 1 << 10, 572169689Skan .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 573169689Skan }; 574169689Skan 575169689Skan of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 576169689Skan} 577169689SkanCLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", 578169689Skan of_ti_omap4_m4xen_dpll_setup); 579169689Skan 580169689Skanstatic void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) 581169689Skan{ 582169689Skan const struct dpll_data dd = { 583169689Skan .idlest_mask = 0x1, 584169689Skan .enable_mask = 0x7, 585169689Skan .autoidle_mask = 0x7, 586169689Skan .mult_mask = 0xfff << 8, 587169689Skan .div1_mask = 0xff, 588169689Skan .max_multiplier = 4095, 589169689Skan .max_divider = 256, 590117395Skan .min_divider = 1, 591132718Skan .sddiv_mask = 0xff << 24, 592117395Skan .flags = DPLL_J_TYPE, 593222097Sbenl .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 594117395Skan }; 595117395Skan 596117395Skan of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd); 597132718Skan} 598117395SkanCLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", 599117395Skan of_ti_omap4_jtype_dpll_setup); 600117395Skan#endif 601117395Skan 602117395Skanstatic void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) 603117395Skan{ 604117395Skan const struct dpll_data dd = { 605117395Skan .idlest_mask = 0x1, 606117395Skan .enable_mask = 0x7, 607117395Skan .ssc_enable_mask = 0x1 << 12, 608117395Skan .ssc_downspread_mask = 0x1 << 14, 609117395Skan .mult_mask = 0x7ff << 8, 610117395Skan .div1_mask = 0x7f, 611 .ssc_deltam_int_mask = 0x3 << 18, 612 .ssc_deltam_frac_mask = 0x3ffff, 613 .ssc_modfreq_mant_mask = 0x7f, 614 .ssc_modfreq_exp_mask = 0x7 << 8, 615 .max_multiplier = 2047, 616 .max_divider = 128, 617 .min_divider = 1, 618 .max_rate = 1000000000, 619 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 620 }; 621 622 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 623} 624CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", 625 of_ti_am3_no_gate_dpll_setup); 626 627static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) 628{ 629 const struct dpll_data dd = { 630 .idlest_mask = 0x1, 631 .enable_mask = 0x7, 632 .mult_mask = 0x7ff << 8, 633 .div1_mask = 0x7f, 634 .max_multiplier = 4095, 635 .max_divider = 256, 636 .min_divider = 2, 637 .flags = DPLL_J_TYPE, 638 .max_rate = 2000000000, 639 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 640 }; 641 642 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 643} 644CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", 645 of_ti_am3_jtype_dpll_setup); 646 647static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) 648{ 649 const struct dpll_data dd = { 650 .idlest_mask = 0x1, 651 .enable_mask = 0x7, 652 .mult_mask = 0x7ff << 8, 653 .div1_mask = 0x7f, 654 .max_multiplier = 2047, 655 .max_divider = 128, 656 .min_divider = 1, 657 .max_rate = 2000000000, 658 .flags = DPLL_J_TYPE, 659 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 660 }; 661 662 of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd); 663} 664CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, 665 "ti,am3-dpll-no-gate-j-type-clock", 666 of_ti_am3_no_gate_jtype_dpll_setup); 667 668static void __init of_ti_am3_dpll_setup(struct device_node *node) 669{ 670 const struct dpll_data dd = { 671 .idlest_mask = 0x1, 672 .enable_mask = 0x7, 673 .ssc_enable_mask = 0x1 << 12, 674 .ssc_downspread_mask = 0x1 << 14, 675 .mult_mask = 0x7ff << 8, 676 .div1_mask = 0x7f, 677 .ssc_deltam_int_mask = 0x3 << 18, 678 .ssc_deltam_frac_mask = 0x3ffff, 679 .ssc_modfreq_mant_mask = 0x7f, 680 .ssc_modfreq_exp_mask = 0x7 << 8, 681 .max_multiplier = 2047, 682 .max_divider = 128, 683 .min_divider = 1, 684 .max_rate = 1000000000, 685 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 686 }; 687 688 of_ti_dpll_setup(node, &dpll_ck_ops, &dd); 689} 690CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); 691 692static void __init of_ti_am3_core_dpll_setup(struct device_node *node) 693{ 694 const struct dpll_data dd = { 695 .idlest_mask = 0x1, 696 .enable_mask = 0x7, 697 .mult_mask = 0x7ff << 8, 698 .div1_mask = 0x7f, 699 .max_multiplier = 2047, 700 .max_divider = 128, 701 .min_divider = 1, 702 .max_rate = 1000000000, 703 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 704 }; 705 706 of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd); 707} 708CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", 709 of_ti_am3_core_dpll_setup); 710 711static void __init of_ti_omap2_core_dpll_setup(struct device_node *node) 712{ 713 const struct dpll_data dd = { 714 .enable_mask = 0x3, 715 .mult_mask = 0x3ff << 12, 716 .div1_mask = 0xf << 8, 717 .max_divider = 16, 718 .min_divider = 1, 719 }; 720 721 of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd); 722} 723CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock", 724 of_ti_omap2_core_dpll_setup); 725