Lines Matching refs:control_reg
119 u32 control_reg;
152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
153 err = write_control_reg(chip, control_reg, true);
200 u32 control_reg, clock;
246 control_reg = le32_to_cpu(chip->comm_page->control_register);
247 control_reg &= GML_CLOCK_CLEAR_MASK;
248 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
263 if (control_reg & GML_SPDIF_PRO_MODE)
288 control_reg |= clock;
295 return write_control_reg(chip, control_reg, force_write);
302 u32 control_reg, clocks_from_dsp;
306 control_reg = le32_to_cpu(chip->comm_page->control_register) &
323 control_reg |= GML_SPDIF_CLOCK;
325 control_reg |= GML_DOUBLE_SPEED_MODE;
327 control_reg &= ~GML_DOUBLE_SPEED_MODE;
336 control_reg |= GML_WORD_CLOCK;
338 control_reg |= GML_DOUBLE_SPEED_MODE;
340 control_reg &= ~GML_DOUBLE_SPEED_MODE;
346 control_reg |= GML_ADAT_CLOCK;
347 control_reg &= ~GML_DOUBLE_SPEED_MODE;
356 return write_control_reg(chip, control_reg, true);
363 u32 control_reg;
392 control_reg = le32_to_cpu(chip->comm_page->control_register);
393 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
398 control_reg |= GML_SPDIF_OPTICAL_MODE;
410 control_reg |= GML_ADAT_MODE;
411 control_reg &= ~GML_DOUBLE_SPEED_MODE;
415 err = write_control_reg(chip, control_reg, false);