Lines Matching refs:control_reg
162 u32 control_reg, clock, base_rate;
179 control_reg = le32_to_cpu(chip->comm_page->control_register);
180 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
197 if (control_reg & GML_SPDIF_PRO_MODE)
222 control_reg |= GML_DOUBLE_SPEED_MODE;
240 control_reg |= clock;
245 "set_sample_rate: %d clock %d\n", rate, control_reg);
247 return write_control_reg(chip, control_reg, false);
254 u32 control_reg, clocks_from_dsp;
257 control_reg = le32_to_cpu(chip->comm_page->control_register) &
269 control_reg |= GML_SPDIF_CLOCK;
271 control_reg &= ~GML_DOUBLE_SPEED_MODE;
274 control_reg |= GML_WORD_CLOCK;
276 control_reg |= GML_DOUBLE_SPEED_MODE;
278 control_reg &= ~GML_DOUBLE_SPEED_MODE;
283 control_reg |= GML_ADAT_CLOCK;
284 control_reg &= ~GML_DOUBLE_SPEED_MODE;
293 return write_control_reg(chip, control_reg, true);
335 u32 control_reg;
373 control_reg = le32_to_cpu(chip->comm_page->control_register);
374 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
378 control_reg |= GML_SPDIF_OPTICAL_MODE;
384 control_reg |= GML_ADAT_MODE;
385 control_reg &= ~GML_DOUBLE_SPEED_MODE;
389 err = write_control_reg(chip, control_reg, true);